KR20060001126A - Method for isolation in semiconductor device - Google Patents

Abstract

The present invention is to provide a device isolation method of a semiconductor device suitable for preventing the occurrence of the moat at the boundary between the device isolation layer and the active region, the device isolation method of the present invention is defined silicon of the cell region and the peripheral circuit region Forming a pad pattern having a triple structure stacked in the order of an oxide film, a nitride film, and an oxide film on the substrate; forming a trench by etching the silicon substrate using the pad pattern as an etching barrier; and forming the trench until the trench fills the trench. Forming a gap fill insulating film on the pattern, partially etching a portion of the gap fill insulating film formed on the cell region, and performing a first CMP process of polishing the gap fill insulating film until the nitride film of the pad pattern is exposed; The second CMP process is performed to further planarize while removing the nitride film remaining after the first CMP process. Step, and a step to proceed with a wet etching for adjusting the height between the gaeppil insulating film and the silicon substrate.

Device Isolation, Trench, Mouth, Pad Nitride, CMP, Touch CMP, Wet Etching

Description

Device Separation Method for Semiconductor Devices {METHOD FOR ISOLATION IN SEMICONDUCTOR DEVICE}             

1A to 1E schematically illustrate a device isolation method of a semiconductor device according to the prior art;

2 is a view showing a state of occurrence of a moat according to the prior art,

3A to 3F are cross-sectional views illustrating a device isolation method of a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 silicon substrate 22a first pad oxide film

22b: second pad oxide film 23: pad nitride film

24a, 24b: trench 25g, 25h: gap fill insulating film

26: cell area open mask

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a device isolation method for semiconductor devices.

In addition to the advancement of semiconductor technology, high speed and high integration of semiconductor devices is progressing. In connection with this, the necessity of refinement | miniaturization of a pattern becomes increasingly high, and the dimension of a pattern is also required for high precision. This also applies to device isolation regions that occupy a wide area in semiconductor devices.

As the device isolation (ISO) process of the semiconductor device, the LOCOS process is mostly used. However, the LOCOS type device isolation process has a drawback in that a bird-shaped bird's beak is generated at an edge thereof, thereby generating a leakage current while reducing the area of the active region.

At present, a shallow trench isolation (STI) process having a narrow width and excellent device isolation characteristics has been proposed.

In the STI process, the semiconductor substrate is etched by plasma etching to form a trench to define an isolation region and an active region.

As described above, the device isolation region and the active region react sensitively according to the process conditions during the oxidation and etching processes of the subsequent processes, and the device characteristics vary according to the boundary portions and the step difference between the two regions.

1A to 1E schematically illustrate a device isolation method of a semiconductor device according to the prior art.                         

As shown in FIG. 1A, after forming the pad oxide film 12 and the pad nitride film 13 on the silicon substrate 11 in which the cell region and the peripheral region are defined, the device isolation mask is formed on the pad nitride film 13. (Not shown) is formed.

Next, the pad nitride film 13 is etched using the device isolation mask as an etching barrier, and the device isolation mask is removed. Then, using the pad nitride film 13 as an etching barrier, the pad oxide film 12 is etched to expose the surface of the silicon substrate 11, and the subsequently exposed silicon substrate 11 is etched to a predetermined depth to form trenches 14a, 14b). At this time, the width of the trench 14b formed in the peripheral region is larger than that of the trench 14a formed in the cell region.

As shown in FIG. 1B, a gap fill insulating film 15 is deposited on the pad nitride film 13 until the trenches 14a and 14b are filled. At this time, a step occurs between the cell region and the peripheral region.

As shown in FIG. 1C, the gap fill insulating film 15 is chemically mechanical polished (CMP) until the surface of the pad nitride film 13 is exposed. At this time, the first gap fill insulating film 15a remains in the trench 14a of the cell region, and the second gap fill insulating film 15b remains in the trench 14b of the peripheral region.

As illustrated in FIG. 1D, the pad nitride film 13 is removed from the phosphoric acid (H ₃ PO ₄ ) solution.

As shown in FIG. 1E, subsequent wet etching is performed. At this time, all of the pad oxide film 12 is removed, and a portion of the first and second gap fill insulating films 15a and 15b is also etched to lower the height of the pad region.

However, the prior art has a problem in that a moat (Mat) M, which becomes lower than an active region, occurs at the corner of each gap fill insulating layer as the subsequent wet etching proceeds isotropically.

Figure 2 is a view showing a state of generating the moat according to the prior art, the moist occurs because the subsequent wet etching proceeds isotropic etching (X).

The above-mentioned moat becomes deeper by various cleaning processes performed before the subsequent gate oxide film formation, and when this moat becomes deeper, the threshold voltage decreases due to electric field concentration at the edge of the active region and the width of the active region decreases (CD). loss and gate electrode residual in the moat. As a result, the electrical properties and yield of the device are deteriorated.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a device separation method of a semiconductor device suitable for preventing the occurrence of the moat at the boundary between the device isolation layer and the active region.

The device isolation method of the present invention for achieving the above object is to form a pad pattern of a triple structure stacked in the order of an oxide film, a nitride film and an oxide film on the silicon substrate defined in the cell region and the peripheral circuit region, the pad pattern Forming a trench by etching the silicon substrate using an etching barrier; forming a gap fill insulating layer on the pad pattern until the trench is filled; partially etching a portion of the gap fill insulating layer formed on the cell region; Performing a first CMP process of polishing the gap fill insulating layer until the nitride film of the pad pattern is exposed, proceeding a second CMP process to further planarize while removing the nitride film remaining after the first CMP process, and the gap fill And performing wet etching to match the height between the insulating film and the silicon substrate. The first CMP process is characterized by using an optional slurry for selectively polishing the top oxide film and the gap fill insulating film in the pad pattern, wherein the selective slurry has a polishing selectivity ratio of 1:40 to 1:50. The second CMP process is characterized by using a slurry in which the polishing selectivity of the nitride film to the oxide film is 1: 1.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3A to 3F are cross-sectional views illustrating a device isolation method of a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 3A, the first pad oxide layer 22a, the pad nitride layer 23, and the second pad oxide layer 22b are sequentially stacked on the silicon substrate 21 on which the cell region and the peripheral circuit region are defined. do. That is, the pad structure is formed of a triple structure, for example, an oxide / nitride / oxide (ONO) structure having a sandwich structure stacked in the order of an oxide film / nitride film / oxide film. Alternatively, a multi-structure in which an oxide film and a nitride film are alternately stacked several times is also applicable.

In the pad having the above-described triple structure, the first pad oxide film 22a and the second pad oxide film 22b are formed to have a thickness of 50 kPa to 200 kPa, and the pad nitride film 23 is formed thin to 20 kPa to 50 kPa.

Next, a photoresist pattern (not shown) defining an isolation region is formed on the second pad oxide film 22b. Subsequently, the second pad oxide layer 22b, the pad nitride layer 23, and the first pad oxide layer 22a are sequentially etched using the photoresist pattern as an etching barrier to expose the surface of the silicon substrate 21 on which the trench is to be formed. After the tripple pad pattern is formed, the photoresist pattern is removed. Here, the triple pad pattern is stacked in the order of the first pad oxide film 22a, the pad nitride film 23, and the second pad oxide film 22b.

Next, the trenches 24a and 24b are formed by etching the silicon substrate 21 exposed by the triple pad pattern as an etching barrier to a depth of 1500 to 4000 microseconds. At this time, the trenches 24a and 24b are formed in both the cell region and the peripheral circuit region. As is well known, the width of the trench 24b formed in the peripheral circuit region is larger than that of the trench 24a formed in the cell region. Big. This is mainly because transistors formed in the cell region are dense as compared with the peripheral circuit region.

As shown in FIG. 3B, a gap fill insulating film 25 is formed on the entire surface until the trenches 24a and 24b are filled. Here, the gap fill insulating film 25 is an oxide film deposited by a high density plasma (High Density Plasma) method.

Next, a photoresist film is coated on the gap fill insulating film 25 and patterned by exposure and development to form a cell region open mask 26 covering the peripheral circuit area and opening the cell area.

As shown in FIG. 3C, the gap fill insulating layer 25 on the cell region exposed by the cell region open mask 26 is partially etched to lower the step difference. As a result of etching the gap fill insulating film 25 using the cell area open mask 26, the gap fill insulating film 25a formed in the peripheral area remains as it is, and the gap fills a portion of the cell area by etching so that the step is lowered by 'd'. The insulating film 25b remains.

The gap fill insulating film 25b of the cell region having a lower step prevents the triple pad pattern of the peripheral circuit region from being excessively polished during the subsequent CMP process. For example, when the CMP process is performed immediately after the gap fill insulating film on the cell region is lowered without lowering the level, the peripheral circuit region is excessively polished while the cell region is polished compared to the relatively thick deposited cell region, which is the triple pad of the peripheral circuit region. This results in the problem of missing patterns.

As shown in FIG. 3D, after removing the cell region open mask 26, a CMP process is performed to planarize the gap fill insulating films 25a and 25b. At this time, the CMP process proceeds until the surface of the pad nitride film 23 is exposed. For this purpose, a selective slurry for selectively polishing only the gap fill insulating films 25a and 25b and the second pad oxide film 22b, which are oxide films, is selected. Use Here, the selective slurry is used in the polishing selectivity of the nitride film to the oxide film is 1:40 to 1:50, as known, the polishing selectivity is known to be adjustable at the time of slurry production.

After the above CMP process, the gap fill insulating films 25c and 25d remain lower in the cell region and the peripheral region, respectively.

As shown in FIG. 3E, a CMP process using a general slurry (slurry having no polishing selectivity of oxide and nitride) is performed in order to remove the pad nitride film 23a remaining after the CMP process and to achieve planarization. . The above CMP process is called a "touch CMP" process. Accordingly, the gap fill insulating films 25c and 25d are also removed at the same polishing rate when the pad nitride film 23a is removed.

As described above, after all of the remaining pad nitride film 23a is removed, the remaining gap fill insulating films 25e and 25f are relatively low in height before proceeding with the subsequent wet etching. That is, although the conventional pad nitride film is formed very thick for the purpose of forming trenches and for the purpose of CMP, the moist has occurred due to relatively excessive etching during subsequent wet etching, but the present invention provides the pad nitride film for the purpose of CMP. As the thickness is very thin, the etching amount of the gap fill insulating layer to be etched during the wet etching is relatively small. This prevents the moat from occurring.

As shown in FIG. 3F, a subsequent wet etching process is performed to lower the step between the gap fill insulating layer and the active region while removing the first pad oxide layer 22a remaining after the pad nitride layer 23 is removed. At this time, the wet etching process uses a hydrofluoric acid (HF) solution.

In the wet etching process, the gap fill insulating films 25e and 25f and the first pad oxide film 22a are the same oxide film, and the first pad oxide film 22a, which is a thermal oxide film, and the HDP type gap fill insulating film 25e, Since there is little difference in the wet etch rate of 25f), the wet etching process can be performed without generating a moat.

Finally, gap fill insulating films 25g and 25h in which no moat is generated remain in the trenches of the cell region and the peripheral region.

On the other hand, in order to maintain the same wet etching rate between the first pad oxide film 22a and the gap fill insulating films 25e and 25f, an annealing process (500 ° C. to 900 ° C. and rapid heat treatment) may be performed before the wet etching process. It is known that the wet etch rate between the first pad oxide film 22a and the gap fill insulating films 25e and 25f is slightly faster than that of the HDP type gap fill insulating films 25e and 25f.

Alternatively, when considering the difference in wet etching rates between the first pad oxide layer 22a and the gap fill insulating layers 25c and 25d, the touch CMP process may be omitted by selectively removing only the pad nitride layer 23a remaining after the CMP process. have. Therefore, after the pad nitride film 23a is removed, the gap fill insulating film remains higher than the first pad oxide film, so that the gap fill insulating film progresses a little faster during the subsequent wet etching process, thereby exposing the active region without generating a moat and simultaneously forming the gap fill insulating film 25e, 25f).

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has an effect of improving the electrical characteristics of the device because it prevents the generation of the moat during the cleaning step performed before the gate oxide film process.

Claims (7)

Forming a pad pattern having a triple structure on the silicon substrate defined in the cell region and the peripheral circuit region in the order of an oxide film, a nitride film, and an oxide film; Etching the silicon substrate using the pad pattern as an etching barrier to form a trench; Forming a gap fill insulating layer on the pad pattern until the trench is filled; Etching a portion of the gap fill insulating layer formed over the cell region; Performing a first CMP process of polishing the gap fill insulating layer until the nitride layer of the pad pattern is exposed; Performing a second CMP process to further planarize while removing the nitride film remaining after the first CMP process; And Performing wet etching to match the height between the gap fill insulating layer and the silicon substrate Device isolation method of a semiconductor device comprising a. The method of claim 1, The first CMP process And an optional slurry for selectively polishing the oxide film on the top of the pad pattern and the gap fill insulating film. The method of claim 2, The selective slurry is a device isolation method of a semiconductor device, characterized in that the polishing selectivity of the nitride film to the oxide film is 1:40 to 1:50. The method of claim 1, The second CMP process, A device isolation method for a semiconductor device, comprising using a slurry having a polishing selectivity of nitride to oxide film of 1: 1. The method of claim 1, After the second CMP process, And an annealing process for equalizing the wet etch rate between the oxide film and the gap fill insulating film in the pad pattern. The method of claim 5, The annealing step is a rapid thermal treatment at 500 ℃ to 900 ℃ device separation method of a semiconductor device. The method of claim 1, In the step of forming the pad pattern of the triple structure, And the oxide films are formed in a thickness of 50 kV to 200 kV and the nitride films are formed in a thickness of 20 kV to 50 kV.

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