KR20060001053A - Phase-change memory device and method for manufacturing the same - Google Patents

Abstract

The present invention discloses a phase change memory device capable of reducing the amount of current by reducing the contact area between the lower electrode and the phase change film and a method of manufacturing the same. Disclosed is a semiconductor substrate having a lower pattern; An interlayer insulating film formed on the semiconductor substrate to cover the lower pattern; A contact plug formed in the interlayer insulating film; A lower electrode formed on the contact plug and having a barrier film thereon; A first oxide layer formed on the interlayer insulating layer on the side of the lower electrode to contact the lower electrode; A second oxide film formed on the first oxide film to expose an upper portion of the lower electrode side surface; A phase conversion film formed on the barrier film, the first oxide film, and the second oxide film to contact the exposed lower electrode side upper portion; And an upper electrode formed on the phase conversion film.

Description

 Phase change memory device and its manufacturing method {PHASE-CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a diagram for explaining a method of programming and erasing a phase change memory cell.

2 is a diagram for explaining a conventional phase change memory cell.

3 is a cross-sectional view illustrating a phase change memory device according to an embodiment of the present invention.

4A to 4F are cross-sectional views of steps for explaining a method of manufacturing a phase change memory device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

21 semiconductor substrate 22 interlayer insulating film

23 contact plug 24 lower electrode

25: first barrier film 26: first oxide film

27: second oxide film 28: phase change film

29: upper electrode 30: second barrier film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase change memory device and a method of manufacturing the same, and more particularly, to a phase change memory device capable of reducing the amount of current by reducing the contact area between a lower electrode and a phase change film and a method of manufacturing the same.

Recently, flash memory devices having a feature in which stored data are not destroyed even when a power supply is cut off have been adopted. Such flash memory devices include a tunnel oxide film, a floating gate, an inter-gate dielectric layer, and a control gate electrode, which are sequentially stacked on a channel. Therefore, in order to improve the reliability and program efficiency of the flash memory devices, the film quality of the tunnel oxide film should be improved and the coupling ratio of the cell should be increased.

In addition, new nonvolatile memory devices have recently been proposed in place of flash memory devices. For example, these devices are phase-change memory devices, and store information by using electric resistance difference according to a phase change, and the chalcogenide alloy material (Ge2Sb2Te5) thin film is changed from an amorphous state to a crystalline state. Phase transformation results in lower resistance and activation energy when in the crystalline state, and higher long-range atomic order and free electron density. The advantages of the phase change memory device are easy to fabricate with Soc (System On Chip), and low production cost among next generation memory semiconductors. The processing speed of the phase change memory device is very fast, 5ns, low power consumption, and a wide range of operating temperature of -196 to 180 ° C.

1 is a diagram for describing a method of programming and erasing a phase change memory cell.                         

As shown in FIG. 1, when the phase conversion thin film is heated after cooling during a first operation (T1) at a temperature higher than a melting temperature (Tm), the phase conversion thin film is in an amorphous state. State) (A). On the other hand, after the phase conversion thin film is heated for a second operation longer than the first operation T1 at a temperature lower than the melting temperature Tm and higher than the crystallization temperature Tc, the second operation T2 is performed. Upon cooling, the phase change material film changes to a crystalline state (B). Here, the specific resistance of the phase change thin film having an amorphous state is higher than that of the phase change thin film having a crystalline state.

Accordingly, by detecting the current flowing through the phase change thin film in a read mode, it is possible to determine whether the information stored in the phase change memory cell is logic '1' or logic '0'. As the phase change thin film, a compound film containing a germanium (Ge), stevilium (Sb), and tellurium (Te) (Compound Material Layer; hereinafter referred to as a GST film) is widely used.

2 is a diagram for describing a conventional phase change memory cell.

As shown in FIG. 2, the conventional phase change memory device forms an interlayer insulating film 5 on a semiconductor substrate 1 including a lower electrode 3. Next, the interlayer insulating layer 5 is etched to form the contact plug 7 electrically connected to the source regions, and then the phase change layer 9 is formed on the substrate product including the contact plug 7. Subsequently, an upper electrode 11 is formed on the phase conversion film 9.                         

When a voltage is applied to program the phase change memory cell, heat is generated at the interface between the phase change film 9 and the contact plug 7 to change the portion 9a of the phase change film into an amorphous state. The heat of the edge C of the phase conversion film 9 and the contact plug 7 may diffuse into the surrounding interlayer insulating film 7 and may not be a temperature necessary for changing the state. As a result, when the phase conversion film is amorphous, abnormal regions in which the edge of the phase conversion film 9 is not amorphous may be generated.

In addition, since the contact area between the lower electrode and the phase conversion film is large during read and write operations of the phase change memory device, the amount of current required for phase change increases, thereby affecting the speed of the phase change memory device. Will give.

Accordingly, an object of the present invention is to provide a phase change memory device and a method of manufacturing the same, which reduce the amount of current by reducing the contact area between the lower electrode and the phase conversion film. .

The present invention for achieving the above object is a semiconductor substrate provided with a lower pattern; An interlayer insulating film formed on the semiconductor substrate to cover the lower pattern; A contact plug formed in the interlayer insulating film; A lower electrode formed on the contact plug and having a barrier film thereon; A first oxide layer formed on the interlayer insulating layer on the side of the lower electrode to contact the lower electrode; A second oxide film formed on the first oxide film to expose an upper portion of the lower electrode side surface; A phase conversion film formed on the barrier film, the first oxide film, and the second oxide film to contact the exposed lower electrode side upper portion; And an upper electrode formed on the phase conversion film.

Here, the barrier layer formed on the upper electrode is characterized in that it further comprises.

The lower electrode and the upper electrode may be made of a polysilicon film or a metal film.

In addition, the present invention comprises the steps of providing a semiconductor substrate having a lower pattern; Forming an interlayer insulating film on the semiconductor substrate to cover the lower pattern; Forming a contact plug in the interlayer insulating film; Forming a lower electrode on the contact plug, the lower electrode having a barrier film thereon; Forming a first oxide film having a uniform thickness on the lower electrode and the interlayer insulating film; Forming a second oxide film on the first oxide film, the second oxide film having an etching speed that is at least two times slower than the first oxide film; Polishing the second oxide film and the first oxide film to expose the barrier film; Partially etching the first oxide layer and the second oxide layer to expose the upper side surface of the lower electrode; Forming a phase conversion film on the barrier film, the remaining first oxide film, and the second oxide film to be in contact with the exposed lower electrode side surface; And forming an upper electrode on the phase conversion film.

Here, the first oxide film is characterized in that it is made of any one selected from the group consisting of SOG, PSG, TEOS, BPSG, USG, HLD and HDP oxide film.

The upper electrode is characterized in that it comprises a barrier film on the top.                     

The lower electrode and the upper electrode may be made of a polysilicon film or a metal film.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view illustrating a phase change memory device according to an embodiment of the present invention.

As shown in FIG. 3, in the phase change memory device of the present invention, an interlayer insulating film 22 is formed on a semiconductor substrate 21 having a lower pattern (not shown) to cover the lower pattern. A contact plug 23 is formed in 22. A lower electrode 24 is formed on the contact plug 23 and includes a first barrier layer 25 thereon. The first oxide layer 26 is formed on the interlayer insulating layer 22 on the side of the lower electrode 24 to contact the lower electrode 24. The phase change layer 28 is formed on the first barrier layer 25, the first oxide layer 26, and the second oxide layer 27 to contact the upper side of the lower electrode 24 on the first oxide layer 26. do. An upper electrode 29 is formed on the phase change layer 28, and a second barrier layer 30 is formed on the upper electrode 29.

The lower electrode 24 and the upper electrode 29 are preferably formed of a polysilicon film or a metal film. The first oxide layer 26 is preferably made of any one selected from the group consisting of SOG, PSG, TEOS, BPSG, USG, HLD and HDP oxide. The first oxide layer 26 may be formed of an oxide layer having an etching selectivity at least two times faster than that of the second oxide layer 27. The phase conversion film 28 is preferably formed of Ge1Sb2Te4 and Ge2Sb2Te.

When heat is generated at the contact surface of the phase change layer 28 during read and write operations of the phase change memory device, the state of the phase change layer changes to an amorphous state or a crystalline state. In the phase change memory device of the present invention, the phase change film 28 is formed on the first barrier film 25, the first oxide film 26, and the second oxide film 27 to form the lower electrode 24 and the phase change film ( Since the contact area D of 28) is small, the current required for phase change can be reduced, so that the speed of the phase change memory element can be improved.

4A through 4F are cross-sectional views of processes for describing a method of manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

As shown in FIG. 4A, a semiconductor substrate 21 having a lower pattern (not shown) is provided. Next, an interlayer insulating film 22 is formed on the semiconductor substrate to cover the lower pattern, and a contact plug 23 is formed in the interlayer insulating film 22.

As shown in FIG. 4B, a lower electrode 24 having a first barrier layer 25 is formed on the contact plug 23.

As shown in FIG. 4C, a first oxide layer 26 is formed on the lower electrode 24 and the interlayer insulating layer to have a uniform thickness. At this time, the first oxide layer 26 is made of any one selected from the group consisting of SOG, PSG, TEOS, BPSG, USG, HLD and HDP oxide. Subsequently, a second oxide film 27 is formed on the first oxide film 26. Here, the first oxide layer 26 is formed of an oxide layer having an etching rate that is at least twice as fast as that of the second oxide layer 27.

As shown in FIG. 4D, the surfaces of the second oxide layer 27 and the first oxide layer 26 are CMP to expose the first barrier layer 25.

As shown in FIG. 4E, the first oxide layer 26 and the second oxide layer 27 are partially etched using an etchant or a gas so that the upper side of the lower electrode 27 is exposed. . In this case, since the etching selectivity of the second oxide layer 27 is lower than that of the first oxide layer 26, the second oxide layer 27 is etched by a predetermined thickness, and the first oxide layer 26 is formed of an interlayer insulating film ( 22) It remains to a certain thickness on the top.

As shown in FIG. 4F, a phase change layer is formed on the first barrier layer 25 and the remaining first oxide layer 26 and the second oxide layer 27 so as to be in contact with the exposed upper side of the lower electrode 27. Form 28. Here, the phase change film 28 is formed of Ge1Sb2Te4 and Ge2Sb2Te. Next, an upper electrode 29 and a second barrier film 30 are formed on the phase change film 28. In this case, the lower electrode 27 and the upper electrode 29 are formed of a polysilicon film or a metal film.

As described above, the present invention can reduce the contact area between the lower electrode and the phase change film by forming the phase change film to contact only the sidewall of the lower electrode when manufacturing the phase change memory device, thereby reducing the amount of current required for the phase change. You can.

In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person of ordinary skill in the art may make many modifications and variations without departing from the spirit of the present invention. I will understand that.

As described above, the present invention can reduce the contact area between the phase change film and the lower electrode by forming the phase change film to contact only the sidewall of the lower electrode in order to facilitate the phase change of the phase change film. The amount of current required for change can be reduced.

Therefore, the speed of the phase conversion memory element can be improved by reducing the amount of current required for phase conversion.

Claims (7)

A semiconductor substrate having a lower pattern; An interlayer insulating film formed on the semiconductor substrate to cover the lower pattern; A contact plug formed in the interlayer insulating film; A lower electrode formed on the contact plug and having a barrier film thereon; A first oxide layer formed on the interlayer insulating layer on the side of the lower electrode to contact the lower electrode; A second oxide film formed on the first oxide film to expose an upper portion of the lower electrode side surface; A phase conversion film formed on the barrier film, the first oxide film, and the second oxide film to contact the exposed lower electrode side upper portion; And And an upper electrode formed on the phase change film. The phase change memory device as claimed in claim 1, further comprising a barrier film formed on the upper electrode. The phase change memory device as claimed in claim 1, wherein the lower electrode and the upper electrode are made of a polysilicon film or a metal film. Providing a semiconductor substrate having a lower pattern formed thereon; Forming an interlayer insulating film on the semiconductor substrate to cover the lower pattern; Forming a contact plug in the interlayer insulating film; Forming a lower electrode on the contact plug, the lower electrode having a barrier film thereon; Forming a first oxide film having a uniform thickness on the lower electrode and the interlayer insulating film; Forming a second oxide film on the first oxide film, the second oxide film having an etching speed that is at least two times slower than the first oxide film; Polishing the second oxide film and the first oxide film to expose the barrier film; Partially etching the first oxide layer and the second oxide layer to expose the upper side surface of the lower electrode; Forming a phase conversion film on the barrier film, the remaining first oxide film, and the second oxide film to be in contact with the exposed lower electrode side surface; And And forming an upper electrode on the phase change film. The method of claim 4, wherein the first oxide film is one selected from the group consisting of SOG, PSG, TEOS, BPSG, USG, HLD, and HDP oxide. 5. The method of claim 4, wherein the upper electrode has a barrier film thereon. 5. The method of claim 4, wherein the lower electrode and the upper electrode are made of a polysilicon film or a metal film.

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