KR20050117964A - Shift register - Google Patents

Abstract

Shift registers having transistors for minimizing parasitic capacitance are disclosed. Each stage of the shift register includes a buffer unit, a charging unit for charging a scan start signal or an output signal of a previous stage, a driver for outputting an output signal in response to a first clock or a second clock, and a discharge for discharging the charged charges. Contains wealth. Here, the buffer unit includes a control electrode pattern, a transistor comprising a first current electrode line formed in a plurality of finger shapes on the control electrode pattern, and a second current electrode line formed in a plurality of finger shapes while being spaced apart from the first current electrode line. It is provided. Accordingly, by minimizing the parasitic capacitance of the buffer transistor provided in the buffer unit, it is possible to remove the interference of the gate-source parasitic capacitance of the buffer transistor to improve the driving capability of the pull-up transistor provided in the driver unit.

Description

Shift register {SHIFT REGISTER}

The present invention relates to a shift register, and more particularly to a shift register having a transistor for minimizing parasitic capacitance.

In general, efforts are being made to integrate data driver ICs or gate driver ICs into liquid crystal panels to meet cost reduction demands and narrow bezel market demands. In order to realize the integration, it is necessary to simplify the circuit of a scan driving circuit composed of an amorphous-silicon thin film transistor (hereinafter, referred to as a-Si TFT).

FIG. 1 is a diagram for explaining a general shift register. In particular, FIG. 1 is a diagram for explaining a scan driving circuit.

As shown in FIG. 1, a scan driving circuit for generating a gate pulse for activating a gate line of a liquid crystal panel includes one shift register, and the unit stage of the shift register is equivalent to one SR latch. It may be composed of one end gate.

In operation, the SR latch is activated by the output signal of the previous stage, is deactivated by the output signal of the next stage, and the gate is gate gate when the SR latch is activated and the clock CKV is at a high level. Or a scan signal).

The method of implementing the unit stage of the shift register as an a-Si TFT is various, and the simplest configuration is as shown in FIG. 2.

FIG. 2 is a diagram for describing a unit stage of the shift register of FIG. 1. 1 and 2, the unit stage of the shift register includes a buffer unit 10, a charging unit 20, a driving unit 30, and a discharging unit 40, and thus the scan start signal STV or the previous stage. A gate signal (or scan signal) is output based on the output signal.

In detail, the buffer unit 10 has a drain and a gate in common, and receives a first input signal IN1, and a source includes a buffer transistor Q1 connected to one end of the charging unit 20.

One end of the charging unit 20 is formed of a capacitor C connected to the source and the discharge unit 40 of the buffer transistor Q1 and the other end connected to the driving unit 30.

The driving unit 30 has a drain connected to the clock terminal CK, a gate connected to one end of the capacitor C via the first node N1, and a source connected to the other end of the capacitor C and the output terminal OUT. The pull-up transistor Q2 is connected to the source and the drain is connected to the source of the second transistor Q2 and the other end of the capacitor C, and the source is composed of a pull-down transistor Q3 connected to the first power supply voltage VOFF. The clock terminal CK is applied with a first clock CKV or a second clock CKVB having a phase opposite to that of the first clock CK.

In the discharge unit 40, a drain is connected to one end of the capacitor C, a gate is common to the gate of the pull-down transistor Q3, and is connected to the second input signal IN2, and the source is connected to the first power voltage VOFF. Is made up of a discharge transistor Q4. The second input signal IN2 is an output signal of the next stage and is a kind of reset signal.

In operation, the scan start signal STV or the gate signal of the previous stage is charged to the capacitor C via the buffer transistor Q1 to turn on the pull-up transistor Q2. Then, the clock CKV is output to the output terminal connected to the gate line load via the channel of the pull-up transistor Q2. Therefore, it is preferable that the pull-up transistor Q2 has a maximum current driving capability, and for this purpose, it is necessary to maximize the gate voltage.

Therefore, since the buffer transistor Q1 is the only path capable of charging the capacitor C to the maximum voltage, the channel width should be maximized when the buffer transistor Q1 is designed.

However, even when the channel width of the buffer transistor Q1 is maximized to maximize the charging voltage of the capacitor, when the node N1 is boosted by the capacitor C, between the gate and the source of the buffer transistor Q1. There is a problem that the driving capability of the pull-up transistor Q2 is not improved due to the interference of parasitic capacitance present in the circuit.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a shift register having a buffer transistor having a minimized parasitic capacitance.

According to one aspect of the present invention, a shift register includes a buffer unit, a charging unit, a driving unit, and a discharge unit in a shift register in which a plurality of stages are connected to sequentially output output signals. . The buffer unit includes a buffer transistor including a first current electrode formed in a plurality of finger shapes on the U-shaped control electrode pattern, and a second current electrode formed in a plurality of finger shapes while being spaced apart from the first current electrode. The scan start signal or the output signal of the preceding stage is supplied. One end of the charging unit is connected to the output terminal of the buffer unit to charge the scan start signal or the output signal of the front end stage. The driver outputs an output signal in response to a clock in response to charging of the charger. The discharge unit discharges the charged charge in response to the output signal of one of the following stages.

According to another aspect of the present invention, a shift register includes a plurality of stages connected, a first scan stage is provided with a scan start signal to an input terminal, and sequentially outputs output signals of each stage. In the shift register, the odd stages are provided with a first clock, and the even side stages are provided with a second clock that is out of phase with the first clock. Each of the stages may include a buffer unit receiving the scan start signal or the output signal of the previous stage, a charging unit configured to charge the scan start signal or the output signal of the previous stage, one end of which is connected to an output terminal of the buffer unit, and the charging unit The charging unit may include a driver configured to output an output signal in response to the first clock or the second clock, and a discharge unit configured to discharge the charged charge in response to an output signal of one of the following stages. The buffer unit may include a control electrode pattern defining a predetermined region, a first current electrode line extending from an outside of the control electrode pattern to form a plurality of finger shapes on the control electrode pattern, and extending from an outside of the control electrode pattern to control the control electrode pattern. A first transistor is spaced apart from the first current electrode line on an electrode pattern, and includes a second current electrode line formed in a plurality of finger shapes.

According to such a shift register, by minimizing the parasitic capacitance of the buffer transistor provided in the buffer unit, it is possible to improve the driving capability of the pull-up transistor provided in the driving unit by eliminating the interference of the gate-source parasitic capacitance of the buffer transistor. .

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

FIG. 3 is a diagram for explaining a buffer transistor according to an exemplary embodiment of the present invention. In particular, FIG. 3 illustrates a buffer transistor of a shift register employed in a gate driving circuit of a liquid crystal display.

Referring to FIG. 3, a buffer transistor according to an embodiment of the present invention is formed on a transparent substrate 105 to define a predetermined region, and a gate electrode pattern 110 extending from an outside of the gate electrode pattern 110 so as to extend the gate. A drain electrode line 130 formed in a plurality of finger shapes on the electrode pattern 110 and extended from an outer side of the gate electrode pattern 110 and spaced apart from the drain electrode line 130 on the gate electrode pattern 110. And a source electrode line 140 formed in a plurality of finger shapes. Here, for convenience of description, only the metal electrode portion is shown, and illustrations of the gate insulating film, the semiconductor layer, and the impurity semiconductor layer formed on the gate electrode pattern are omitted.

That is, the gate electrode pattern 110 formed on the transparent substrate 105 defines a U-shape, and the drain electrode line 130 or the source electrode line 140 formed on the gate electrode pattern 110 are staggered from each other. Is formed. In view of the observer, the source electrode line 140 is formed to surround the drain electrode line 130.

Specifically, the drain electrode line 130 branches from the body-drain line 132, the hand-drain line 134 branched from the body-drain line 132, and the hand-drain line 134. Finger-drain line 136. The body-and hand-drain lines 132 are formed in regions where the gate electrode patterns 110 are not formed, and the finger-drain lines 136 are formed in regions where the gate electrode patterns 110 are formed.

On the other hand, the source electrode line 140 is a body-source line 142, a hand-source line 144 branched from the body-source line 142, and the hand-source line 144 branched from Finger-source line 146. The body-source line 142, the hand-source line 144, and the finger-source line 146 are formed in a region where the gate electrode pattern 110 is formed.

According to the result, the finger-drain line 136 is formed while defining an I-shape on the gate electrode pattern 110, and the hand- and finger-source lines 144 and 146 are formed on the gate electrode pattern 110. It is formed in a shape surrounding the finger-drain line 136 while defining a U shape from above. The channel length L of the formed a-Si thin film transistor is the distance between the outermost side of the finger-drain line 136 and the outermost side of the finger-source line 146, and the channel width W is the hand-side. And the U-shaped average distance defined by the finger-source line and the finger-drain line 136.

As such, when n finger-drain lines 136 or finger-source lines 146 are formed in order to form a large-capacity a-Si thin film transistor, a channel width corresponding to nx 4 [μm] is obtained by a separate parasitic capacitance (Cgd). Can be formed without increase. Specifically, when the length of each short finger structure is designed to be 4 [μm], which is the minimum design-rule, the outer three sides of the finger-drain line 136 are defined as channels so that 3 x 4 [μm] of channels are defined. Form. In this case, as much as 4 [μm], the parasitic capacitance Cgd is independent of the parasitic capacitance.

Next, a method of manufacturing an a-Si thin film transistor, particularly a buffer transistor, for minimizing parasitic capacitance will be described.

4 to 7 are cross-sectional views of the a-Si thin film transistor of FIG. 3, in particular, FIG. 4 is a cross-sectional view taken along line II ′, FIG. 5 is a cross-sectional view taken along line II-II ′, and FIG. It is sectional drawing cut by -III ', FIG. 7 is sectional drawing cut by IV-IV'.

4 to 7, after depositing a metal including aluminum on the transparent substrate 105, the aluminum metal layer is patterned to form a low resistance gate electrode pattern 110. In the drawings, a single metal layer is used as the gate electrode pattern, but multiple metal layers may be used as the gate electrode pattern. In the case of using the multiple metal layer, a metal such as chromium (Cr) or molybdenum (Mo) is further deposited on the aluminum metal layer.

Subsequently, an insulating material such as silicon oxide or silicon nitride is entirely deposited on the transparent substrate 105 on which the gate electrode pattern 110 is formed, and then a semiconductor material including intrinsic semiconductor material and impurities is sequentially deposited.

Subsequently, the insulating material, the intrinsic semiconductor material, and the semiconductor material to which impurities are added are etched to form a gate insulating film 112, a semiconductor layer (or an amorphous-silicon layer, a-Si: H) 114, and a semiconductor to which impurities are added. A layer (or n + doped layer, n + a-Si: H) 116 is formed. As a result, the gate insulating layer 112 covers the entire gate electrode pattern 110, and the semiconductor layer 114 and the impurity semiconductor layer 116 have the same shape as the gate insulating layer 112. 112).

Subsequently, a metal layer such as chromium or a chromium alloy is deposited on the substrate on which the semiconductor layer 114 and the impurity semiconductor layer 116 are formed.

Next, the metal layer is patterned to form a drain electrode line 130 defining an I shape and a source electrode line 140 defining a U shape on the gate electrode pattern 110.

Specifically, the drain electrode line 130 branches from the body-drain line 132, the hand-drain line 134 branched from the body-drain line 132, and the hand-drain line 134. And the source electrode line 140 to the body-source line 142, and the hand-source line 144 branched from the body-source line 142. And pattern the finger-source line 146 branching from the hand-source line 144.

In this case, the body-drain line 132 is patterned to be formed in the region where the gate electrode pattern 110 is not formed, and the hand-drain line 134 and the finger-drain line 136 are formed in the gate electrode pattern ( 110 is patterned to be formed in the formed region. In addition, the body-source line 142 and the hand-source line 144 are patterned so that the gate electrode pattern 110 is formed in an unformed region, and the finger-source line 146 is the gate electrode pattern 110. ) Is patterned to be formed in the formed region.

In particular, the finger-drain line 136 branching from the drain electrode line 130 and the finger-source line 146 branching from the source electrode line 140 are formed to be adjacent to each other on the same plane.

In addition, the impurity semiconductor layer 116 between the drain electrode line 130 and the source electrode line 140 is completely separated by using the drain electrode line 130 and the source electrode line 140 as a mask. do.

Subsequently, an insulating material such as silicon nitride or silicon oxide is deposited on the entire surface of the substrate on which the drain electrode line 130 and the source electrode line 140 are formed to form a passivation layer 150.

In the above, in order to operate the buffer transistor as a kind of diode, a part of the gate insulating film formed on the gate electrode is removed to expose the gate electrode, and then the connection is performed when the drain electrode is formed. 8, a portion of the organic layer 160 formed on the passivation layer 150 may be removed to expose the drain electrode and the gate electrode, and then may be connected through the pixel electrode.

Of course, if the structure does not employ the organic layer described above, a portion of the passivation layer 150 may be removed to expose the drain electrode and the gate electrode, and the exposed region may be connected through the pixel electrode.

3 to 7 illustrate an inverted staggered type in which a gate electrode pattern is formed on a transparent substrate and a drain electrode line and a source electrode line are formed on the gate electrode pattern. However, the same applies to a staggered type structure in which a drain electrode line and a source electrode line are formed on a transparent substrate and a gate electrode pattern is formed on the drain electrode line and the source electrode line.

Further, in the above embodiments, only a-Si thin film transistors for minimizing parasitic capacitance are shown in the drawings, but a liquid crystal display panel or a liquid crystal display using a shift register employing the a-Si thin film transistor or the shift register as a gate driver. The same applies to the apparatus, and description thereof will be omitted.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

As described above, according to the present invention, a plurality of stages are connected to a plurality of U-shaped control electrode patterns to minimize parasitic capacitance of the buffer transistor provided in each stage of the shift register for sequentially outputting output signals. And a first current electrode formed in a finger shape and a second current electrode formed in a plurality of finger shapes while being spaced apart from the first current electrode. Accordingly, it is possible to improve the driving capability of the pull-up transistor included in the driving unit by removing the interference of the gate-source parasitic capacitance of the buffer transistor.

1 is a diagram for explaining a general shift register.

FIG. 2 is a diagram for describing a unit stage of the shift register of FIG. 1.

3 is a diagram for describing a buffer transistor according to an exemplary embodiment of the present invention.

FIG. 4 is an example of sectional drawing which cut the transistor of FIG.

5 is a cross-sectional view taken along line II-II ′ of the transistor of FIG. 3.

6 is a cross-sectional view taken along line III-III ′ of the transistor of FIG. 3.

FIG. 7 is a cross-sectional view taken along line IV-IV ′ of the transistor of FIG. 3.

FIG. 8 is another example of a cross-sectional view taken along the line II ′ of the transistor of FIG. 3.

<Description of the symbols for the main parts of the drawings>

110: gate electrode pattern 130: drain electrode line

132: body-drain line 134: hand-drain line

136 finger-drain line 140 source electrode line

142: body-source line 144: hand-source line

146 finger-source lines

Claims (13)

In a shift register in which a plurality of stages are connected to sequentially output output signals, Each of the stages, A buffer transistor comprising a first current electrode formed in a plurality of finger shapes on the U-shaped control electrode pattern and a second current electrode formed in a plurality of finger shapes while being spaced apart from the first current electrode, thereby starting scanning A buffer unit receiving a signal or an output signal of a front end stage; A charging unit having one end connected to an output terminal of the buffer unit to charge the scan start signal or an output signal of a front end stage; A driving unit outputting an output signal in response to a clock according to charging of the charging unit; And And a discharge unit for discharging the charged charge in response to an output signal of one of next stages. The method of claim 1, wherein the first current electrode, A first body line extending from an outside of the control electrode pattern; A first hand-line branched from the first body-line and formed on the control electrode pattern; And And a first finger line formed on the control electrode pattern while branching from the first hand line. The method of claim 2, wherein the second current electrode, A second body line extending from an outside of the control electrode pattern; A second hand-line branching out of the second body-line; And And a second finger line formed on the control electrode pattern while branching from the second hand line. 4. The shift register according to claim 3, wherein the sum of the distances between the outer side of the first hand-line and the outer side of the second finger-line defines the channel length of the buffer transistor. 4. The apparatus of claim 3, further comprising: a first region formed by an outer side of the first hand-line and an outer side of the second finger-line, and an outer side of the first finger-line connected to the first region; And a second region formed by an outer side of the second finger-line, and a second region formed by an outer other side of the first finger-line and an outer side of the second finger-line while being connected to the first region. And a sum of the average distances of the three regions defines the channel width of the buffer transistor. A plurality of stages are connected, the first stage is provided with a scan start signal to the input terminal, in the shift register to sequentially output the output signals of each stage, Odd-numbered stages are provided with a first clock, even-numbered stages are provided with a second clock that is out of phase with the first clock, Each of the stages, A buffer unit configured to receive the scan start signal or the output signal of a previous stage; A charging unit having one end connected to an output terminal of the buffer unit to charge the scan start signal or an output signal of a front end stage; A driving unit outputting an output signal in response to the first clock or the second clock according to the charging of the charging unit; And A discharge unit for discharging the charged charge in response to an output signal of one of next stages, The buffer unit may include a control electrode pattern defining a predetermined region, a first current electrode line extending from an outside of the control electrode pattern to form a plurality of finger shapes on the control electrode pattern, and extending from an outside of the control electrode pattern to control the control electrode pattern. And a first transistor spaced apart from the first current electrode line on an electrode pattern, the first transistor comprising a second current electrode line formed in a plurality of finger shapes. The shift register of claim 6, wherein the control electrode and the first current electrode of the first transistor are connected in common. The method of claim 6, wherein the driving unit A second transistor having a first current electrode connected to a clock terminal, a gate connected to one end of the charging unit via a first node, and a second current electrode connected to the other end of the charging unit and an output terminal; And And a third transistor having a first current electrode connected to the second current electrode of the second transistor and the other end of the charging unit, and a second transistor connected to the first power voltage. The method of claim 8, wherein the discharge part has a first current electrode connected to one end of the charging part, a control electrode is connected to a second input signal in common with a control electrode of a third transistor, and a second current electrode is connected to the first input electrode. A shift register comprising a fourth transistor connected to a power supply voltage. The method of claim 6, wherein the first current electrode line, A first body line extending from an outside of the control electrode pattern; A first hand-line branched from the first body-line and formed on the control electrode pattern; And And a first finger line formed on the control electrode pattern while branching from the first hand line. The method of claim 10, wherein the second current electrode line, A second body line extending from an outside of the control electrode pattern; A second hand-line branching out of the second body-line; And And a second finger line formed on the control electrode pattern while branching from the second hand line. 12. The shift register according to claim 11, wherein the sum of the distances between the outer side of the first hand-line and the outer side of the second finger-line defines the channel length of the first transistor. 12. The apparatus of claim 11, further comprising: a first region formed by an outer side of the first hand-line and an outer side of the second finger-line, and an outer side of the first finger-line connected to the first region; And a second region formed by an outer side of the second finger-line, and a second region formed by an outer other side of the first finger-line and an outer side of the second finger-line while being connected to the first region. And a sum of the average distances of the three regions defines the channel width of the first transistor.