KR20070096571A - Gate driver circuit - Google Patents

Abstract

A gate driving circuit is provided to prevent a light leakage current and prevent a defective operation by forming a semiconductor layer of a transistor in an area within an area corresponding to a gate electrode so that the semiconductor layer is covered with the gate electrode. A pull-up unit(210) includes a first transistor(T1), and outputs a gate signal based on a signal of a clock terminal to an output terminal in response to a signal of an input terminal. A shift resister is dependently connected with a stage including a pull-down unit(230) outputting a ground voltage to the output terminal in response to a next-terminal gate signal. The first transistor includes a first gate electrode on a substrate, a first semiconductor layer formed on the first gate electrode within an area corresponding to the first gate electrode, a first source electrode formed on the first semiconductor layer, and a first drain electrode formed on the first semiconductor layer and spaced apart from the first source electrode at a predetermined interval.

Description

Gate driver circuit {GATE DRIVER CIRCUIT}

1 is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a detailed block diagram of the gate driving circuit shown in FIG. 1.

3 is a detailed circuit diagram of the stage shown in FIG.

4 is a diagram for describing a gate driving circuit according to a first embodiment of the present invention.

Ⅰ-Ⅰ'선을 따라 자른 단면도이다.5 is a view of FIG. 4

This is a cross-sectional view taken along the line I-I '.

6 is a diagram for describing a gate driving circuit according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view taken along the line II-II ′ of FIG. 6.

FIG. 8 is a cross-sectional view taken along line III-III ′ of FIG. 6.

<Description of the symbols for the main parts of the drawings>

410: gate electrode 412: gate insulating film

420: semiconductor layer 422: active layer

424: ohmic contact layer 430: source electrode

432: hand source electrode 434: finger source electrode

436: body source electrode 440: drain electrode

442, hand drain electrode 444: finger drain electrode

450: protective layer 452: drain contact hole

454: drain contact portion 460: connection wiring

470: authorization wiring 472: clock contact hole

474: clock contact

The present invention relates to a gate driving circuit, and more particularly to a gate driving circuit for improving a drive failure.

In general, a liquid crystal display device is a flat panel display device that displays a desired image by adjusting a light transmittance that varies depending on the intensity of an electric field by using a liquid crystal having an anisotropic dielectric constant.

The liquid crystal display device includes a display panel in which a plurality of pixel portions are formed by crossing gate lines and data lines, a gate driving circuit for driving the gate lines, and a data driving circuit for driving the data lines. The gate driving circuit and the data driving circuit are generally formed in a chip form and mounted on a display panel.

Recently, in order to increase productivity while reducing the overall size of a liquid crystal display, a method of integrating a gate driving circuit on an array substrate of a display panel in the form of an integrated circuit has been attracting attention. The gate driving circuit includes a shift register having a plurality of stages connected to each other, and each stage includes a plurality of transistors and includes a pull-up unit, a pull-down unit, and a carry unit, and outputs a gate signal in one-to-one correspondence with the gate wiring. .

As described above, the gate driving circuit integrated in the display panel exposes a semiconductor layer to light emitted from the backlight disposed on the back of the display panel, causing photo leakage current to occur in the transistors, thereby causing abnormal operation. It is even more pronounced at improved high temperature driving conditions. In particular, due to the photo-leakage current generated in the transistors of the pull-up part and the carry part, noise defects in which an abnormal high level signal appears in a low level section of the gate signal may occur, thereby degrading image quality.

Accordingly, an object of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a gate driving circuit and a display device having the same for improving image quality by improving driving failure.

According to an embodiment of the present invention, a gate driving circuit includes a pull-up part and a next gate signal outputting a gate signal based on a signal of a clock terminal as an output terminal in response to a signal of an input terminal. In response, the stage including a pull-down unit for outputting a ground voltage to the output terminal includes a shift register connected to each other. A first gate electrode formed on the substrate, a first semiconductor layer formed on the first gate electrode in a region corresponding to the first gate electrode, a first source electrode formed on the first semiconductor layer and the And a first transistor including a first drain electrode formed on the first semiconductor layer and spaced apart from the first source electrode by a predetermined distance.

According to still another aspect of the present invention, there is provided a gate driving circuit including a pull-up unit configured to output a gate signal based on a signal of a clock terminal to an output terminal in response to a signal of an input terminal; The stage including a carry part for outputting a carry signal based on the signal of the clock terminal to an input terminal of a next stage stage in response to a signal and a pull-down part for outputting a ground voltage to the output terminal in response to a next gate signal. It contains cascaded shift registers. A pull-down portion comprising: a gate electrode formed on the substrate; a semiconductor layer formed on the gate electrode in a region corresponding to the gate electrode; a drain electrode formed on the semiconductor layer in a region corresponding to the gate electrode; And a transistor formed on the source electrode and the drain electrode spaced apart from each other by a predetermined interval, and including a connection wire electrically connecting the drain electrode and the application wire extended from the clock terminal.

According to such a gate driving circuit, the driving failure caused by the light leakage current can be improved by blocking the light irradiated to the semiconductor layer of the transistor.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display panel 100, a gate driving circuit 200, and a data driver 130.

The display panel 100 includes an array substrate 110 and an opposing substrate 120 (for example, a color filter substrate) facing each other at a predetermined interval, and a liquid crystal layer interposed between the array substrate 110 and the opposing substrate 120. , The display area DA and the peripheral area PA surrounding the display area DA. In the display area DA, a plurality of pixel parts are formed by intersecting gate lines GL and data lines DL. Each pixel unit includes a thin film transistor TFT that is a switching element, a liquid crystal capacitor CLC, and a storage capacitor CST that are electrically connected to the thin film transistor TFT. Specifically, the gate electrode and the source electrode of the thin film transistor TFT are electrically connected to the gate line GL and the data line DL, respectively, and the pixel electrode forming the liquid crystal capacitor CLC and the storage capacitor CST at the drain electrode. And a storage electrode (not shown) are electrically connected.

The peripheral area PA includes a first peripheral area PA1 positioned at one end of the data lines DL and a second peripheral area PA2 positioned at one end of the gate lines GL.

The data driving circuit 130 outputs a data signal to the data lines DL in synchronization with the gate signal applied to the gate line GL, and includes at least one data driving chip 132. The data driving chip 132 is mounted on the flexible circuit board 134 having one end connected to the first peripheral area PA1 of the display panel 100 and the other end connected to the printed circuit board 140. The substrate 134 is electrically connected to the printed circuit board 134 and the display panel 100.

The gate driving circuit 200 is an integrated circuit integrated in the second peripheral area PA2 of the display panel 100. The gate driving circuit 200 is formed of a shift register in which a plurality of stages are connected in succession to sequentially apply a gate signal to the gate lines GL. Output

FIG. 2 is a detailed block diagram of the gate driving circuit shown in FIG. 1.

1 and 2, the gate driving circuit 200 includes a shift register CS including a plurality of stages SRC1 to SRCn + 1 connected in a cascade manner.

The shift register CS includes n + 1 stages SRC1 to SRCn + 1, and the n + 1 stages SRC1 to SRCn + 1 include n driving stages SRC1 to SRCn and one dummy. ) Stages SRCn + 1 to sequentially output the first to nth gate signals GOUT1 to GOUTn.

Each stage includes a first clock terminal CK1, a second clock terminal CK2, a first input terminal IN1, a second input terminal IN2, a power supply terminal V, a reset terminal RE, and a carry terminal ( CR) and an output terminal OUT, and a power supply terminal V is provided with a ground voltage VSS.

The first clock signal CK and the second clock signal CKB are provided to the first clock terminal CK1 and the second clock terminal CK2, respectively, or the second clock signal CKB and the first clock signal CK are provided. Are provided respectively. Specifically, the first clock signal CK is provided to the first clock terminal CK1 of the odd-numbered stages among the plurality of stages SRC1 to SRCn + 1, and the second clock signal CKB is provided to the second clock terminal CK2. ) Is provided. The second clock signal CKB is provided to the first clock terminal CK1 of the even-numbered stage among the plurality of stages SRC1 to SRCn + 1, and the first clock signal CK is supplied to the second clock terminal CK2. Is provided. Here, the first clock signal CK and the second clock signal CKB are opposite in phase.

The first input terminal IN1 receives a vertical start signal STV or a carry signal of a previous stage. In detail, a vertical start signal STV provided externally is provided to the first input terminal IN1 of the first stage SRC1 in which the front stage does not exist, and the first input of the remaining stages SRC2 to SRCn + 1. The terminal IN1 is provided with a carry signal output at the front end stage. That is, the carry signals output from the first to nth stages SRC1 to SRCn are respectively provided to the first input terminals IN1 of the second to n + 1th stages SRC2 to SRCn + 1.

The second input terminal IN2 receives a gate signal or a vertical start signal output from the next stage. Specifically, the vertical start signal STV is provided to the second input terminal IN2 of the last stage SRCn + 1 where the next stage does not exist, and the second input terminal IN2 of the remaining stages SRC1 to SRCn is provided. Is provided with a gate signal output at the next stage. That is, the gate signals GOUT2 to GOUTn + 1 output from the second to n + 1th stages SRC2 to SRCn + 1 are applied to the second input terminals IN2 of the first to nth stages SRC1 to SRCn. Is provided.

The reset terminal RE is provided with a carry signal output from the n + 1 stage SRCn + 1 which is the last stage.

The carry terminal CR and the output terminal OUT may output a carry signal and a gate signal GOUT based on the first clock signal CK or the second clock signal CKB provided to the first clock terminal CK1, respectively. . Specifically, the carry terminal CR and the output terminal OUT of the odd-numbered stages among the plurality of stages SRC1 to SRCn + 1 are output by the carry signal and the gate signal GOUT based on the first clock signal CK. do. The carry terminal CR and the output terminal OUT of the even-numbered stages among the plurality of stages SRC1 to SRCn + 1 are outputted with a carry signal and a gate signal GOUT based on the second clock signal CKB.

Meanwhile, the gate driving circuit 200 further includes a wiring part LS formed on one side of the shift register to provide a synchronization signal and a driving voltage to the plurality of stages SRC1 to SRCn + 1, and the wiring part LS ) Includes a start signal wiring SL1, a first clock wiring SL2, a second clock wiring SL3, a power supply wiring SL4, and a reset wiring SL5.

The start signal line SL1 receives a vertical start signal STV from the outside, and applies the vertical start signal STV to the first input terminal IN1 and the n + 1 stage SRCn + 1 of the first stage SRC1. To the second input terminal IN2.

The first clock signal CK is applied to the first clock wire SL2 from the outside, and the first clock signal CK is applied to the first clock terminal CK1 of the odd-numbered stage and the second clock terminal of the even-numbered stage ( CK2).

The second clock wire SL3 is supplied with a second clock signal CKB having a phase opposite to that of the first clock signal CK from the outside, and receives the second clock signal CKB from the second clock terminal of the odd-numbered stage. CK2) and the first clock terminal CK1 of the even-numbered stages.

The power supply line SL4 is applied with the ground voltage VSS from the outside, and the reset wiring SL5

Provides a carry signal output from the n + 1th stage SRCn + 1, which is the last stage, to the reset terminal RE of each stage.

3 is a detailed circuit diagram of the stage shown in FIG.

Here, since the plurality of stages have the same configuration, the first stage is taken as an example and description of the remaining stages will be omitted.

2 to 4, the first stage SRC1 of the gate driving circuit 200 according to the exemplary embodiment of the present invention may include a buffer unit 240, a charging unit 250, a pull-up unit 210, and a pull-down unit ( 230, a discharge part 280, a first holding part 260, a second holding part 270, and a carry part 220.

In the buffer unit 240, a drain (or a first current electrode) and a gate (or a control electrode) are commonly connected to the first input terminal IN1 to receive a signal of the first input terminal (hereinafter, referred to as a first input signal). The source (or second current electrode) includes a fourth transistor T4 connected to one end of the charging unit 250 to form the first node N1.

The buffer unit 250 operates as a diode and provides a high level signal to the first node N1 based on the first input signal. That is, the ninth transistor T9 is turned on in synchronization with the vertical start signal STV to provide a high level signal to the first node N1. Meanwhile, in the second to n + 1th stages SRC2 to SRCn + 1, the buffer unit 250 receives the gate signal of the previous stage as the first input signal.

The charging unit 250 includes a first capacitor C1 having one end connected to the source of the fourth transistor T4 to form the first node N1 and the other end connected to the output terminal OUT. The charging unit 250 charges the high level signal provided from the buffer unit 240 to the first capacitor C1 to maintain the first node N1 at the high level.

The pull-up unit 210 has a drain connected to the first clock terminal CK1, a gate connected to one end of the third capacitor C3 to form a first node N1, and a source of the third capacitor C3. The first transistor T1 is connected to the other end and the output terminal OUT. The pull-up unit 210 outputs to the output terminal OUT based on the first clock signal CK or the second clock signal CKB provided to the first clock terminal CK1 in response to the signal of the first node N1. The high level gate signal GOUT is output. That is, the odd-numbered stage outputs the gate signal GOUT based on the first clock signal CK, and the even-numbered stage outputs the gate signal GOUT based on the second clock signal CKB.

The pull-down unit 230 has a drain connected to the output terminal OUT and a gate connected to the second input terminal IN2 to receive a signal (hereinafter, referred to as a second input signal) of the second input terminal IN2. Includes a third transistor T3 connected to the power supply terminal V to receive a ground voltage VSS. The pull-down unit 230 outputs the ground voltage VSS to the output terminal OUT in response to the second input signal. That is, the ground voltage VSS is output to the output terminal OUT by turning on the second input signal during the high level.

The discharge unit 280 includes a thirteenth transistor T13 and a fourteenth transistor T14, and discharges the charge charged in the charger 260 to the power terminal V in response to the second input signal. In addition, in response to the carry signal output from the last stage SRCn + 1, the electric charges charged in the charging unit 250 are discharged to the power supply terminal V for the second time.

In detail, the drain of the thirteenth transistor T13 is connected to the second input terminal IN2, and the source thereof is connected to the power supply terminal V. The fourteenth transistor T14 has a drain connected to the first node N1, a gate connected to a reset terminal RE, and receives a carry signal of the last stage SRCn + 1, and a source of the power supply terminal V )

The first holding part 260 includes fifth, sixth, seventh, and eighth transistors T5, T6, T7, and T8, and second and third capacitors C2 and C3.

The fifth transistor T5 has a drain and a gate in common and is connected to the first clock terminal CK1, a source is connected to a drain of the sixth transistor T6, and a gate of the sixth transistor T6 has an output terminal ( OUT), and the source is connected to the power supply terminal (V). A drain of the seventh transistor T7 is connected to the first clock terminal CK1, and a gate thereof is connected to the source of the fifth transistor T5 and the drain of the sixth transistor T6. A drain of the eighth transistor T8 is connected to the source of the seventh transistor T7 to form a second node N2, and a gate thereof is connected to the output terminal OUT in common with the gate of the sixth transistor T6. , The source is connected to the power supply terminal (V). The second capacitor C2 is connected between the drain and the gate of the seventh transistor T7, and the third capacitor C3 is connected between the gate and the source of the seventh transistor T7.

The first holding part 260 controls the operation of the second holding part 270 through the signal of the second node N2.

In detail, a control voltage synchronized with the signal of the first clock terminal CK1 is provided to the second node N2 through the seventh transistor T7, and when the signal of the output terminal OUT is at a high level, The eighth transistor T8 is turned on and the second node N2 is at a low level. That is, except when the signal of the output terminal OUT is at the high level, a control voltage synchronized with the signal of the first clock terminal CK1 is provided to the second node N2, and the signal of the output terminal OUT is supplied. In the high level, the second node N2 becomes a low level.

The second holding part 270 includes the ninth, tenth, eleventh, and twelfth transistors T9, T10, T11, and T12. In the ninth transistor T9, a drain is connected to the output terminal OUT, a gate is connected to the second node N2, and is connected to the first holding part 260, and a source is connected to the power supply terminal V. . In the tenth transistor T10, a drain is connected to the first input terminal IN1, a gate is connected to the second clock terminal CK2, and a source is connected to the first node N1. A drain of the eleventh transistor T11 is connected to the first node N1, a gate thereof is connected to the first clock terminal CK1, and a source thereof is connected to the output terminal OUT. The drain of the twelfth transistor T12 is connected to the output terminal OUT, the gate is connected to the second clock terminal CK2 in common with the gate of the tenth transistor T10, and the source is connected to the power supply terminal V. Connected.

 Here, the clock signal applied to the second clock terminal CK2 is opposite in phase to the clock signal applied to the first clock terminal CK1. That is, when the first clock signal CK is provided to the first clock terminal CK1, the second clock signal CKB is provided to the second clock terminal CK2, and the second clock is supplied to the first clock terminal CK1. When the signal CKB is provided, the first clock signal CK is provided to the second clock terminal CK2.

The second holding unit 270 maintains the output terminal OUT at a low level after the operation of the pull-down unit 230. That is, the ground voltage VSS is output to the output terminal OUT in response to the low level period of the gate signal, and the ground voltage VSS is also provided to the first node N1 to turn off the pull-up unit 210. Hold operation to perform the hold operation.

Specifically, when the signal of the first clock terminal CK1 is at the high level, the second node N2 is at the high level, and the ground voltage VSS is turned on by the turn-on operation of the ninth transistor T9. OUT) is output. In addition, since the eleventh transistor T11 is turned on by the signal of the first clock terminal CK1, the ground voltage VSS of the output terminal OUT is provided to the first node N1, and thus, the first transistor T1. ) Is turned off. When the signal of the first clock terminal CK1 is at the low level, since the signal of the second clock terminal CK2 is at the high level, the twelfth transistor T12 is turned on to operate the ground voltage VSS. OUT) is output. That is, in the low level period of the gate signal, the ninth and twelfth transistors T9 and T12 are alternately turned on after the pull-down unit 230 operates to output the ground voltage VSS to the output terminal OUT. Maintain a low level.

The carry part 220 includes a second transistor, a drain of which is connected to the first clock terminal CK1, a gate of which is connected to the first node N1, and a source of the second transistor T2. CR). The carry unit 220 outputs a carry signal based on the signal of the first clock terminal CK1 to the carry terminal CR in response to the signal of the first node N1.

Here, the carry unit 280 outputs a carry signal based on a signal of the first clock terminal CK1 which is electrically isolated from the output terminal OUT and is not affected. Therefore, even if the signal of the output terminal OUT is distorted, a normal carry signal is output and provided to the next stage to induce normal operation.

Ⅰ-Ⅰ'선을 따라 자른 단면도이다.FIG. 4 is a diagram illustrating a gate driving circuit according to a first embodiment of the present invention, and illustrates a transistor layout of a stage illustrated in FIG. 3, and FIG. 5 is a diagram of FIG. 4.

This is a cross-sectional view taken along the line I-I '.

Here, the illustrated transistor is the first transistor T1 or the second transistor T2, and preferably, the first transistor T1 and the second transistor T2 have a layout shown. That is, in the stage SRC according to the first embodiment, at least one of the first transistor T1 and the second transistor T2 has a layout shown. The first transistor T1 and the second transistor T2 have only a difference in that the source electrode is connected to the output terminal OUT and the carry terminal CR, respectively, and thus only the second transistor T2 will be described.

3 and 4, the second transistor includes a second gate electrode 310, a second semiconductor layer 320, a second source electrode 330, and a second drain electrode 340. The second gate electrode 310 is formed on a substrate (eg, an array substrate), and the second semiconductor layer 320 is formed on the second gate electrode 310 in an area corresponding to the second gate electrode 310. . That is, the second semiconductor layer 320 is formed in a region that does not leave the region corresponding to the second gate electrode 310. The second source electrode 330 and the second drain electrode 340 are spaced apart from each other by a predetermined distance on the second gate electrode 310 to have a finger shape.

In detail, the second gate electrode 310 is formed on the substrate to define a predetermined region, and is formed to extend from the first node N1.

The second semiconductor layer 320 is formed of an active layer 322 and an ohmic contact layer 324 sequentially formed on the second gate electrode 310, and is disposed in a region not deviating from an area corresponding to the second gate electrode 310. Is formed. That is, the second semiconductor layer 320 is formed in a region corresponding to the second gate electrode 310 and covered by the second gate electrode 310. Therefore, the light irradiated from the rear surface of the display panel 100 is blocked by the second gate electrode 310 so that no light is irradiated to the second semiconductor layer 320.

The second drain electrode 340 is formed from the second body drain electrode 346, at least one second hand drain electrode 342 branching from the second body drain electrode 346, and from each second hand drain electrode 342. One or more second finger drain electrodes 344 branching off. The second drain electrode 340 is connected to the first clock terminal CK1. Here, the second body drain electrode 346 and the second hand drain electrode 342 are formed in a shape (for example, U-shape) surrounding the second gate electrode 310, and the second finger drain electrode 344 is formed in the second shape. It branches to the gate electrode 310 and overlaps the second gate electrode 310 and the second semiconductor layer 320.

The second source electrode 330 comprises at least one second hand source electrode 332 and at least one second finger source electrode 334 branching from each second hand source electrode 332, in some cases It further comprises two body source electrodes (not shown). The second source electrode 330 is connected to the carry terminal CR (output terminal in the case of the first transistor). The second source electrode 330 is formed in a region corresponding to the second gate electrode 310 to overlap the second gate electrode 310 and the second semiconductor layer 320, and the second hand source electrode 332 And the second finger source electrode 344 is formed in parallel with the second hand drain electrode 342 and the second finger drain electrode 344, respectively. That is, the second source electrode 330 is formed to be surrounded by the second drain electrode 340 spaced apart from the second drain electrode 340 by a predetermined interval.

The number of the second hand drain electrode 342, the second finger drain electrode 344, the second hand source electrode 332, and the second finger source electrode 334 can be freely changed according to the characteristics and the purpose of the transistor. As a result, the shape of the transistor may be changed somewhat.

The gate driving circuit 200 according to the first exemplary embodiment of the present invention is formed in the wiring of the display area DA and in the process of forming the pixel part transistor.

A method of forming the second transistor T2 according to the first embodiment will be briefly described. First, a gate metal layer is formed on a substrate (eg, an array substrate), and then the second gate electrode 310 is formed by a photolithography process using a mask. To form. Here, the gate metal layer is formed of a single layer or multiple metal layers using a conductive metal such as chromium, aluminum, molybdenum, copper, or silver. Examples of the multi-metal layer include a three-layer structure of molybdenum / aluminum / molybdenum (Mo / Al / Mo).

An insulating material such as silicon oxide or silicon nitride is deposited on the entire surface of the substrate on which the second gate electrode 310 is formed to form the gate insulating layer 312.

Next, an intrinsic semiconductor material layer and a semiconductor material layer including impurities are sequentially formed on the entire surface of the substrate on which the gate insulating layer 312 is formed, and then the active layer 322 and the ohmic contact layer 324 are formed by a photolithography process using a mask. Form. Here, the active layer 322 and the ohmic contact layer 324 are defined as the second semiconductor layer 320, and the second semiconductor layer 320 is formed in a region corresponding to the second gate electrode 310. That is, the second semiconductor layer 320 is formed in a region that does not leave the region corresponding to the second gate electrode 310.

Next, after the source / drain metal layer is formed on the entire surface of the substrate on which the second semiconductor layer 320 is formed, the second source electrode 330 and the second drain electrode 340 spaced apart from each other by a photolithography process using a mask. In the etching process, the ohmic contact layer between the second source electrode 330 and the second drain electrode 340 is also etched to form a channel region. Here, the source / drain metal layer is formed of a single layer or multiple metal layers using a conductive metal, like the second gate electrode 310. A protective layer 350 is formed by depositing an insulating material such as silicon oxide and silicon nitride on the entire surface of the substrate on which the second source electrode 330 and the second drain electrode 340 are formed.

Subsequently, in the display area DA, contact holes are formed in the protective layer 350 using a photolithography process using a mask, a transparent conductive metal layer is formed on the entire surface of the substrate on which the contact holes are formed, and then photolithography processes using a mask. Patterning is performed to form pixel electrodes in each pixel portion.

As can be seen through the above-described forming method, it is mentioned that the first embodiment is applicable to any method capable of forming the semiconductor layer 320 independently.

FIG. 6 is a diagram for describing a gate driving circuit according to a second embodiment of the present invention. FIG. 6 is a diagram illustrating a second transistor layout of a stage illustrated in FIG. 3, and FIG. 7 is a II-II illustrated in FIG. 6. 8 is a cross-sectional view taken along the line Ⅲ-Ⅲ of FIG. 6.

3 and 6 to 8, the second transistor T2 (eg, a carry transistor) of the gate driving circuit 200 according to the second embodiment includes the gate electrode 410, the semiconductor layer 420, and the source electrode. 430, a drain electrode 440, and a connection wire 460.

The gate electrode 410 is formed on a substrate (eg, an array substrate), and the semiconductor layer 420 is formed on the gate electrode 410 in a region corresponding to the gate electrode 410. That is, the semiconductor layer 420 is formed in a region that does not leave the region corresponding to the gate electrode 410. The source electrode 430 and the drain electrode 440 are formed in a finger shape on the semiconductor layer 420 in a region not spaced apart from each other by a predetermined interval. The connection line 460 is formed on the drain electrode 440 to connect the drain electrode 440 and the first clock terminal CK1.

In detail, the gate electrode 410 is formed on the substrate to define a predetermined region, and is formed to extend from the first node N1.

The semiconductor layer 420 is formed of an active layer 422 and an ohmic contact layer 424 sequentially stacked on the gate electrode 410, and is formed in a region corresponding to the gate electrode 410. That is, the semiconductor layer 420 is formed in a region that does not leave the region corresponding to the gate electrode 410 and is covered by the gate electrode 410. Therefore, the light irradiated from the rear surface of the display panel 100 is blocked by the gate electrode 410 so that the semiconductor layer 420 is not irradiated with light.

The drain electrode 440 may include a drain contact portion 454 in which a drain contact hole 452 is formed to contact the connection line 460, one or more hand drain electrodes 442 branched from the drain contact portion 454, and One or more finger drain electrodes 444 branched from the hand drain electrode 442 in a direction perpendicular to each other, and further include a body drain electrode (not shown) in some cases. The drain electrode 440 is formed on the semiconductor layer 420 in the region of the gate electrode 410 and overlaps the gate electrode 410 and the semiconductor layer 420. That is, the drain electrode 440 is formed in an island form in the gate electrode 410 region.

Source electrode 430 includes body source electrode 436, one or more hand source electrodes 432 branching from body source electrode 436, and one or more finger source electrodes 434 branching from hand source electrode 432. Include. The body source electrode 436 and the hand source electrode 432 are formed in a shape (eg, U-shaped) surrounding the drain electrode 440, and the finger source electrode 434 is formed in parallel with the finger drain electrode 444. . The source electrode 430 is formed in the gate electrode 410 region and overlaps the gate electrode 410 and the semiconductor layer 420. Here, since the source electrode 430, the drain electrode 440, and the semiconductor layer 420 are formed by a single mask process, regions of the source electrode 430 and the drain electrode 440 correspond to regions of the semiconductor layer 420.

The connection line 460 is formed on the drain electrode 440, and electrically connects the drain electrode 440 and the first clock terminal CK1 through the drain contact hole 452 and the clock contact hole 472. The clock contact hole 472 extends from the first clock terminal CK1 and is formed in the clock contact portion 474 formed at one end of the application line 470 to which the signal of the first clock terminal CK1 is provided.

The number of the hand drain electrode 442, the finger drain electrode 444, the hand source electrode 432, and the finger source electrode 434 can be freely changed according to the characteristics and the purpose of the transistor. you can change it.

The gate driving circuit according to the second exemplary embodiment of the present invention is formed at the same time in the wiring of the display area DA and the pixel portion transistor forming process.

A method of forming the second transistor T2 according to the second embodiment will be briefly described based on differences from the first embodiment.

An intrinsic semiconductor material layer, an impurity-containing semiconductor material layer, and a source / drain metal layer are sequentially formed on the entire surface of the substrate on which the gate insulating film 412 is formed, and then the semiconductor material layer stacked by a photolithography process using a mask and impurities are included. The semiconductor material layer and the source / drain metal layer are etched at once to form the active layer 422, the ohmic contact layer 424, the source electrode 430, and the drain electrode 440.

Here, the active layer 422 and the ohmic contact layer 424 are defined as the semiconductor layer 420, and the semiconductor layer 420, the source electrode 430, and the drain electrode 440 are located in an area corresponding to the gate electrode 410. Form. That is, the semiconductor layer 420, the source electrode 430, and the drain electrode 440 are formed in a region that does not leave the region corresponding to the gate electrode 410. Therefore, the semiconductor layer 420, the source electrode 430, and the drain electrode 440 are covered by the gate electrode 410.

In addition, an application wiring 470 extending from the first clock terminal CK1 is formed, and one end of the application wiring 470 is defined as a clock contact portion 474 in which a clock contact hole 472 is formed in a subsequent process. . The application wiring 470 may be formed at the time of forming the gate electrode 410 in some cases.

Next, a protective layer 450 is formed by depositing an insulating material on the entire surface of the substrate, and a portion of the drain electrode 440 is exposed to the drain contact portion 454 by etching the deposited protective layer 450 using a mask. A clock contact hole 472 is formed in the drain contact hole 452 and the clock contact part 474 to expose a part of the application wiring 470.

Next, after the transparent conductive material layer is formed on the substrate on which the drain contact hole 452 and the clock contact hole 472 are formed, the connection wiring 460 is formed by a photolithography process using a mask and applied with the drain electrode 440. The wiring 470 is electrically connected. That is, the connection wire 460 is formed to electrically connect the drain electrode 440 and the first clock terminal CK1. The transparent conductive material is a material layer for forming a pixel electrode formed in the pixel portion of the display area DA, and includes indium tin oxide or indium zinc oxide.

As can be seen through the formation method described above, in the case of the second embodiment, the semiconductor layer 420, the source electrode 430, and the drain electrode 440 may be applied to a single etching process.

As described above, according to the present invention, the semiconductor layer of the transistor included in the gate driving circuit is formed in a region not deviating from the region corresponding to the gate electrode, so that the semiconductor layer is covered by the gate electrode, so that the back of the display panel Light irradiated from is blocked by the gate electrode so that no light is irradiated to the semiconductor layer. Therefore, the occurrence of the light leakage current is prevented to improve the driving failure.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (9)

A pull-up unit including a first transistor and outputting a gate signal based on a signal of a clock terminal to an output terminal in response to a signal of an input terminal; And A stage including a pull-down unit configured to output a ground voltage to the output terminal in response to a next gate signal, the shift register being dependently connected to each other, The first transistor A first gate electrode formed on the substrate; A first semiconductor layer formed on the first gate electrode in a region corresponding to the first gate electrode; A first source electrode formed on the first semiconductor layer; And And a first drain electrode formed on the first semiconductor layer and spaced apart from the first source electrode by a predetermined distance. The method of claim 1, wherein the first drain electrode A first body drain electrode; A first hand drain electrode branched from the first body drain electrode and surrounding the first gate electrode together with the first body drain electrode; And a first finger drain electrode which is branched from the first hand drain electrode and overlaps the first gate electrode. The method of claim 2, wherein the first source electrode is A first hand source electrode parallel to the first hand drain electrode and overlapping the first gate electrode; And And a first finger source electrode which is branched from the first hand source electrode and overlaps the first gate electrode. The method of claim 1, wherein the stage And a carry part for outputting a carry signal based on a signal of the clock terminal to an input terminal of a next stage in response to a signal of the input terminal. The second transistor A second gate electrode formed on the substrate; A second semiconductor layer formed on the second gate electrode in a region corresponding to the second gate electrode; A second source electrode formed on the second semiconductor layer; And And a second drain electrode formed on the second semiconductor layer and spaced apart from the second source electrode by a predetermined distance. The method of claim 4, wherein the second drain electrode A second body drain electrode; A second hand drain electrode branched from the second body drain electrode and surrounding the second gate electrode together with the second body drain electrode; And a second finger drain electrode which is branched from the second hand drain electrode and overlaps the second gate electrode. The method of claim 5, wherein the second source electrode A second hand source electrode parallel to the second hand drain electrode and overlapping the second gate electrode; And And a second finger source electrode which is branched from the second hand source electrode and overlaps the second gate electrode. A pull-up unit configured to output a gate signal based on a signal of a clock terminal to an output terminal in response to a signal of an input terminal; A carry section including a transistor and outputting a carry signal based on a signal of the clock terminal to an input terminal of a next stage in response to a signal of the input terminal; And A stage including a pull-down unit configured to output a ground voltage to the output terminal in response to a next gate signal, the shift register being dependently connected to each other, The transistor is A gate electrode formed on the substrate; A semiconductor layer formed on the gate electrode in a region corresponding to the gate electrode; A drain electrode formed on the semiconductor layer in a region corresponding to the gate electrode; A source electrode formed on the semiconductor layer spaced apart from the drain electrode by a predetermined distance; And And a connection line formed on the drain electrode, the connection line electrically connecting the drain electrode and the application line extending from the clock terminal. The method of claim 7, wherein the drain electrode A drain contact portion contacting the connection line through a drain contact hole; A hand drain electrode branched from the drain contact portion; And And a finger drain electrode branched from the hand drain electrode. The method of claim 8, wherein the source electrode is overlapped with the gate electrode, Body source electrodes; A hand source electrode branched from the body source electrode and surrounding the drain electrode together with the body source electrode; And And a finger source electrode branching from the hand source electrode.

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