KR101783976B1 - Display device - Google Patents

Abstract

The present invention relates to a display device, and more particularly to a display device including a driving part integrated on a display panel. A display device according to an embodiment of the present invention includes a display panel on which a plurality of pixels and signal lines are formed, and a driver including a first element and a second element formed on the display panel and electrically connected to each other , The density of the pattern of the first element and the density of the pattern of the second element are different from each other, the region where the first element is formed includes at least two first element regions, Wherein the at least two first device regions and the at least one second device region are alternately arranged.

Description

Display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a display device including a driving part integrated on a display panel.

Among the display devices, a liquid crystal display device is one of the most widely used flat panel display devices, and includes two display panels in which field generating electrodes such as pixel electrodes and common electrodes are formed, and a liquid crystal layer interposed therebetween do. The liquid crystal display displays an image by applying a voltage to the electric field generating electrode to generate an electric field in the liquid crystal layer, thereby determining the direction of the liquid crystal molecules in the liquid crystal layer and controlling the polarization of the incident light. In addition to liquid crystal display devices, display devices include organic light emitting display devices, plasma display devices, and electrophoretic display devices.

The display device generally includes a display panel provided with a pixel including a switching element and a display signal line, a gate driver for turning on / off a switching element of a pixel by transmitting a gate signal to a gate line of the display signal line, A data driver, and a signal controller for controlling them.

The gate driver and the data driver may be mounted on a display device in the form of an integrated circuit chip or may be mounted on a flexible printed circuit film and attached to a display device in the form of a tape carrier package (TCP) (printed circuit board). In particular, the gate driver may be formed in the same process as the display signal lines, the switching elements, and the like, and integrated on the display panel.

When the driving portion is formed by being integrated on the display panel, the element of the driving portion can be formed by the patterning method using the exposure and development method. In this case, if there is a difference in the density of the pattern of neighboring elements among the various elements to be patterned of the driving unit, that is, the area ratio of the portion to be developed in each of the neighboring elements, the element having a small density of patterns may be patterned . ≪ / RTI > For example, when a device having a relatively simple pattern such as a capacitor is placed next to a device having a relatively complicated pattern such as a transistor, there is a difference in the concentration of the developer used when developing the photoresist film after exposure, There is a problem that the photosensitive film applied on the element having a complicated pattern close to the boundary portion of the photosensitive film is over-developed. Then, there arises a problem in element patterning of the driving portion, and the driving portion may be defective.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a display device in which when a driving part of a display device is integrated on a display panel, the density of patterns of adjacent elements among the various elements of the driving part, .

A display device according to an embodiment of the present invention includes a display panel on which a plurality of pixels and signal lines are formed, and a driver including a first element and a second element formed on the display panel and electrically connected to each other , The density of the pattern of the first element and the density of the pattern of the second element are different from each other, the region where the first element is formed includes at least two first element regions, Wherein the at least two first device regions and the at least one second device region are alternately arranged.

The first element may comprise a transistor, and the second element may comprise a capacitor.

The driving unit may include a gate driver including an output unit for outputting a gate signal.

The two terminals of the capacitor may be connected to the gate and source of the transistor, respectively.

The source electrodes of the plurality of unit transistors are connected to each other, and the drain electrodes of the plurality of unit transistors are connected to each other, and the gate electrodes of the plurality of unit transistors are connected to each other, And one first element region may include at least one unit transistor arranged in a line among the plurality of unit transistors.

Further comprising a resistive contact member layer and a semiconductor layer located under the source electrode and the drain electrode of the plurality of unit transistors, wherein the resistive contact member layer and the semiconductor layer are electrically connected to the source electrode and the drain And may have the same planar shape as the electrode.

The first element may comprise a capacitor, and the second element may comprise a transistor.

The source electrodes of the plurality of unit transistors are connected to each other, and the drain electrodes of the plurality of unit transistors are connected to each other, and the gate electrodes of the plurality of unit transistors are connected to each other, And one second element region may include at least one unit transistor arranged in a line among the plurality of unit transistors.

The signal line may include a gate line for transmitting a gate signal to the pixel, and the driving unit may include a gate driver including an output unit for supplying a gate signal to the gate line.

A display device according to another embodiment of the present invention includes a display panel having a plurality of pixels and signal lines formed thereon, and a driver formed on the display panel and including first and second elements electrically connected to each other , The average density of the pattern of the first element is higher than the average density of the pattern of the second element, the first element region in which the first element is formed and the second element region in which the second element are formed are adjacent to each other, The second element includes regions where the density of the pattern differs depending on the position.

The density of the pattern of the second element can be increased as it approaches the boundary between the first element region and the second element region.

The first element may comprise a transistor, and the second element may comprise a capacitor.

The driving unit may include a gate driver including an output unit for outputting a gate signal.

The second element includes a first layer formed on an insulating substrate and a second layer formed on the first layer, and the pattern of the second element includes a plurality of openings formed in the second layer And the density of the pattern of the second element may be the distribution density of the opening.

The two terminals of the capacitor may be connected to the gate and source of the transistor, respectively.

The source electrodes of the plurality of unit transistors are connected to each other, and the drain electrodes of the plurality of unit transistors are connected to each other, and the gate electrodes of the plurality of unit transistors are connected to each other, .

Further comprising a resistive contact member layer and a semiconductor layer located under the source electrode and the drain electrode of the plurality of unit transistors, wherein the resistive contact member layer and the semiconductor layer are electrically connected to the source electrode and the drain And may have the same planar shape as the electrode.

The signal line may include a gate line for transmitting a gate signal to the pixel, and the driving unit may include a gate driver for supplying a gate signal to the gate line.

According to another aspect of the present invention, there is provided a display device including a display panel including a plurality of pixels and a signal line, and a driver formed on the display panel, the driver including a transistor, And an overlapping source and drain, wherein the area of the source is at least twice the area of the drain.

The source electrodes of the plurality of unit transistors are connected to each other, and the drain electrodes of the plurality of unit transistors are connected to each other, and the gate electrodes of the plurality of unit transistors are connected to each other, And the width of the source electrode of the unit transistor may be wider than the width of the drain electrode.

Further comprising a resistive contact member layer and a semiconductor layer located under the source electrode and the drain electrode of the plurality of unit transistors, wherein the resistive contact member layer and the semiconductor layer are electrically connected to the source electrode and the drain And may have the same planar shape as the electrode.

The signal line may include a gate line for transmitting a gate signal to the pixel, and the driving unit may include a gate driver for supplying a gate signal to the gate line.

The gate driver may include an output unit that outputs the gate signal, and the transistor may be included in the output unit.

In the case where the density of the pattern is different when the two elements of the driver of the display device are formed in the respective regions, regions of the two elements may be arranged alternately as in the embodiment of the present invention, It is possible to reduce the deviation of the device of the driving part due to the density difference of the pattern of the two devices and the characteristic deviation according to the position by forming the two patterns in one area simultaneously.

1 is a block diagram of a display device according to an embodiment of the present invention,
2 is a block diagram of a gate driver according to an embodiment of the present invention,
3 is an example of a circuit diagram of one stage of a gate driver according to an embodiment of the present invention,
4 is an enlarged view of a portion Aex in the gate driver of FIG. 3,
5 is a layout diagram of a portion of a gate driver according to an embodiment of the present invention,
6 is a cross-sectional view of the gate driver shown in FIG. 5 taken along line VI-VI,
Figs. 7 to 11 are cross-sectional views at an intermediate stage of manufacturing a part of the gate driver shown in Figs. 5 and 6 according to an embodiment of the present invention,
12 is a layout diagram of a part of a gate driver according to another embodiment of the present invention,
13 is a schematic view of a part of a gate driver according to an embodiment of the present invention,
14 is a layout diagram of a part of a gate driver according to another embodiment of the present invention,
15 is a schematic view of a part of the gate driver according to the embodiment shown in FIG. 14,
FIGS. 16, 17 and 18 are partial arrangement views of a gate driver according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. Whenever a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

First, a display device according to an embodiment of the present invention will be described with reference to FIG.

1 is a block diagram of a display device according to an embodiment of the present invention.

1, a display device according to an exemplary embodiment of the present invention includes a display panel 300, a gate driver 400 and a data driver 500 connected to the display panel 300, and a signal controller 600 for controlling the same. .

The display panel 300 includes a plurality of signal lines G1-Gn and D1-Dm and a plurality of pixels PX connected to the signal lines G1-Gn and D1-Dm in the form of an approximate matrix.

The signal lines G1-Gn and D1-Dm include a plurality of gate lines G1-Gn for transferring gate signals (also referred to as "scan signals") and data lines D1-Dm for transferring data signals.

Each pixel PX includes a switching element (not shown) connected to the signal lines G1-Gn and D1-Dm.

The gate driver 400 is connected to the gate lines G1 to Gn to apply a gate signal composed of a combination of the gate-on voltage Von and the gate-off voltage Voff to the gate lines G1 to Gn. The gate driver 400 includes a plurality of stages substantially connected to the gate lines G1 to Gn as shift registers and is formed in the same process as the switching elements of the pixels PX, Lt; / RTI >

The data driver 500 is connected to the data lines D1-Dm of the thin film transistor display panel 300 and applies a data signal to the data lines D1-Dm.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

The data driver and the signal controller 500 or 600 may be directly mounted on the thin film transistor display panel 300 in the form of at least one integrated circuit chip or mounted on a flexible printed circuit film And may be attached to the thin film transistor display panel 300 in the form of a TCP (tape carrier package) or mounted on a separate printed circuit board (not shown). Alternatively, the gate driver 400 may be integrated with the thin film transistor panel 300 together with the signal lines G1-Gn, D1-Dm and the switching elements.

The operation of the display device will be described below.

The signal controller 600 receives an input image signal Din and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 appropriately processes the input video signal Din based on the input video signal Din and the input control signal in accordance with the operation conditions of the thin film transistor display panel 300 and supplies the gate control signal CONT1 and the data control signal CONT1 The gate driver 400 outputs the gate control signal CONT1 to the data driver 500 and the video signal DAT processed with the data control signal CONT2.

The gate control signal CONT1 includes at least one clock signal for controlling the output period of the scan start signal STV indicating the start of scanning and the gate-on voltage Von. The gate control signal CONT1 may further include an output enable signal OE that defines the duration of the gate on voltage Von.

The data control signal CONT2 includes a horizontal synchronization start signal STH for notifying the start of transmission of image data to a pixel PX of one row and a load signal LOAD for applying a data signal to the data lines D1 to Dm, And a data clock signal (HCLK). The data control signal CONT2 is also an inverted signal which inverts the voltage polarity of the data signal with respect to the common voltage Vcom (hereinafter referred to as "the polarity of the data signal by reducing the voltage polarity of the data signal with respect to the common voltage" RVS).

The data driver 500 receives the digital video signal DAT for one row of the pixels PX in accordance with the data control signal CONT2 from the signal controller 600 and outputs the digital video signal DAT corresponding to each digital video signal DAT And converts the digital video signal DAT into an analog data signal and applies it to the corresponding data line D1-Dm.

The gate driver 400 applies a gate-on voltage Von to the gate lines G1-Gn in accordance with the gate control signal CONT1 from the signal controller 600 and applies the gate-on voltage Von to the gate lines G1- . Then, the data signal applied to the data lines D1-Dm is applied to the corresponding pixel PX through the turned-on switching element.

This process is repeated in units of one horizontal period (also referred to as "1H ", which is the same as one cycle of the horizontal synchronizing signal Hsync and the data enable signal DE), so that all the gate lines G1 to Gn On voltage Von is sequentially applied to all the pixels PX to display an image of one frame by applying a data signal to all the pixels PX.

At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled such that the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame ( "Frame inversion"). At this time, the polarity of the data signal flowing through one data line changes (for example, row inversion and dot inversion) depending on the characteristics of the inversion signal RVS in one frame, or the polarity of the data signal applied to one pixel row is different (For example, thermal inversion, dot inversion).

Hereinafter, the driving unit according to one embodiment of the present invention will be described in detail with reference to FIG. 2 to FIG. In this embodiment, the gate driver 400 will be described by way of example, but not limited thereto.

FIG. 2 is a block diagram of a gate driver according to an embodiment of the present invention. FIG. 3 is an example of a circuit diagram of one stage of a gate driver according to an embodiment of the present invention, An enlarged view of one part (Aex).

2 and 3, the gate driver 400 according to an embodiment of the present invention includes a common voltage Vss, first and second clock signals CLK and CLKB, a scan start signal STV, The signal RESET is input, and the reset signal RESET may be omitted. The first and second clock signals CLK and CLKB may have a phase difference of 180 ° with each other. The high level is the gate-on voltage Von and the low level is the gate-off voltage Von so that the switching element can be turned on / (Voff).

The gate driver 400 includes a plurality of stages ST1, ST2, ..., STn, and each stage ST1, ST2, ..., STn includes a set terminal ST, a common voltage terminal GT, Terminals CK and CKB, a reset terminal R, a frame reset terminal FR and a gate output terminal OUT1 and a carry output terminal OUT2. However, as shown in Fig. 2, the last stage STn may not include a frame reset terminal.

The first and second clock signals CLK and CLKB are input to the clock terminals CK and CKB of the stages ST1 to STn and the common voltage Vss is input to the common voltage terminal GT. do. The gate output terminal OUT1 of each of the stages ST1 to STn outputs the gate outputs Gout1, Gout2, ..., and Goutn and outputs the stages ST1, ST2, ..., and ST (except for the last stage STn) the carry output terminal OUT2 of the carry-out circuit Cout1, Cout2, ..., Cout (n-1) outputs the carry outputs Cout1, Cout2, ..., Cout (n-1).

On the other hand, the scan start signal STV is supplied to the set terminal ST of the first stage ST1 and the set terminals ST of the remaining stages ST2, ST3, ..., STn are connected to the front stage ST1, ST2, (n-1)), that is, carry output Cout1, Cout2, ..., Cout (n-1). The gate outputs of the rear stage stages ST2, ST3, and STn, that is, the rear stage gate outputs Gout2, STn, and STn are connected to the reset terminals R of the stages ST1, ST2, Gout3, .., Goutn are input.

3, each stage of the gate driver 400 according to an embodiment of the present invention, for example, the first stage ST1 includes an input unit 420, a pull-up driver 430, a pull-down driver 440, And an output unit 460. These include at least one thin film transistor T1-T14, and the pull-up driver 430 and the output 460 further include capacitors C1-C3. The thin film transistors T1 to T14 may be NMOS transistors or PMOS transistors. Also, the capacitors C1-C3 may actually be the parasitic capacitance between the gate and the drain / source formed in the process.

The input unit 420 includes three transistors T11, T10, and T5 connected in series to the set terminal ST and the common voltage terminal GT. The gates of the transistors T11 and T5 are connected to the clock terminal CKB and the gate of the transistor T10 is connected to the clock terminal CK. The contact between the transistor T11 and the transistor T10 is connected to the contact J1 and the contact between the transistor T10 and the transistor T5 is connected to the contact J2.

The pull-up driving part 430 includes a transistor T4 connected between the set terminal ST and the contact J1, a transistor T12 connected between the clock terminal CK and the contact J3, And a transistor T7 connected between the contact CK and the contact J4. The gate and the drain of the transistor T4 are connected in common to the set terminal ST and the source thereof is connected to the contact J1 and the gate and the drain of the transistor T12 are connected in common to the clock terminal CK And the source is connected to the contact J3. The gate of the transistor T7 is connected to the contact J3 and is connected to the clock terminal CK through the capacitor C3 while the drain is connected to the clock terminal CK and the source is connected to the contact J4 , And a capacitor C2 is connected between the contact J3 and the contact J4.

The pull-down driver 440 includes a plurality of transistors T6, T9, T13, T8, T3, and T2 that receive the common voltage Vss through a source and output the same through the drain to the contacts J1, J2, J3, . The gate of the transistor T6 is connected to the frame reset terminal FR and the drain thereof is connected to the contact J1. The gate of the transistor T9 is connected to the reset terminal R and the drain thereof is connected to the contact J1 , The gates of the transistors T13 and T8 are commonly connected to the contact J2 and the drains are connected to the contacts J3 and J4, respectively. The gate of the transistor T3 is connected to the contact J4 and the gate of the transistor T2 is connected to the reset terminal R while the drains of the two transistors T3 and T2 are connected to the contact J2.

The output section 460 includes a pair of transistors T1 and T14 whose drain and source are connected between the clock terminal CK and the output terminals OUT1 and OUT2 and whose gate is connected to the contact J1, And a capacitor C1 connected between the gate and the source of the transistor T1, i.e., between the contact J1 and the contact J2. The source of the transistor T1 is also connected to the contact J2.

4, two terminals of the capacitor C1 are connected to the drain of the transistor T1, and the other terminal of the capacitor C1 is connected to the gate of the transistor T1. The source G and the gate G of the transistor Q1 are connected to each other. When such elements are formed by patterning on the display panel 300, the transistor T1 has a relatively high density pattern, that is, a relatively high proportion of the area of the portion removed by patterning, as compared with the capacitor C1 , Which are adjacent to each other. Hereinafter, the density of the pattern refers to the area ratio of the portion to be patterned and removed or the area ratio of the developed portion to the entire area of the device.

(For example, the transistor T1) and the low density pattern (for example, the capacitor C1) among the elements adjacent to each other in the driving unit integrated in the display panel 300, Will be described with reference to Figs. 1 to 4 described above with reference to Figs. 5, 6, and 13. Fig.

In this embodiment, the transistor T1 and the capacitor C1 included in the output portion 460 of the gate driver 400 are described as an example, but the present invention is not limited thereto.

5 is a cross-sectional view taken along line VI-VI of FIG. 5, and FIG. 13 is a cross-sectional view of an embodiment of the present invention FIG. 2 is a schematic view of a part of a gate driver according to FIG.

First, referring to FIGS. 5 and 6, a gate electrode 124a is formed on an insulating substrate 110 made of transparent glass or plastic. The gate electrode 124a transmits a gate signal and may have a polygonal shape.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate electrode 124a.

A semiconductor layer (not shown) made of hydrogenated amorphous silicon (amorphous silicon is abbreviated as a-Si) or polycrystalline silicon (polysilicon) is formed on the gate insulating layer 140. The semiconductor layer includes a plurality of vertical portions (not shown) extending vertically and a plurality of projections 154a projecting leftward or rightward from the vertical portions.

A pair of ohmic contact layers (not shown) are formed on the semiconductor layer. One resistive contact member layer includes a plurality of vertical portions (not shown) having substantially the same shape as the vertical portion of the semiconductor layer and a plurality of resistive contact members 163a protruding leftward or rightward from the vertical portions . The remaining resistive contact member layer includes a plurality of resistive contact members 165a that respectively face the resistive contact member 163a. The plurality of resistive contact members 163a are connected to each other or connected to each other through a vertical portion, and the plurality of resistive contact members 165a are also connected to each other.

The resistive contact member layer may be made of a material such as n + hydrogenated amorphous silicon, or a silicide, which is heavily doped with an n-type impurity such as phosphorus.

A data conductor layer is formed on the resistive contact member layer. The data conductor layer includes a plurality of source electrodes 173a, a plurality of source expansions 172a and a plurality of drain electrodes 175a.

The source extension 172a extends vertically and is located above the vertical portion of the semiconductor layer and the resistive contact member layer, respectively. The source extension 172a has substantially the same shape as the vertical portion of the semiconductor layer and the ohmic contact member layer.

The source electrode 173a is connected to the source extension 172a and extends to the left or right of the source extension 172a. The source electrodes 173a immediately adjacent to each other may be directly connected to each other. The source electrode 173a has substantially the same shape as the resistive contact member 163a.

The drain electrode 175a is separated from the source electrode 173a and the source extension 172a. Each drain electrode 175a faces each source electrode 173a on the gate electrode 124a and all the drain electrodes 175a are connected to each other through a connection 177a. The drain electrode 175a and the connection portion 177a have substantially the same shape as the plurality of resistive contact members 165a.

The resistive contact members 163a and 165a are only present between the protruding portion 154a of the semiconductor layer below it and the data conductor layer thereon and lower the contact resistance therebetween.

The gate electrode 124a, the source electrode 173a and the drain electrode 175a together with the protrusion 154a of the semiconductor layer constitute a unit transistor TFTua which is a thin film transistor (TFT) channel is formed in the protrusion 154a of the semiconductor layer between the source electrode 173a and the drain electrode 175a. All of the unit transistors TFTua are connected to each other to form a single transistor T1 which functions together. The plurality of source electrodes 173a constitute the source S of the transistor T1 and the plurality of drain electrodes 175a constitute the gate G of the transistor T1. (D).

A plurality of source extension portions 172a of the data conductor layer overlapping the gate electrode 124a with the gate insulating film 140 therebetween form a single capacitor C1. The capacitor C1 can serve to maintain a voltage difference between the gate G and the source S of the transistor T1 and to improve the noise of the output signal.

The projecting portion 154a of the semiconductor layer has a portion exposed between the source electrode 173a and the drain electrode 175a without being blocked by the data conductor layer and the resistive contact member layer. The semiconductor layer has almost the same planar shape as the data conductor layer and the underlying resistive contact member layer except for the channel portion between the source electrode 173a and the drain electrode 175a. The resistive contact member layer also has substantially the same planar shape and the same outer shape as the data conductor layer.

Referring to FIGS. 5 and 13, a plurality of unit transistors TFTua are arranged in a plurality of transistor columns. A region where each transistor row is located is referred to as a transistor region TA. A capacitor region CA constituting a capacitor C1 is disposed between the transistor regions TA.

The region constituting one transistor T1 is divided into at least two transistor regions TA and the region constituting one capacitor C1 is formed into at least one capacitor region CA to form two regions TA and CA The density of the pattern, that is, the area of the capacitor C1 in which the density of the pattern is relatively low and the area of the transistor T1 where the area ratio of the portion to be patterned and removed with respect to the entire area is relatively high, Can be mixed alternately.

Unlike the embodiment shown in FIG. 13, the region constituting one transistor T1 is formed into at least one transistor region TA and the region constituting one capacitor C1 is divided into at least two capacitor regions CA The regions TA and CA may be arranged alternately. In this case, the transistor region TA is located only between the capacitor regions CA.

The number of transistor regions TA and the number of capacitor regions CA are not limited to the embodiment shown in FIG. 13 and can be variously set according to design conditions.

A manufacturing method of this transistor T1 and the capacitor C1 according to one embodiment of the present invention will be described with reference to Figs. 5 and 6 and Figs. 7 to 11. Fig.

Referring to FIG. 7, a gate electrode 124a is formed on an insulating substrate 110, and a gate insulating film 140 is formed thereon. Next, an intrinsic semiconductor material such as amorphous or crystalline silicon, a semiconductor material doped with impurities, and a conductive material for data are sequentially stacked on the gate insulating layer 140 to form an intrinsic semiconductor layer 150, a semiconductor layer 160 doped with impurities, And a data conductive layer 170 are stacked. Next, the photosensitive film 50 is coated on the data conductive layer 170.

8, the photoresist film 50 is exposed and developed through a photomask (not shown) to form a photoresist pattern including the thick portion 52 and the thin portion 54. Next, as shown in FIG. In this case, the density of the photoresist pattern, that is, the area ratio of the portion to be patterned and removed with respect to the total area, or the concentration of the developer in a region where the developed area ratio is high is smaller than that in the portion where the density of the photoresist pattern is relatively low have.

9, the data conductive layer 170, the impurity-doped semiconductor layer 160, and the intrinsic semiconductor layer 150 are wet-etched and dry-etched using the photoresist pattern as an etch mask, A data conductor 174, a resistive contact layer 164, and a protrusion 154a.

10, the thin portion 54 of the photoresist pattern is removed. At this time, the thick portion 52 is also thinned because it is removed by the thickness of the thin portion 54.

The data conductor 174 and the ohmic contact layer 164 are etched using the remaining photoresist pattern 52 to form the source electrode 173a, the source extension 172a and the drain electrode 175a ), And a resistive contact member layer comprising resistive contact members 163a, 165a. Finally, as shown in FIG. 6, the remaining photoresist pattern 52 is removed.

The area TA of the transistor T1 having a high pattern density, that is, the area ratio of the part to be patterned and removed, and the area CA of the capacitor C1 having a low pattern density are formed as shown in Figs. 5 and 6, It is possible to alleviate the concentration difference of the developer depending on the density difference of the pattern of the photoresist film 50 when the photoresist film 50 is developed. It is possible to prevent a variation in the area and thickness of the thin portion 54 of the photoresist pattern according to the transistor region TA and to prevent the thin portion 54 of the photoresist pattern from over-developing and becoming too thin or missing . This makes it possible to reduce variations in the characteristics of the transistor T1 along with the position of the transistor region TA in which the transistor T1 is formed and also to prevent defects in some regions of the transistor T1.

Next, the arrangement structure of the transistor T1 and the capacitor C1 of the gate driver according to another embodiment of the present invention will be described with reference to FIG. The same reference numerals are given to the same constituent elements as those of the above-described embodiment, and the same explanations are omitted.

12 is a layout diagram of a portion of a gate driver according to another embodiment of the present invention.

The embodiment shown in Fig. 12 has almost the same structure as the embodiment of Figs. 5 and 6 except for the semiconductor layer.

A gate electrode 124b, a gate insulating film 140, a plurality of island-shaped semiconductors 154b, a pair of resistive contact member layers (not shown), a source electrode 173b connected to each other, A data conductor layer (not shown) including a drain electrode 175b and a drain electrode 175b are sequentially formed.

The island-like semiconductor 154b overlapping the source electrode 173b and the drain electrode 175b facing each other is formed, unlike the embodiments of Figs. 5 and 6 described above.

The gate electrode 124b, the source electrode 173b and the drain electrode 175b together with the semiconductor 154b form a unit transistor TFTub. One semiconductor 154b may overlap a part of two source electrodes 173b and two drain electrodes 175b as shown in Fig.

All the unit transistors TFTub are connected to each other to form one transistor T1 which functions as a single unit. A plurality of source extension portions 172b overlapping the gate electrode 124b and the gate insulating film 140 form a single capacitor C1.

In the method of manufacturing the gate driver 400 according to the present embodiment, the island-like semiconductor 154b, the data conductor layer, and the ohmic contact member layer are formed using a separate mask without using one optical mask. In addition, various features and effects of the embodiments shown in Figs. 5 to 11 and 13 can be applied to the embodiment shown in Fig.

Next, the structure of the gate driver according to another embodiment of the present invention will be described with reference to FIGS. 14 and 15. FIG. 14 is a layout diagram of a portion of a gate driver according to another embodiment of the present invention, and FIG. 15 is a cross-sectional view of a gate driver shown in FIG. 14 Fig. 2 is a schematic view of a part of a gate driver according to an embodiment.

The embodiment shown in FIG. 14 is mostly the same as the embodiment shown in FIG. 5, but shows an example in which the transistor area TA and the capacitor area CA are alternately arranged in the column direction.

14 and 15, a unit transistor TFTua constituting a transistor T1 of the gate driver 400 forms a plurality of transistor rows. The transistor region TA, which is an area where each transistor row is located, extends long in the row direction, and a capacitor region CA that forms a capacitor C1 is disposed between adjacent transistor regions TA. The capacitor region CA also extends in the row direction.

13, in this embodiment, at least two transistor regions TA constituting one transistor T1 and at least one capacitor region CA constituting one capacitor C1 are opened Direction. Alternatively, the region of one transistor T1 may be at least one transistor region TA and the region of one capacitor C1 may be divided into at least two capacitor regions CA to alternate between the two regions TA and CA. As shown in FIG.

The number of transistor regions TA and the number of capacitor regions CA are not limited to the embodiments shown in Figs. 14 and 15, and may be variously set according to design conditions.

According to another embodiment of the present invention, the transistor T1 and the capacitor C1 may be formed by mixing the structure shown in Fig. 13 and the structure shown in Fig. That is, a portion in which a plurality of transistor regions TA and a plurality of capacitor regions CA are alternately arranged in the row direction and a portion alternately arranged in the column direction can be formed together.

Next, the structure of the gate driver according to another embodiment of the present invention will be described with reference to FIGS. 16 and 17, respectively.

16 and 17 are respectively a layout diagram of a part of the gate driver according to another embodiment of the present invention. The embodiment shown in Figs. 16 and 17 has almost the same layered structure as the embodiment of Figs. 5 and 6 described above.

A gate electrode 124c and a gate insulating film 140 are sequentially formed on the insulating substrate 110. [

A semiconductor layer (not shown) is formed on the gate insulating layer 140. The semiconductor layer includes one extension (not shown) and a plurality of protrusions 154c protruding from one side of the extension. The protrusions 154c may be arranged in a plurality of rows or columns. The extension of the semiconductor layer may include a plurality of openings (not shown).

A pair of resistive contact member layers (not shown) separated from each other is formed on the semiconductor layer. One resistive contact member layer includes one extension (not shown) having substantially the same shape as the extension of the semiconductor layer and a plurality of resistive contact members (not shown) protruding from one face of the extension. The remaining resistive contact member layer includes a plurality of resistive contact members (not shown) connected to each other. The extension of the resistive contact member layer may include a plurality of openings (not shown).

A data conductor layer is formed on the resistive contact member layer. The data conductor layer includes a plurality of source electrodes 173c, a source extension 172c, and a plurality of drain electrodes 175c.

The source electrode 173c is connected to the source extension 172a and extends from one side of the source extension 172c. The plurality of source electrodes 173c may be arranged in a plurality of rows, and the adjacent source electrodes 173c in one row are connected to each other.

The drain electrode 175c is separated from the source electrode 173c and the source extension 172c. Each drain electrode 175c faces each source electrode 173c on the gate electrode 124c and all the drain electrodes 175c are connected to each other through a connection 177c.

The source extension 172c is located over the extension of the semiconductor layer and the ohmic contact layer and has substantially the same shape as the extension of the semiconductor layer and ohmic contact layer. The outer periphery of the source extension 172c may have a polygonal shape such as a substantially rectangular shape.

The gate electrode 124c, the source electrode 173c and the drain electrode 175c together with the protrusion 154c of the semiconductor layer constitute a unit transistor TFTuc and all the unit transistors TFTuc are connected to each other to perform one function One transistor T1. The source extension portion 172c overlapping the gate electrode 124c with the gate insulating film 140 therebetween forms one capacitor C1. In the embodiment of Fig. 16, the region of the transistor T1 is one and the region of the capacitor C1 is also one, and neighbor to each other.

The semiconductor layer has substantially the same planar shape as the data conductor layer and the underlying resistive contact member layer except for the channel portion between the source electrode 173c and the drain electrode 175c. The resistive contact member layer also has substantially the same planar shape and the same outer shape as the data conductor layer.

Particularly, in the embodiment of the present invention, the source extension portion 172c includes a plurality of openings 70, and the distribution density of the openings 70 may be different in position. That is, the distribution density of the plurality of openings 70 may be higher nearer to the region of the transistor T1, and may become lower as the distance from the transistor T1 increases.

Each opening 70 may have various shapes such as a polygon such as a rectangle, an ellipse, and a circle. The sizes of the openings 70 may vary according to the design conditions. On the other hand, the opening included in the extension of the semiconductor layer and the ohmic contact layer may be formed in the same shape as the opening 70 of the source extension 172c.

The average density depending on the position of the pattern of the region of the capacitor C1 including the opening portion 70 in the present embodiment may be lower than the density of the pattern of the region of the transistor T1.

As described above, when the region of the transistor T1 and the region of the capacitor C1 are adjacent to each other, the density of the pattern, that is, the data challenge of the capacitor C1 constituting the capacitor C1, The density difference of the abrupt pattern at the boundary between the region of the capacitor C1 and the region of the transistor T1 can be reduced by forming the same pattern as the opening portion whose density becomes higher as the transistor T1 approaches the body layer. Therefore, in the method of manufacturing the gate driver according to the embodiment of FIGS. 7 to 11 described above, it is possible to prevent the abrupt change in the concentration of the developer, and to reduce the defect and the characteristic deviation of the transistor T1.

On the other hand, in the embodiment shown in Fig. 17, transistors T2 and T3 other than the transistor T1 are further formed around the region where the capacitor C1 is formed. These transistors T2 and T3 may be transistors T2 and T3 included in the pull-down driving unit 440 in the embodiment of FIG. 3 described above.

In this embodiment, the density of the opening 70 of the source extension 172c is higher toward the region of the transistor T1 and closer to the region of the transistor T2 adjacent thereto. Therefore, it is possible to prevent the pattern density at the boundary portion between the capacitor C1 region and the other transistor T2 adjacent to the upper portion, that is, the abrupt change in the area ratio of the portion to be patterned and removed with respect to the whole area. Various features and effects of the embodiment of Fig. 16 described above can also be applied to this embodiment.

Finally, the structure of the gate driver according to another embodiment of the present invention will be described with reference to FIG.

18 is a layout diagram of a portion of a gate driver according to another embodiment of the present invention. The embodiment of Fig. 18 has almost the same layer structure as the embodiment of Figs. 5 and 6 described above.

A gate electrode 124d and a gate insulating film 140 are sequentially formed on the insulating substrate 110 and a semiconductor 154d overlapping the gate electrode 124d is formed on the gate insulating film 140. [ On the semiconductor 154d, a pair of resistive contact member layers (not shown) separated from each other is formed, and a data conductor layer is formed thereon.

The data conductor layer includes a plurality of source electrodes 173d and a plurality of drain electrodes 175d.

The source electrode 173d has a plurality of rows, and adjacent source electrodes 173d in each row are connected to each other. Further, a plurality of rows of the source electrodes 173d are all electrically connected through a connection portion 172d.

The drain electrode 175d is surrounded by the source electrode 173d and separated from the source electrode 173d. Each drain electrode 175d faces each source electrode 173d on the gate electrode 124d and all the drain electrodes 175d are connected to each other through a connection 177d.

The gate electrode 124d, the source electrode 173d and the drain electrode 175d constitute a unit transistor TFTud together with the semiconductor 154d and all the unit transistors TFTud are connected to each other to form a single Thereby forming a transistor T1. The source electrode 173d, which overlaps the gate electrode 124d and the gate insulating film 140, forms a capacitor C1 together.

That is, in this embodiment, the region of the transistor T1 and the region of the capacitor C1 are not separated from each other but formed in one region. The width W or the area of the source electrode 173d is much larger than the width or area of the source electrodes 173a, 173b, and 173c in the above-described embodiment. For example, the area of all the source electrodes 173d may be at least two times, more specifically at least three times, the area of all the drain electrodes 175d.

As described above, by forming the region of the transistor T1 and the region of the capacitor C1 in one region without being separated from each other, the defect of the gate driver due to the density difference of the patterns of the two elements and the formation It is possible to eliminate the deviation according to the position.

In the embodiments shown in FIGS. 16 to 18, the semiconductor or semiconductor layer has substantially the same planar shape as the data conductor layer and the underlying resistive contact layer except for the channel portion. However, the semiconductor or semiconductor layer is not limited thereto, Or may be formed using a separate photomask from the data conductor layer.

Various features of the embodiments of the present invention can be applied to display devices and various driving parts of various structures.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

50: photosensitive film 52, 54: photosensitive film pattern
70: opening 110: insulating substrate
124a, 124b, 124c, and 124d:
140: gate insulating film 150: intrinsic semiconductor layer
154a, 154b, 154c, 154d: protrusions of the semiconductor and semiconductor layers
160: doped semiconductor layer
163a, 165a: resistive contact member
164: resistive contact layer 170: data conductive layer
172a, 172b, 172c:
172d, 177a, 177b, 177c, 177d:
173a, 173b, 173c, and 173d:
174: Data conductor
175a, 175b, 175c, and 175d: drain electrodes
300: display panel 400: gate driver
500: Data driver 600: Signal controller
CA: capacitor area TA: transistor area
TFTua, TFTub, TFTuc, TFTud: unit transistor

Claims (20)

A display panel in which a plurality of pixels and a plurality of signal lines are formed, and
A driver connected to the plurality of signal lines and including a transistor electrically connected to each other and a capacitor,
Lt; / RTI >
The capacitor being located adjacent to the transistor in a plan view,
Wherein the capacitor includes a first conductive layer and a second conductive layer overlapping each other with an insulating film interposed therebetween,
Wherein the second conductive layer comprises at least one opening adjacent the transistor
Display device. The method of claim 1,
Wherein the at least one opening is provided with a plurality of openings,
Wherein the plurality of openings are spaced apart from each other,
Wherein a portion of the plurality of openings is adjacent to the transistor and arranged around the transistor. delete 3. The method of claim 2,
Wherein the driving unit includes a gate driver including an output unit for outputting a gate signal. 3. The method of claim 2,
And the distribution density of the plurality of openings decreases as the distance from the transistor increases. The method of claim 5,
The second conductive layer being connected to a source electrode of the transistor,
And the first conductive layer is connected to a gate electrode of the transistor. The method of claim 6,
Wherein the transistor includes a plurality of unit transistors,
The gate electrodes of the plurality of unit transistors are connected to each other, the source electrodes of the plurality of unit transistors are connected to each other, and the drain electrodes of the plurality of unit transistors are connected to each other
Display device. 8. The method of claim 7,
Further comprising: a resistive contact member layer and a semiconductor layer located below the source electrode and the drain electrode of the plurality of unit transistors,
Wherein the ohmic contact layer and the semiconductor layer have the same planar shape as the source electrode and the drain electrode of the plurality of unit transistors except the channel portion
Display device. The method of claim 6,
The source electrode of the transistor being located in the same layer as the second conductive layer,
And the gate electrode of the transistor is located in the same layer as the first conductive layer. delete The method of claim 1,
The second conductive layer being connected to a source electrode of the transistor,
And the first conductive layer is connected to a gate electrode of the transistor. 12. The method of claim 11,
Wherein the transistor includes a plurality of unit transistors,
The gate electrodes of the plurality of unit transistors are connected to each other, the source electrodes of the plurality of unit transistors are connected to each other, and the drain electrodes of the plurality of unit transistors are connected to each other
Display device. The method of claim 1,
Wherein the plurality of signal lines include a gate line for transmitting a gate signal to the pixel,
Wherein the driver includes a gate driver for supplying a gate signal to the gate line
Display device. delete delete delete delete delete delete delete

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