KR20050113696A - Organic electro luminescent display panel - Google Patents

Abstract

 The present invention relates to an organic light emitting display panel, wherein a boost control line and a capacitor comprise a semiconductor layer forming one electrode of the capacitor; A gate electrode layer formed on the semiconductor layer and branched from the boost control line; A first contact hole formed over the gate electrode layer and a second contact hole contacting the semiconductor layer; And a metal layer in contact with the semiconductor layer and the gate electrode layer through the first contact hole and the second contact hole, respectively.

Description

Organic electroluminescent display panel {ORGANIC ELECTRO LUMINESCENT DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting display panel, and more particularly, to an organic light emitting display panel having an improved aperture ratio by improving an arrangement structure of unit pixels.

The organic light emitting device electrically emits and emits a fluorescent organic material by a combination of electrons supplied from a cathode and holes supplied from an anode. In this case, in order to improve the supply of electrons and holes, the organic material is generally formed of a multilayer structure including an emitting layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL). .

In addition, the organic EL device can be classified into a passive matrix type and an active matrix type. The active matrix type is a signal type that maintains a voltage by writing a voltage to a capacitor. Therefore, it is divided into a voltage programming method and a current programming method.

1 is an equivalent circuit diagram of an active matrix type organic light emitting device, and a pixel circuit of a conventional organic light emitting device includes a switching thin film transistor ST, a driving thin film transistor DT, and a storage capacitor C _ST . do. In this case, the unit pixels have a matrix array structure defined by the intersecting arrangement of the scan lines S1 to Sn, the data lines D1 to Dn, and the power lines V1 to Vn.

In each unit pixel, the switching thin film transistor ST has a source electrode and a gate electrode connected to the scan lines S1 to Sn and the data lines D1 to Dn, respectively, and the drain electrode has a gate electrode of the driving thin film transistor DT. Is connected. The storage capacitor C _ST is connected in parallel between the drain electrode of the switching thin film transistor ST and the power lines V1 to Vn. The source electrode of the driving thin film transistor DT is connected to the power lines V1 to Vn, and the drain electrode is connected to the organic material EL to form an anode of the organic material EL. The cathode of the organic material EL is supplied with the same common voltage for each pixel.

When the thin film transistor ST is turned on by a selection signal applied to the gate of the switching thin film transistor ST, the data voltage from the data lines D1 to Dn is applied to the switching thin film transistor ST. Is applied to the gate. Then, a current I _OLED flows in the thin film transistor DT in response to the voltage V _GS charged between the gate and the source by the storage capacitor C _ST , and according to the current I _OLED , an organic material ( EL) emits light.

However, in such a driving voltage writing method, there is a problem in that the luminance of the panel is not uniform due to the characteristic variation of each pixel of the driving thin film transistor, for example, the variation of the threshold voltage, the mobility of the channel, and the like.

Accordingly, a number of compensation circuits have been proposed for correcting the characteristic variation of the driving thin film transistor. However, the number of the thin film transistors has been increased, resulting in a problem of lowering the aperture ratio of the unit pixel.

On the other hand, in the organic light emitting device of the current writing method, even if the current source for supplying the current to the pixel circuit is uniform for the entire panel, that is, all the data lines, even if the driving thin film transistors in each pixel have uneven voltage-current characteristics One display characteristic can be obtained.

FIG. 2 is a pixel circuit of a conventional current write method for driving an organic light emitting device, and typically shows one of N × M pixels. The driving thin film transistor DT is connected to the organic material EL to supply current for emitting light, and the amount of current of the thin film transistor DT is controlled by the data current I _DATA applied through the switching thin film transistor ST1. It is configured to be controlled.

When the switching thin film transistors ST1 and ST2 are turned on by the selection signal from the scan line Sn, the thin film transistor DT is in a diode-connected state, and current flows in the storage capacitor C _ST to charge the voltage. In addition, the gate potential of the thin film transistor DT is dropped so that a current flows from the source to the drain, and a voltage corresponding to the luminance setting data current I _DATA is stored in the storage capacitor C _ST . Next, the switching thin film transistors ST1 and ST2 are turned off and the thin film transistor ET connected to the emission control line En is turned on. Then, power is supplied from the power supply line Vm, and a current corresponding to the voltage stored in the storage capacitor C _ST flows into the organic material EL to emit light at the set luminance.

However, since the current I _OLED flowing through the organic material is a microcurrent and the voltage range of the data line Dm is wide, the parasitic capacitance of the data line is charged when driving the pixel circuit with the microcurrent I _DATA . There is a problem that takes a lot of time.

In addition, the number of thin film transistors disposed in a unit pixel increases, causing a problem that the aperture ratio is considerably reduced. This reduction in aperture ratio causes a problem of lowering luminance and requiring high current driving and thus reducing lifetime.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide an organic light emitting display panel of the present invention, in which an aperture ratio is increased by improving an arrangement structure of unit pixels.

In order to achieve the above object, the organic light emitting display panel of the present invention,

Data lines and power lines in one direction; A scan line selectively intersecting the power line and the data line: an emission control line parallel to the scan line; And a boost control line parallel to the emission control line, wherein the unit pixel is defined.

The pixel circuit for driving the unit pixel,

First and second thin film transistors configured to transfer data current from the data line in response to a selection signal from the scan line;

A third thin film transistor supplying a driving current for emitting an organic material and diode-connected while the data current is transmitted from the first and second thin film transistors;

A fourth thin film transistor configured to transfer the driving current from the third thin film transistor to the organic material;

A first capacitor storing a first voltage corresponding to a data current from the first thin film transistor; And,

And a second capacitor electrically connected between the first capacitor and the boost control line and configured to change the first voltage of the first capacitor to a second voltage through coupling with the first capacitor. ,

The boost control line and the second capacitor,

A semiconductor layer forming one electrode of the second capacitor;

A gate electrode layer formed on the semiconductor layer and branched to the boost control line;

A first contact hole formed over the gate electrode layer and a second contact hole contacting the semiconductor layer; And,

And a metal layer contacting the semiconductor layer and the gate electrode layer through the first contact hole and the second contact hole, respectively.

In this case, the first to fourth thin film transistors are formed in an area defined by the data line, the scan line, the power line, and the emission control line.

More preferably, the first thin film transistor is formed in an area where the data line and the scan line intersect, the second thin film transistor is formed in an area where the data line and the emission control line intersect, and the third thin film transistor is The fourth thin film transistor is formed across the light emission control line.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. When a part is connected to another part, this includes not only a directly connected part but also a case where another part is connected in between. In addition, when a part of a layer, a film, an area, a plate, or the like is on another part, this includes not only the part directly above the other part but also another part in the middle.

3 is a view schematically showing a configuration of an organic light emitting device to which the present invention is applied.

Referring to this, the organic field display device includes a display panel 100, a scan driver 200, and a data driver 400. The display panel 100 extends in the column direction with a plurality of scan lines S1 to Sn, light emission control lines E1 to En, and boost control lines B1 to Bn extending in the row direction with reference to the drawings. A plurality of data lines D1 to Dm, a plurality of power lines VDD, and a plurality of pixels 110.

Herein, the pixel 110 is formed in a pixel area formed by two arbitrary adjacent scan lines Sk-1 and Sk and two adjacent data lines Dk-1 and Dk, and each pixel 110 is formed. Is driven by signals transmitted from the scan lines S1 to Sn, the light emission control lines E1 to En, the boost control lines B1 to Bn, and the data lines D1 to Dm.

In addition, the scan driver 200 sequentially transmits a selection signal for selecting a corresponding line to the scan lines S1 to Sn so that a data signal can be applied to the pixels of the corresponding line, and controls emission of the organic material EL. The light emission control signals are sequentially transmitted to the light emission control lines E1 to En.

In addition, the scan driver 200 applies a boost signal to the pixels of the line through the boost control line to determine the gate voltage rising width of the driving transistor by coupling the two capacitors C1 and C2 connected to the boost control line. . Accordingly, the current supplied to the organic material EL can be set to a desired value.

In addition, whenever the selection signals transmitted through the scan lines S1 to Sn are sequentially applied, the data driver 400 outputs data signals corresponding to the pixels of the line to which the selection signals are applied to the data lines D1 to Dm. ) Is applied.

The scan driver 200 and the data driver 400 configured as described above are electrically connected to the substrate on which the display panel 100 is formed. Alternatively, the scan driver 200 and / or the data driver 400 may be directly mounted on the glass substrate of the display panel 100, and the substrates of the display panel 100 may have the same layers as the scan lines, the data lines, and the transistors. It may be replaced by a driving circuit formed. Alternatively, the scan driver 200 and / or the data driver 400 may be bonded to a substrate of the display panel 100 and electrically connected to a tape carrier package (TCP), a flexible printed circuit (FPC), or a tape automatic bonding (TAB). It can also be mounted in the form of a chip or the like.

Next, a detailed operation of the organic light emitting device will be described with reference to FIGS. 4 and 5.

4 is a diagram schematically illustrating a display panel according to an exemplary embodiment of the present invention applied to the organic light emitting device illustrated in FIG. 3, and FIG. 5 is an equivalent circuit diagram corresponding to an nth pixel of FIG. 4.

Referring to this, the pixel circuit of the display panel 100 of the present exemplary embodiment includes the driving transistor M3, the light emitting transistor M4, the switching transistor M1, the diode transistor M2, the organic material EL, and It consists of two capacitors C1 and C2.

More specifically, the switching transistor M1 is connected between the data line D _m and the gate of the driving transistor M3, and is input from the data line D _m in response to a selection signal from the scanning line S _n . The data current I _DATA is transferred to the transistor M1. Diode transistor (M2) is connected between the drain of the transistor (M1) and the data line (D _m), in response to a select signal from the scan line (S _n) then diode connecting the driving transistor (M3).

The driving transistor M3 has a source connected to the power supply voltage Vm and a drain connected to the diode transistor M2. The gate-source voltage of this driving transistor M3 is determined corresponding to the data current I _DATA .

The capacitor C2 is connected between the gate and the source of the driving transistor M1 to maintain the gate-source voltage of the driving transistor M3 for a predetermined time, and the capacitor C1 drives the boost control line B _n . It is connected between the gates of the transistor M3 to regulate the gate voltage of the transistor M1.

By connecting the capacitors in this way, the voltage at the node of the capacitor C2 is increased by the voltage rising width ΔV _B of the boost signal input from the boost control line B _n , so that the gate voltage V _G of the driving transistor M3 is increased. The increase amount ΔV _G is given by Equation 1. Therefore, the transistor (M1, M2, M3) corresponding to a parasitic capacitance component desired to rise (ΔV _G) of the gate voltage (V _G) for directing an voltage rise (ΔV _B) of the boost signal, the driving transistor (M3) of Can be set to a value. That is, the current I _OLED supplied to the organic EL element OLED can be set to a desired value.

Next, the light emitting transistor M4 supplies a current flowing through the driving transistor M3 to the organic material EL in response to a light emission signal from the light emission control line E _n . The organic material EL is connected between the light emitting transistor M4 and the reference voltage and emits light corresponding to the amount of current flowing through the driving transistor M3.

The operation of the pixel circuit thus constructed will be described in detail below.

First, the switching transistor (M2) and a diode transistor (M3) by a selection signal applied through the scan line (S _n) is turned on. As a result, the driving transistor M3 is diode-connected, and the data current I _DATA from the data line D _m flows to the driving transistor M3. At the same time, since the light emitting transistor M4 is turned off by the light emission signal applied through the light emission scan line E _n , the driving transistor M3 and the organic material EL are electrically blocked.

At this time, between the absolute value of the voltage between the gate and the source of the driving transistor M3 (hereinafter referred to as "gate-source voltage") (V _GS ) and the current (I _DATA ) flowing through the transistor (M3) Since the relationship between is established, the gate-source voltage V _GS of the driving transistor M3 is given by Equation 3 below.

Here, β is a constant value and V _TH is an absolute value of the threshold voltage of the driving transistor M3.

Here, V _G is a gate voltage of the driving transistor M3, and V _DD is a voltage supplied to the driving transistor M3 by the power supply voltage VDD.

Next, the scanning line is turned, the switching transistor (M1) and a diode transistor (M3) off in accordance with the flash signal of the selection signal and the emission control line (E _n) of the (S _n), the light-emitting transistor (M4) is turned on.

In this case, it is elevated by 'ΔV _S' by the voltage at the junction capacitor (C2) and a scan line (S _n) to the selection signal. Therefore, the gate voltage V _G of the driving transistor M3 is increased by the coupling of the capacitors C1 and C2, and the rising width ΔV _G is expressed by Equation 4 below.

Here, C ₁ and C ₂ are the capacitances of the capacitors C1 and C2, respectively.

Since the gate voltage V _G of the driving transistor M3 has increased by ΔV _G , the current I _OLED flowing through the transistor M3 is determined as shown in Equation 5 below. That is, since the gate-source voltage V _GS of the transistor M3 decreases as the gate voltage V _G of the driving transistor M3 increases, the size of the drain current I _OLED of the transistor M3 is increased. It can be made smaller than the data current I _DATA . Since the light emitting transistor M4 is turned on by the light emission signal of the light emission control line E _n , the current I _OLED of the driving transistor M3 is supplied to the organic material to emit light.

Further, from equation (5) the data current (I _DATA) may be set to a value greater than the current (I _OLED) flowing so is derived as equation (6), the data current (I _DATA) in the organic material (EL).

Hereinafter, a layout of a display panel according to an exemplary embodiment of the present invention will be described with reference to FIGS. 6 to 8. 6 illustrates a layout structure of a display panel according to an exemplary embodiment, and FIGS. 7 and 8 are cross-sectional views illustrating an interlayer structure.

Referring to this, in the present exemplary embodiment, the unit pixels 110 of the display panel 100 intersect the data line 110 extending in the first direction (the Y-axis direction in the drawing) and the data line 110. Scan lines 120 arranged in a direction (X-axis direction in the drawing) and extending in a direction orthogonal to the data line 110 (Y-axis direction in the drawing) in a state spaced apart from the scan line 120 at regular intervals. Limited by the power supply line 130, the light emission control line 140 arranged in parallel with the scan line 120, and the boost control line 150 arranged in parallel with a constant distance from the light emission control line 140. do.

In this case, the switching transistor M1, the driving transistor M3, the diode transistor M2, and the light emitting transistor M4 constituting the pixel circuit are disposed in a space provided between the scan line 120 and the light emission control line 140. . Accordingly, since the boost control line 150 does not overlap with the elements constituting the pixel circuit described above, signal distortion of the boost signal due to interference of the pixel circuit elements can be prevented. Therefore, since the boost signal can be stably input to the capacitor, the data current I _DATA can be transmitted to the organic material EL more accurately than before.

The arrangement structure of the pixel circuit described above will be described in detail. In the switching transistor M1, a gate electrode is formed on a channel formed near the intersection of the scan line 120 and the data line 110, and the source electrode is formed in the contact hole h1. It is connected to the data line 110 through. The drain electrode is connected to the gate electrode of the driving transistor M3 through the contact holes h2 and h3.

The diode transistor M2 is formed at a point where the data line 110 and the emission control line 140 cross each other, and a source electrode is connected to the data line 110 through a contact hole h1. The gate electrode is formed in common with the gate electrode of the switching transistor M1. In addition, the drain electrode is connected to the drain electrode of the driving transistor M3 through the semiconductor layer.

The driving transistor M3 is formed at the intersection of the scan line 120 and the power line 130, and the gate electrode is connected to the drain electrode of the switching transistor M1 through the contact hole h3. . The source electrode is connected to the power supply line 130 through the contact hole h4, and the drain electrode is connected to the source electrode of the light emitting transistor M4 through the semiconductor layer.

Next, in the light emitting transistor M4, a gate electrode is formed as part of the light emission control line 140, a drain electrode is connected to the pixel electrode through the contact hole h5, and the pixel electrode is connected through the contact hole h6. It is connected with the organic material (EL).

Meanwhile, the capacitors C1 and C2 are formed to overlap the power line 130 adjacent to the long side 201 of the organic material EL, and the gate electrode layer 50 forming the first electrode of the capacitor contacts. It is connected to the gate electrode of the driving transistor M3 through the hole h9. The semiconductor layer 35, which is a polycrystalline silicon layer, is formed to overlap the gate electrode layer to form a second electrode of the capacitor. In this case, the semiconductor 35 layer is connected to the boost control line 150 through the contact holes h7 and h8.

Next, the interlayer structure of the display panel having the unit pixels arranged as described above will be described.

In the display panel 100 of the present exemplary embodiment, a blocking layer 20 made of silicon oxide, silicon nitride, or the like is formed on an insulating substrate 10, and a polycrystalline silicon layer 30, which is a semiconductor layer, is formed on the blocking layer. .

The semiconductor layer 30 includes source regions 31b, 32b, and 33b, drain regions 31c, 32c, and 33c, and channel regions 31a, 32a, and 33a for each transistor. 31b, 32b, 33b) and drain regions 31c, 32c, 33c are each doped with n-type impurities or p-type impurities depending on the driving conditions.

In addition, the semiconductor layers 35 forming the capacitor are formed side by side along the long side 201 of the organic material EL. At this time, the semiconductor layer 35 is formed in a substantially '┛' shape.

On the semiconductor layers 30 and 35, a gate insulating film 40 made of silicon oxide or silicon nitride is formed.

In addition, the gate electrode layer on which the gate lines 51, 52, 53, and 54 of the transistors and the scan line 120 including a conductive film made of a low resistance conductive material, such as aluminum or an aluminum alloy, are formed on the gate insulating film 40. 50 is formed. The emission control line 140 and the boost control line 150 described above are formed on the gate electrode layer 50 with the same material as the scan line 120 or the gate electrodes.

In addition, one electrode of the capacitors C1 and C2 is also formed as the gate electrode layer 50.

More specifically, the gate electrodes 51 and 52 of the switching transistor M1 and the diode transistor M2 are connected to the scan line 120 to form a branch so that the channel regions 31a and 32a of the transistors M1 and M2 are respectively formed. Nested). The gate electrode 53 of the light emitting transistor M4 is separated from the scan line 120 and overlaps the channel region 33a formed of the semiconductor layer 30. In this case, the gate electrode 53 of the light emitting transistor M4 is formed of a part of the light emitting control line 140 formed of the same layer, and the light emitting control line 140 extends in the row direction, thereby channeling the light emitting transistor M4. The gate electrode of the light emitting transistor M4 is formed in contact with the region 33a.

The gate electrode of the driving transistor M3 is separated from the scan line 120 and overlaps the channel region 34a formed of the semiconductor layer 30.

On the other hand, the gate electrode layer 50 is formed in the state overlapping with the semiconductor layer 35 which forms one electrode of a capacitor, and the gate insulating film interposed therebetween. Accordingly, the gate electrode layer 50 forms another electrode of the capacitor. In this state, the gate electrode layer 50 is connected to the gate electrode of the driving transistor M3 through the contact hole h9.

In addition, the boost control line 150 formed of the gate electrode layer may include a gate electrode layer 50 connected to the semiconductor layer 35 constituting a capacitor at a point where the boost control line 150 and the power supply line 130 cross each other. Formed. As a result, the semiconductor layer is formed on the glass substrate 10 and has a laminated structure in which the gate electrode layer 50 is stacked thereon.

The first interlayer insulating layer 60 is formed on the gate electrode layer 50.

Each of the contact holes h7 and h8 for connecting the gate electrode layer 50, which is part of the boost control line, and the semiconductor layer, is formed in the first interlayer insulating layer 60. More specifically, the contact hole h7 is formed on the gate electrode layer 50 forming the boost control line 150 to penetrate the first interlayer insulating layer 60. The contact hole h8 is formed adjacent to the contact hole h7, and the semiconductor layer 35 of the capacitor is formed to penetrate through the first interlayer insulating film 60 and the gate insulating film 40 ( See FIG. 8).

The metal layer 135 is formed on the first interlayer insulating layer 60. Accordingly, the semiconductor layer 35 of the capacitor and the gate layer 50 forming the boost control line 150 are electrically connected to each other through the metal layer 135 and the contact holes h7 and h8.

In addition, a power supply voltage line 130 for supplying a data line 110 and a power supply voltage is formed on the first interlayer insulating layer 60 to contact the electrodes of the transistor through contact holes h1 to h6. have.

The data line 110 has a source region 31b of the switching transistor M1 and a source of the diode transistor M2 through the contact hole h2 penetrating through the first interlayer insulating layer 60 and the gate insulating layer 40. In the state connected to the area | region 32b, respectively, it extends in the column direction.

The power supply line 130 is connected to the source region of the driving transistor M3 through the contact hole h4 penetrating through the first interlayer insulating film 60 and the gate insulating film 40 similarly to the data line 110. In the connected state, it extends in the column direction.

The drain electrode 71 of the light emitting transistor M4 is formed of the same metal layer as the data line 110 and the power line 130. That is, it contacts the drain region of the light emitting transistor M4 through the contact hole h5 penetrating the first interlayer insulating film 60 and the gate insulating film 40.

A second interlayer insulating film 80 made of silicon nitride, silicon oxide, an organic insulating material, or the like is formed on the data line 110, the power supply line 130, and the drain electrode of the light emitting transistor M4. 80 has a contact hole h6 for electrically connecting the organic material EL to the drain electrode 71 of the light emitting transistor M4.

In the organic material EL on the second interlayer insulating layer 80, a pixel electrode 81 connected to the drain electrode 71 of the light emitting transistor M4 is formed through the contact hole h6. The pixel electrode 81 is preferably formed of a material having excellent reflectivity such as aluminum or silver alloy. However, optionally, the pixel electrode 81 may be formed of a transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 81 made of a transparent conductive material may be applied to an organic light emitting device of a bottom emission type that displays an image in a downward direction of the display panel 100. The pixel electrode 81 made of an opaque conductive material may be applied to an organic light emitting device of a top emission type that displays an image in an upper direction of the display panel 100.

An upper portion of the second interlayer insulating layer 80 is formed of an organic insulating material, and partition walls 83 for separating the organic light emitting cells are formed. The partition 83 surrounds the pixel electrode 81 to define a region in which the organic material EL is to be filled. The partition 83 serves as a light shielding film by exposing and developing a photosensitive agent including a black pigment, and at the same time, the forming process can be simplified. The organic light emitting layer 85 is formed in the region on the pixel electrode 81 surrounded by the partition 83. The organic emission layer 85 is made of an organic material EL that emits light of any one of red, green, and blue.

The buffer layer 90 is formed on the organic light emitting layer 85 and the partition 83. The buffer layer 90 may be omitted as necessary.

The common electrode 95 is formed on the buffer layer 90. The common electrode 95 is made of a transparent conductive material such as ITO or IZO. If the pixel electrode 81 is made of a transparent conductive material such as ITO or IZO, the common electrode 95 may be made of a metal having good reflectivity such as aluminum.

Although not shown, an auxiliary electrode may be formed of a metal having low resistance to compensate for the conductivity of the common electrode 95. The auxiliary electrode may be formed between the common electrode 95 and the buffer layer 90 or on the common electrode 95. The auxiliary electrode may be formed in a matrix shape along the partition 83 so as not to overlap the organic light emitting layer 85. .

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto and is intended by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents of the claims to be described.

According to the present invention, it is possible to control the current flowing through the organic material with a large current value, thereby enabling driving by accurate current writing. In addition, it is possible to solve the difference in luminance between cells by compensating for variation in threshold voltage or mobility between pixels generated in the process of the transistor.

1 is an equivalent circuit diagram of an active matrix type organic light emitting device according to the prior art.

2 is a pixel circuit diagram of a conventional current write method for driving an organic light emitting device according to the related art.

3 is a view schematically showing a configuration of an organic light emitting device to which the present invention is applied.

4 is a diagram schematically illustrating an organic light emitting display panel according to an exemplary embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram corresponding to one pixel of FIG. 4.

6 is a diagram illustrating an arrangement structure of an organic light emitting display panel according to an exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view taken along the line II ′ of FIG. 6.

FIG. 8 is a cross-sectional view taken along the line II-II 'of FIG. 6.

Claims (4)

Data lines and power lines in one direction; A scan line selectively intersecting the power line and the data line: an emission control line parallel to the scan line; And a boost control line parallel to the emission control line, wherein the unit pixel is defined. The pixel circuit for driving the unit pixel, First and second thin film transistors configured to transfer data current from the data line in response to a selection signal from the scan line; A third thin film transistor supplying a driving current for emitting an organic material and diode-connected while the data current is transmitted from the first and second thin film transistors; A fourth thin film transistor configured to transfer the driving current from the third thin film transistor to the organic material; A first capacitor storing a first voltage corresponding to a data current from the first thin film transistor; And, And a second capacitor electrically connected between the first capacitor and the boost control line and configured to change the first voltage of the first capacitor to a second voltage through coupling with the first capacitor. , The boost control line and the second capacitor, A semiconductor layer forming one electrode of the second capacitor; A gate electrode layer formed on the semiconductor layer and branched to the boost control line; A first contact hole formed over the gate electrode layer and a second contact hole contacting the semiconductor layer; And, And a metal layer in contact with the semiconductor layer and the gate electrode layer through the first and second contact holes, respectively. The method of claim 1, And the first to fourth thin film transistors are formed in an area defined by the data line, the scan line, the power line, and the light emission control line. The method of claim 2, The first thin film transistor is formed in an area where the data line and the scan line intersect, the second thin film transistor is formed in an area where the data line and the emission control line intersect, and the third thin film transistor is formed in the scan line and the power line. The organic light emitting display panel is formed in the region crossing, the fourth thin film transistor is formed across the emission control line. The method of claim 1, The organic light emitting display panel of which the metal layer is formed of the same material as the data line and the power line.