KR20050111906A - Plasma display panel - Google Patents

Abstract

The present invention discloses a plasma display panel. According to the invention, the lower substrate; A lower dielectric layer formed on the lower substrate; Address electrodes embedded in the lower dielectric layer to be spaced apart; An upper substrate disposed to face the lower substrate; An upper dielectric layer opposite the lower dielectric layer and formed on the upper substrate; Vertical barrier ribs spaced apart from each other with an address electrode disposed between the lower substrate and the upper substrate; A phosphor layer disposed for each space between the vertical partition walls; Embedded in an upper dielectric layer, each consisting of a pair of X and Y electrodes spaced apart from each other by a mutual discharge gap, wherein the X and Y electrodes intersect with the transparent and address electrodes with spaced apart projections with a vertical barrier therebetween; And a bus electrode connected to the protrusions, respectively, wherein Bg / Ig, which is the ratio between Bg, which is the distance between the bus electrode of the X electrode and the bus electrode of the Y electrode, and Ig, which is the distance between the protrusions connected to each bus electrode, is 1.3. Storage electrode pairs disposed so as to be in the range of ˜6.6.

Description

Plasma display panel {Plasma display panel}

The present invention relates to a plasma display panel, and more particularly, to a plasma display panel having an improved structure to ensure discharge stability.

In general, a plasma display panel applies a predetermined voltage to an electrode in a state where gas is charged between electrodes installed in an enclosed space so that a glow discharge occurs, and the plasma display panel is formed by ultraviolet rays generated during the glow discharge. The phosphor layer formed in the pattern is excited to form an image.

The plasma display panel is classified into a direct current type, an alternating current type, or a hybrid type according to a driving method. And, depending on the electrode structure, it is divided into having at least two electrodes required for discharge and having three electrodes. In the case of the DC type, an auxiliary electrode is added to induce an auxiliary discharge. In the case of an AC type, an address electrode is introduced to separate the address discharge and the sustain discharge to improve the address speed. In addition, the AC type may be classified into a counter electrode structure and a surface discharge electrode structure according to the arrangement of the electrodes for discharging. In the case of the counter electrode structure, two sustain electrodes forming a discharge are respectively formed on the substrates. The surface discharge type electrode structure is a structure in which the discharge is formed on one plane of the substrate by placing two sustain electrodes forming the discharge on the same substrate.

1 illustrates a cross-sectional structure of a unit discharge cell provided in a conventional plasma display panel.

Referring to the drawings, in the discharge cell 10, a sustain electrode pair 12 composed of the X electrode 13 and the Y electrode 14 is formed on the lower surface of the upper substrate 11. The X electrode 13 and the Y electrode 14 serve as a common electrode and a scan electrode, respectively, and are spaced apart from each other by a discharge gap g.

The X electrode 13 and the Y electrode 14 are each composed of transparent electrodes 13a and 14a and bus electrodes 13b and 14b which are applied to a lower surface thereof to apply a voltage. The sustain electrode pair 12 is embedded by an upper dielectric layer 15, and a protective layer 16 is formed on a lower surface of the upper dielectric layer 15.

The lower substrate 21 is disposed to face the upper substrate 11, and the address electrode 22 is formed on the lower substrate 21 to intersect the pair of sustain electrodes 12. The address electrode 22 is embedded by the lower dielectric layer 23. The phosphor layer 24 is formed of a fluorescent material on the lower dielectric layer 23. The discharge gas is injected into the discharge cell 10 comprised in this way.

The operation of the plasma display panel with the discharge cells 10 having the above structure will be briefly described as follows.

First, when an address discharge voltage is applied between the address electrode 22 and the Y electrode 14, an address discharge occurs. Thus, a predetermined wall charge is formed in the addressed discharge cell 10. In this state, when the sustain discharge voltage is applied between the X electrode 13 and the Y electrode 14, the sustain discharge occurs. The charges generated by such a discharge collide with the discharge gas, and thus plasma is formed to generate ultraviolet rays. The phosphor layer 24 is excited by the generation of such ultraviolet rays, thereby displaying an image.

On the other hand, the sustain discharge has a mechanism that starts at the discharge gap g between the X electrode 13 and the Y electrode 14 and diffuses along each electrode surface of the X electrode 13 and the Y electrode 14. In the plasma display panel having such a discharge mechanism, efforts have been made to increase the discharge efficiency. For example, the bus electrodes 13b and 14b are disposed closer to the center of the discharge cell 10 while the discharge gap g between the transparent electrodes 13a and 14a is shorter. .

However, such a structure causes strong electric field concentration by bus electrodes disposed close to the center side of the discharge cell, causing a problem of erroneous discharge between adjacent discharge cells.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a plasma display panel capable of ensuring a discharge efficiency and ensuring a sufficient discharge stability.

Plasma display panel according to the present invention for achieving the above object,

A lower substrate;

A lower dielectric layer formed on the lower substrate;

Address electrodes embedded in the lower dielectric layer and spaced apart from each other;

An upper substrate disposed to face the lower substrate;

An upper dielectric layer facing the lower dielectric layer and formed on the upper substrate;

Vertical barrier ribs spaced apart from each other with the address electrode disposed between the lower substrate and the upper substrate;

A phosphor layer disposed for each space between the vertical partition walls;

A pair of X and Y electrodes embedded in the upper dielectric layer and spaced apart from each other by a mutual discharge gap, wherein the X and Y electrodes are provided with transparent electrodes and protrusions spaced apart from each other with the vertical partition interposed therebetween. A bus electrode extending to intersect with the electrodes and connected to the protrusions, respectively, between Bg, the distance between the bus electrode of the X electrode and the bus electrode of the Y electrode, and Ig, the distance between the protrusions connected to each bus electrode. And sustain electrode pairs arranged such that the ratio of Bg / Ig is in the range of 1.3 to 6.6.

Here, it is preferable that the horizontal partitions are further formed on the side surfaces of the vertical partition walls so as to be spaced apart from each other in the direction crossing the vertical partition walls, and partitioned into discharge cells having a matrix shape.

Here, it is preferable that the said Bg value exists in the range of 120-200 micrometers.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is an exploded perspective view of a plasma display panel according to an exemplary embodiment of the present invention, and FIG. 3 is a plan view showing a state in which sustain electrode pairs of FIG. 2 are disposed in discharge cells. 4 is a cross-sectional view taken along the longitudinal bulkhead direction in FIG. 2.

The illustrated plasma display panel 100 includes an upper substrate 111 on which an image is displayed and a lower substrate 131 disposed to face the upper substrate 111. A plurality of sustain electrode pairs 121 are arranged on a surface of the upper substrate 111 facing the lower substrate 131. The sustain electrode pair 121 may include an X electrode 122 and a Y electrode 125. The X electrode 122 may correspond to a common electrode, and the Y electrode 125 may correspond to a scan electrode.

The X electrode 122 and the Y electrode 125 are transparent electrodes 123 and 126, and bus electrodes 124 and 127 connected to one surface of the transparent electrodes 123 and 126, respectively. Equipped with.

The transparent electrodes 123 and 126 are formed of indium tin oxide (ITO), which is a transparent conductor to transmit visible light. In addition, the bus electrodes 124 and 127 apply voltages to the transparent electrodes 123 and 126, respectively, and the electric power of the transparent electrodes 123 and 126 formed of ITO having relatively low electrical conductivity. In order to improve the resistance, it is formed of a metal having excellent conductivity such as silver (Ag) or copper (Cu).

As shown in the drawing, the transparent electrodes 123 and 126 are formed of a plurality of protrusions 123a and 126a, each of which is continuously formed at one end of the protrusions 123a and 126a. The electrodes 124 and 127 are connected at predetermined intervals, respectively, and the other end forms a discharge gap G.

The storage electrode pairs 121 are covered and embedded by an upper dielectric layer 112 formed on the upper substrate 111, and the upper dielectric layer 112 is covered by a protective layer 113 formed of MgO or the like. .

In the lower substrate 131 facing the upper substrate 111, the address electrodes 132 intersect the storage electrode pairs 121 and are formed in a stripe shape on a surface facing the upper substrate 111. .

The address electrodes 132 are covered by a lower dielectric layer 133 formed on the lower substrate 131 and buried therein, and a partition wall 134 is formed on the lower dielectric layer 133 to form the upper substrate 111. ) And the lower substrate 131 are partitioned.

As shown, the barrier ribs 134 are horizontally formed to extend in a direction intersecting the vertical barrier ribs 134a formed at a predetermined interval and the vertical barrier ribs 134a from side surfaces of the vertical barrier ribs 134a, respectively. Partition walls 134b. Here, the vertical partitions 134a are disposed in parallel with one address electrode 132 therebetween.

As the vertical bulkheads 134a and the horizontal bulkheads 134b are formed as described above, the cells are partitioned into discharge cells 135 closed in four surfaces in a matrix form, and cross talk between the discharge cells 135 is performed. Is prevented. When partitioned in the form of a matrix as described above, there is an advantage in that fine pitch, brightness, and efficiency can be increased. On the other hand, the partition wall is not limited to the above, it may be made of a structure such as a stripe shape, a delta shape.

Phosphor is coated on the inner surface of the partition 134 and the upper surface of the lower dielectric layer 133 surrounded by the partition 134 to form the phosphor layer 136. The colors of the phosphors are largely divided into red, green, and blue colors to implement colors, and constitute red, green, and blue phosphor layers 136R, 136G, and 136B according to the color of the phosphor.

The discharge cells 135 may be formed of red, green, and blue discharge cells 135R, 135G, and 135B, respectively, according to the colors of the red, green, and blue phosphor layers 136R, 136G, and 136B. The three adjacent red, green, and blue discharge cells 135R, 135G, and 135B constitute a unit pixel. The discharge cells 135 are filled with a discharge gas in which neon (Ne), xenon (Xe), and the like are mixed. In the state where the discharge gas is filled, the upper and lower substrates 111 and 131 are sealed to each other by a sealing member such as frit glass formed at edges of the upper and lower substrates 111 and 131.

Meanwhile, as shown in FIG. 3, each of the discharge cells 135 in which the phosphor layer 136 is formed as described above, the X electrode 122 and the Y electrode 125 forming the sustain electrode pair 121 are discharge cells ( The discharge cells 135 are respectively introduced into the discharge cells 135 from both edges of the 135, and are arranged to form a discharge gap G.

More specifically, in the transparent electrodes 123 and 126 provided in the X electrode 122 and the Y electrode 125, the divided and spaced protrusions 123a and 126a are discharge cells 135. The vertical bulkheads 134a are disposed to correspond to the spaced apart protrusions 123a and 126a. Here, both side portions of the protrusions 123a and 126a are spaced apart from the adjacent vertical bulkheads 134a at predetermined intervals, respectively. As described above, since the transparent electrodes 123 and 126 have a structure in which portions corresponding to the vertical partitions 134a are deleted, the circuit current may be reduced.

The bus electrodes 124 and 127 connected to the transparent electrodes 123 and 126 are arranged side by side in the direction in which the horizontal partitions 134b are formed, and are spaced apart at predetermined intervals to discharge the discharge cell 135. Are arranged inside each.

When the discharge is started between the X electrode 122 and the Y electrode 125 of the sustain electrode pair 121 disposed in the discharge cell 135 as described above, as shown in Figure 4, from the discharge gap (G) Beginning and spreading along the electrode faces of the X electrode 122 and the Y electrode 125 in a direction away from the discharge gap G, a discharge path as indicated by the dotted line is formed.

In the discharge made as described above, the discharge efficiency and the discharge stability are determined by the spacing between the bus electrodes 124 and 127 disposed for each discharge cell 135, more specifically, the bus electrodes 124 as shown. The gap between the opposing inner surfaces of the () 127 is referred to as Bg, and the distance between the protrusions 123a and 126a of the transparent electrodes 123 and 126 disposed with the vertical partition 134a interposed therebetween. Is influenced according to the Bg and Ig values.

According to one aspect of the present invention, by optimally setting the Ig / Bg value and the Bg and Ig value representing the correlation between Ig and Bg, it is possible to maximize the discharge efficiency and ensure the discharge stability. The Ig / Bg optimum value and the Bg and Ig optimum values may be set based on data obtained through the experiments of Tables 1 and 2.

Table 1 summarizes the data measuring the discharge efficiency according to the Bg value, and Table 2 shows the data of measuring the number of locations where the discharge occurred according to the Bg and Ig values by arbitrarily designating nine positions on the panel. In summary. At this time, as experimental conditions, the panel was 42 "HD, and the discharge cell was set to 304 micrometers (horizontal pitch) x 693 micrometers (vertical pitch), and the bus width was set to 75 micrometers.

Bg (μm) 100 110 120 130 140 150 160 170 180 190 200 210 220 Discharge efficiency (㏐ / W) 2.6 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.2 2.1

Referring to Table 1, the discharge efficiency is the largest when the Bg value is 100㎛, and when the Bg value exceeds 200 it can be seen that the discharge efficiency tends to decrease.

Ig (μm) 0 10 20 30 40 50 60 70 80 90 Bg (μm) 100 9 9 9 9 9 8 7 7 7 6 110 9 9 9 9 9 5 5 5 4 3 120 5 5 5 0 0 0 0 0 0 0 130 3 3 3 0 0 0 0 0 0 0 140 3 One One 0 0 0 0 0 0 0 150 2 One One 0 0 0 0 0 0 0 160 One One One 0 0 0 0 0 0 0 170 One One One 0 0 0 0 0 0 0 180 One One One 0 0 0 0 0 0 0 190 One One One 0 0 0 0 0 0 0 200 One One One 0 0 0 0 0 0 0

Referring to Table 2 above, the case where the misdischarge is not caused even in one place is a case where the Bg value is 120 µm or more and the Ig value is 30 µm or more. On the other hand, when the Bg value is 200 μm or more, it is not preferable because the discharge efficiency is worse, as shown in Table 1, and when the Ig value is 90 μm or more, the area of the transparent electrode becomes too small and the discharge efficiency may be bad. not.

Therefore, the Bg value may be set in the range of 120 to 200 μm, and the Ig value may be set in the range of 30 to 90 μm, respectively. From the Bg and Ig values thus set, the Bg / Ig value may be set in the range of 1.3 to 6.6. Can be. As a result, the discharge efficiency can be maximized and the discharge stability can be sufficiently secured.

As described above, the plasma display panel according to the present invention optimally sets the relationship between the spacing between the bus electrodes arranged for each discharge cell and the spacing between the protrusions of the transparent electrodes arranged with the vertical partition wall interposed therebetween. Thus, the effect of maximizing the discharge efficiency and the discharge plan and at the same time ensuring the discharge stability can be obtained.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

1 is a block diagram of a unit discharge cell according to a conventional example.

2 is an exploded perspective view of a plasma display panel according to an embodiment of the present invention;

3 is a plan view illustrating a state in which sustain electrode pairs are disposed in discharge cells of FIG. 2;

4 is a cross-sectional view taken along the longitudinal bulkhead direction in FIG. 2.

<Brief description of the major symbols in the drawings>

111.Top substrate 112.Top dielectric layer

121..holding electrode pair 122..X electrode

123,126 .. transparent electrode 124,127..bus electrode

125 Y electrode 131 lower substrate

132. Address electrode 133. Lower dielectric layer

134. Bulkhead 135. Discharge cell

136. Phosphor layer G. Discharge gap

Claims (9)

A lower substrate; A lower dielectric layer formed on the lower substrate; Address electrodes embedded in the lower dielectric layer and spaced apart from each other; An upper substrate disposed to face the lower substrate; An upper dielectric layer facing the lower dielectric layer and formed on the upper substrate; Vertical barrier ribs spaced apart from each other with the address electrode disposed between the lower substrate and the upper substrate; A phosphor layer disposed for each space between the vertical partition walls; A pair of X and Y electrodes embedded in the upper dielectric layer and spaced apart from each other by a mutual discharge gap, wherein the X and Y electrodes are provided with transparent electrodes and protrusions spaced apart from each other with the vertical partition interposed therebetween. A bus electrode extending to intersect with the electrodes and connected to the protrusions, respectively, between Bg, the distance between the bus electrode of the X electrode and the bus electrode of the Y electrode, and Ig, the distance between the protrusions connected to each bus electrode. And sustain electrode pairs arranged such that the ratio Bg / Ig is in the range of 1.3 to 6.6. The method of claim 1, And said Bg value is in the range of 120 to 200 mu m. The method of claim 2, And a pitch of the vertical bulkhead is 693 μm. The method of claim 1, Plasma display panel, characterized in that the horizontal partition walls are formed on the side of each vertical partition wall so as to be spaced apart in the direction crossing the vertical partition wall, and divided into discharge cells of the matrix form. The method of claim 4, wherein And said Bg value is in the range of 120 to 200 mu m. The method of claim 1, And the bus electrode is formed of silver (Ag), copper (Cu), or the like. The method according to claim 1 or 6, And the transparent electrode is formed of indium tin oxide (ITO). The method of claim 1, And the phosphor layer is formed over a side surface of the vertical partition wall and an upper surface of the lower dielectric layer. The method of claim 1, And a protective layer is formed on the lower surface of the upper dielectric layer.