KR20050105834A - Method of manufacturing lcos device - Google Patents
Method of manufacturing lcos device Download PDFInfo
- Publication number
- KR20050105834A KR20050105834A KR1020040031106A KR20040031106A KR20050105834A KR 20050105834 A KR20050105834 A KR 20050105834A KR 1020040031106 A KR1020040031106 A KR 1020040031106A KR 20040031106 A KR20040031106 A KR 20040031106A KR 20050105834 A KR20050105834 A KR 20050105834A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- film
- high voltage
- region
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 239000010410 layer Substances 0.000 claims abstract description 28
- 239000011229 interlayer Substances 0.000 claims abstract description 26
- 150000002500 ions Chemical class 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000007943 implant Substances 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/795—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in lateral device isolation regions, e.g. STI
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Power Engineering (AREA)
- Nonlinear Science (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 LCOS 칩의 평탄도(Flatness) 및 반사율(Reflectance)을 개선할 수 있는 LCOS 소자 제조방법을 개시한다. 개시된 본 발명은 LCOS 소자 특성 확보를 위해 반도체 기판 상의 고전압 영역(HVR)에 고농도의 불순물 이온을 주입하여 드리프트 영역을 형성하고, 고전압 영역(HVR)의 NMOS를 위한 필드 스탑 이온을 소자분리막 형성 후에 주입함으로써 LCOS 화소의 누설전류를 개선할 수 있다. 또한, 본 발명은 0.6㎛ 공정에 층간절연막 공정을 추가하여 5％ 이하의 칩 평탄도를 확보할 수 있으며, 미러 금속막을 증착하여 80％ 이상의 반사율을 확보할 수 있다.The present invention discloses an LCOS device manufacturing method capable of improving flatness and reflectance of an LCOS chip. The disclosed invention forms a drift region by implanting a high concentration of impurity ions into a high voltage region (HVR) on a semiconductor substrate to secure LCOS device characteristics, and implants field stop ions for NMOS in the high voltage region (HVR) after forming an isolation layer. As a result, leakage current of the LCOS pixel can be improved. In addition, the present invention can secure a chip flatness of 5% or less by adding an interlayer insulating film process to a 0.6 μm process, and obtain a reflectance of 80% or more by depositing a mirror metal film.
Description
본 발명은 실리콘 상층 액정(Liquid Crystal on Silicon, 이하 LCOS라 함) 에 관한 것으로, 보다 상세하게는, 칩의 평탄도(Flatness) 및 반사율(Reflectance)을 개선할 수 있는 LCOS 소자 제조방법에 관한 것이다.The present invention relates to a liquid crystal on silicon (hereinafter referred to as LCOS), and more particularly, to a method of manufacturing an LCOS device capable of improving flatness and reflectance of a chip. .
최근, 마이크로 디스플레이 중의 하나인 LCOS는 반사형으로 실리콘 웨이퍼를 기판으로 사용하고 화소전극을 반사율이 좋은 금속전극을 이용하여 액정을 반사모드로 사용하고 있다. 또한, 실리콘 웨이퍼를 기판으로 사용하므로, HTPS(High Temperature Poly Silicon) 방식의 디스플레이 보다 높은 운동성의 전자를 가지는 장점을 가지고 있다. 이로 인해 온 스크린(On-Screen)과 오프 스크린(Off-Screen) 양쪽 모두 좋은 품질을 갖는 회로를 제작할 수 있다. 그리고, LCOS 디스플레이는 온 스크린 트랜지스터와 어드레스 라인을 반사형 상부 전극 아래에 숨길 수 있는데, 이것으로 구경비(Aperture Ratio)와 밀도를 높게 할 수 있으며, 단순한 제작 과정을 갖기 때문에 비용이 절감된다.Recently, LCOS, one of the micro displays, uses a liquid crystal in a reflection mode by using a silicon wafer as a substrate as a reflection type and a metal electrode having good reflectance. In addition, since the silicon wafer is used as the substrate, it has the advantage of having electrons of higher mobility than the display of the HTPS (High Temperature Poly Silicon) method. This makes it possible to produce circuits of good quality for both on-screen and off-screen. In addition, the LCOS display can hide on-screen transistors and address lines underneath the reflective top electrode, which increases aperture ratio and density, and saves costs due to the simple manufacturing process.
LCOS 칩 구현을 위해 0.6㎛ 및 16V 공정 조건을 사용하는 소자 즉, DDD(Double Doped Drain) 구조를 가진 소자를 말하며, 이 구조를 동일하게 LCOS 화소 구조에 적용할 경우에는 전압에 따라 화소당 스탠바이 전류(Standby Current)가 100fA/cell 이상을 나타내어 스탠바이 전류가 100fA/cell 이하을 만족해야 하는 규격을 벗어나므로 적합하지 않다.It refers to the device using the 0.6μm and 16V process conditions for implementing the LCOS chip, that is, the device having the double doped drain (DDD) structure.If the same structure is applied to the LCOS pixel structure, the standby current per pixel depends on the voltage. It is not suitable because (Standby Current) is over 100fA / cell, so the standby current is out of the specification to satisfy 100fA / cell or less.
따라서, LCOS 칩 구현을 위해 0.6㎛ 및 16V 공정 조건을 사용하는 소자를 적용하게 되면, 화소의 누설전류(Leakage Current)와 칩의 거칠기(Chip Roughness) 등으로 인해 LCOS 칩 고유의 특성을 확보할 수 없게 된다.Therefore, when the device using the 0.6㎛ and 16V process conditions are applied to implement the LCOS chip, the unique characteristics of the LCOS chip can be obtained due to the leakage current of the pixel and the chip roughness of the chip. There will be no.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 칩의 평탄도 및 반사율을 개선할 수 있는 LCOS 소자의 제조방법을 제공함에 그 목적이 있다. Accordingly, an object of the present invention is to provide a method for manufacturing an LCOS device capable of improving the flatness and reflectivity of a chip, which has been devised to solve the above problems.
상기와 같은 목적을 달성하기 위하여, 본 발명은 고전압 영역과 저전압 영역으로 구성되는 반도체 기판을 제공하는 단계; 상기 기판 상의 고전압 영역과 저전압 영역에 N웰 및 P웰영역을 형성하는 단계; 상기 기판 상의 고전압 영역에 고농도의 불순물 이온을 주입하여 드리프트 영역을 형성하는 단계; 상기 기판 상의 저전압 영역 및 고전압 영역에 고전압용 게이트 산화막을 형성하는 단계; 상기 기판 상의 저전압 영역 및 고전압 영역 트랜지스터의 문턱전압을 조절하기 위해 이온을 주입하는 단계; 상기 기판 상의 저전압 영역에 형성된 고전압용 게이트 산화막을 제거한 후에 저전압 영역에 저전압용 게이트 산화막을 형성하는 단계; 상기 기판 상의 저전압 영역 및 고전압 영역에 저전압용 및 고전압용 게이트를 형성하는 단계; 상기 저전압용 게이트 양측 기판 상에 이온주입 공정을 실시하여 LDD 영역을 형성하는 단계; 상기 저전압용 및 고전압용 게이트 양측 기판 상에 이온주입 공정을 실시하여 소오스/드레인 영역을 형성하는 단계; 상기 저전압용 및 고전압용 게이트를 포함한 기판 결과물 상에 버퍼산화막을 형성하는 단계; 상기 소자분리막 상부의 버퍼산화막 상에 폴리실리콘막으로 이루어지는 화소용 제1게이트를 형성하는 단계; 상기 화소용 제1게이트를 포함한 상기 버퍼산화막 상에 산화막 및 질화막을 형성하는 단계; 상기 화소용 제1게이트의 소정부분이 노출되도록 질화막 상에 폴리실리콘막으로 이루어지는 화소용 제2게이트를 형성하는 단계; 상기 기판 결과물 상에 층간절연막을 형성한 후에 층간절연막 표면을 CMP하는 단계; 상기 층간절연막을 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀 표면에 티타늄/티타늄질화막 및 텅스텐막을 증착한 후에 상기 층간절연막이 노출되도록 텅스텐막을 에치백하는 단계; 상기 기판 결과물 상에 알루미늄막을 증착한 후에 알루미늄막을 식각하여 트렌치를 형성하는 단계; 상기 트렌치 표면 상에 TEOS막을 형성한 후에 상기 트렌치가 매립되도록 필드 산화막을 형성하는 단계; 및 상기 알루미늄막이 노출되도록 TEOS막에 에치백하여 금속배선을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a semiconductor substrate comprising a high voltage region and a low voltage region; Forming N well and P well regions in the high voltage region and the low voltage region on the substrate; Implanting a high concentration of impurity ions into a high voltage region on the substrate to form a drift region; Forming a high voltage gate oxide film in a low voltage region and a high voltage region on the substrate; Implanting ions to adjust the threshold voltages of the low voltage region and high voltage region transistors on the substrate; Removing the high voltage gate oxide film formed in the low voltage region on the substrate and forming a low voltage gate oxide film in the low voltage region; Forming low and high voltage gates in a low voltage region and a high voltage region on the substrate; Forming an LDD region by performing an ion implantation process on both substrates of the low voltage gate; Forming a source / drain region by performing an ion implantation process on both of the low voltage and high voltage gate substrates; Forming a buffer oxide film on a substrate product including the low voltage and high voltage gates; Forming a first gate for pixels formed of a polysilicon layer on the buffer oxide layer on the device isolation layer; Forming an oxide film and a nitride film on the buffer oxide film including the pixel first gate; Forming a second gate for pixels made of a polysilicon film on the nitride film so that a predetermined portion of the first gate for pixels is exposed; CMPing the interlayer dielectric surface after forming the interlayer dielectric on the substrate resultant; Etching the interlayer insulating layer to form a contact hole; Depositing a titanium / titanium nitride film and a tungsten film on the contact hole surface and etching back the tungsten film to expose the interlayer insulating film; Forming a trench by etching an aluminum film after depositing an aluminum film on the substrate resultant; Forming a field oxide film to fill the trench after forming a TEOS film on the trench surface; And forming a metal wiring by etching back to the TEOS film so that the aluminum film is exposed.
여기에서, 드리프트 영역을 형성하는 단계와 고전압용 게이트 산화막을 형성하는 단계 사이에 상기 기판 상의 고전압 영역에 고농도의 불순물 이온을 주입하여 드리프트 영역을 형성하는 단계; 상기 저전압 영역에 NMOS 트랜지스터 및 고전압 영역에 PMOS 트랜지스터를 위한 필드 스탑 이온을 주입하는 단계; 상기 기판의 액티브 영역을 제외한 나머지 영역에 필드산화막을 형성하여 소자분리막을 형성하는 단계; 및 상기 고전압 영역에 NMOS 트랜지스터를 위한 필드 스탑 이온을 주입하는 단계를 더 포함하는 것을 특징으로 한다.And forming a drift region by implanting a high concentration of impurity ions into the high voltage region on the substrate between the step of forming a drift region and the step of forming a high voltage gate oxide film; Implanting field stop ions for an NMOS transistor in the low voltage region and a PMOS transistor in a high voltage region; Forming a device isolation film by forming a field oxide film on a region other than the active region of the substrate; And implanting field stop ions for an NMOS transistor in the high voltage region.
상기 층간절연막 표면을 CMP하는 단계는 층간절연막이 1㎛의 두께를 갖도록 CMP 하는 것을 특징으로 한다.CMP the surface of the interlayer insulating film is characterized in that the CMP to have a thickness of 1㎛.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1g는 본 발명의 실시예에 따른 LCOS 소자의 제조방법을 설명하기 위한 공정별 단면도이다. 1A to 1G are cross-sectional views of processes for describing a method of manufacturing an LCOS device according to an exemplary embodiment of the present invention.
도 1a를 참조하면, 고전압 영역(HVR)과 저전압 영역(LVR)으로 구성되는 반도체 기판(10)을 마련한다. 상기 기판(10) 상의 고전압 영역(HVR)과 저전압 영역(LVR)에 N웰 및 P웰영역(13a, 13b)을 형성한 다음, 상기 N웰 및 P웰영역에 주입된 이온들이 확산되도록 기판 결과물에 대해 열처리를 실시한다.Referring to FIG. 1A, a semiconductor substrate 10 including a high voltage region HVR and a low voltage region LVR is provided. After forming the N well and P well regions 13a and 13b in the high voltage region HVR and the low voltage region LVR on the substrate 10, and then implanting the ions implanted in the N well and P well regions. The heat treatment is performed.
이어서, 상기 기판(10) 상의 고전압 영역(HVR)에 NMOS 및 PMOS를 형성하기 위해 고농도의 N형 및 P형 불순물 이온을 주입하여 N형 및 P형 드리프트 영역(Drift :14a, 14b)을 형성한 다음, N형 및 P형 드리프트 영역에 주입된 이온들이 확산되도록 기판 결과물에 대해 열처리를 실시한다.Subsequently, high concentrations of N-type and P-type impurity ions are implanted to form NMOS and PMOS in the high-voltage region HVR on the substrate 10 to form N-type and P-type drift regions (Drift: 14a, 14b). Next, heat treatment is performed on the substrate resultant so that the ions implanted in the N-type and P-type drift regions are diffused.
그 다음, 상기 기판(10) 내에 소자분리막을 형성하기 위해 액티브 영역은 포토 레지스트(미도시)로 마스킹한 후에 저전압 영역(LVR)에 NMOS 트랜지스터를 위한 필드 스탑(Field Stop) 이온을 주입한다. 이어서, 상기 고전압 영역(HVR)에 PMOS 트랜지스터를 위한 필드 스탑 이온을 주입한 후에 상기 필드 산화막(15a)을 형성한다. 그 다음, 상기 고전압 영역(HVR)에 NMOS 트랜지스터를 위한 필드 스탑 이온을 주입하여 저전압 영역(LVR) 및 고전압 영역(HVR)에 소자분리막(15)을 형성한다.The active region is then masked with a photoresist (not shown) to form an isolation layer in the substrate 10, and then field stop ions for the NMOS transistor are implanted into the low voltage region LVR. Subsequently, the field oxide film 15a is formed after implanting field stop ions for the PMOS transistor into the high voltage region HVR. After that, field stop ions for the NMOS transistor are implanted into the high voltage region HVR to form the device isolation layer 15 in the low voltage region LVR and the high voltage region HVR.
도 1b를 참조하면, 상기 기판(10) 상의 저전압 영역(LVR) 및 고전압 영역(HVR)에 고전압용 게이트 산화막(16)을 형성한 후에 NMOS 및 PMOS 트랜지스터의 문턱전압을 조절하기 이온주입 공정을 실시한다. 그 다음, 상기 저전압 영역(LVR)의 NMOS 및 PMOS 트랜지스터의 문턱전압을 조절하기 이온주입 공정을 실시한 후에 저전압 영역(LVR) 상에 형성된 고전압용 게이트 산화막(16)을 제거한 후에 상기 기판(10) 상의 저전압 영역(LVR)에 저전압용 게이트 산화막(17)을 형성한다. Referring to FIG. 1B, after forming the high voltage gate oxide layer 16 in the low voltage region LVR and the high voltage region HVR on the substrate 10, an ion implantation process is performed to adjust threshold voltages of NMOS and PMOS transistors. do. Next, after the ion implantation process is performed to adjust the threshold voltages of the NMOS and PMOS transistors in the low voltage region LVR, the high voltage gate oxide layer 16 formed on the low voltage region LVR is removed, and then on the substrate 10. A low voltage gate oxide film 17 is formed in the low voltage region LVR.
도 1c를 참조하면, 상기 기판(10) 상의 저전압 영역(LVR) 및 고전압 영역(HVR)에 폴리실리콘막과 텅스텐실리사이드막 및 하드마스크막의 적층구조로 이루어지는 고전압용 및 저전압용 게이트(18a, 18b)를 형성한다. 여기에서, 상기 폴리실리콘막과 텅스텐실리사이드막 및 하드마스크막은 각각 1500, 1200 및 1500Å의 두께로 형성한다.Referring to FIG. 1C, high-voltage and low-voltage gates 18a and 18b formed of a laminated structure of a polysilicon film, a tungsten silicide film, and a hard mask film in the low voltage region LVR and the high voltage region HVR on the substrate 10 are illustrated. To form. Herein, the polysilicon film, the tungsten silicide film, and the hard mask film are formed to have thicknesses of 1500, 1200, and 1500 GPa, respectively.
이어서, 상기 저전압용 게이트(18b) 양측 기판 상에 이온주입 공정을 실시하여 LDD 영역(19a, 19b)을 형성한 후에 상기 저전압용 및 고전압용 게이트(18a, 18b) 양측벽에 스페이서(20)를 형성한다. Subsequently, an ion implantation process is performed on both sides of the low voltage gate 18b to form LDD regions 19a and 19b, and then spacers 20 are formed on both side walls of the low voltage and high voltage gates 18a and 18b. Form.
그 다음, 상기 저전압용 및 고전압용 게이트(18a, 18b) 양측의 기판 상에 이온주입 공정을 실시하여 소오스/드레인 영역(21a, 21b)을 형성한 다음, 상기 소오스/드레인 영역(21a, 21b)에 주입된 불순물 이온들을 활성화시키기 위해 기판 결과물에 대해 열처리를 실시한다.Then, an ion implantation process is performed on the substrates on both sides of the low voltage and high voltage gates 18a and 18b to form source / drain regions 21a and 21b, and then the source / drain regions 21a and 21b. Heat treatment is performed on the substrate resultant to activate the impurity ions implanted in the.
도 1d를 참조하면, 화소(Pixel)를 형성하기 위해 상기 저전압용 및 고전압용 게이트(18a, 18b)를 포함한 기판 결과물 상에 버퍼산화막(22)을 형성한다. 이어서, 상기 버퍼산화막(22) 상에 폴리실리콘막을 형성한 후에 상기 폴리실리콘막을 식각하여 화소용 제1게이트(23)를 형성한다. 여기에서, 상기 버퍼산화막(22) 및 폴리실리콘막은 각각 2000Å의 두께로 형성한다. Referring to FIG. 1D, a buffer oxide layer 22 is formed on a substrate product including the low voltage and high voltage gates 18a and 18b to form a pixel. Subsequently, after the polysilicon layer is formed on the buffer oxide layer 22, the polysilicon layer is etched to form the first gate 23 for pixels. Here, the buffer oxide film 22 and the polysilicon film are each formed to a thickness of 2000 kPa.
그 다음, 상기 화소용 제1게이트(23)를 포함한 상기 버퍼산화막(22) 상에 산화막(24) 및 질화막(25)을 형성한 다음, 상기 질화막(25) 상에 폴리실리콘막을 형성한 후에 상기 화소용 제1게이트(23)의 소정부분이 노출되도록 폴리실리콘막을 식각하여 화소용 제2게이트(26)를 형성한다. 여기에서, 상기 산화막(24) 및 질화막(25)은 70 및 140Å의 두께로 형성한다.Next, an oxide film 24 and a nitride film 25 are formed on the buffer oxide film 22 including the pixel first gate 23, and then a polysilicon film is formed on the nitride film 25. The polysilicon layer is etched to expose a predetermined portion of the pixel first gate 23 to form the pixel second gate 26. Here, the oxide film 24 and the nitride film 25 are formed to a thickness of 70 and 140 kHz.
도 1e를 참조하면, 상기 기판 결과물 상에 제1층간절연막(27)을 형성한 후에 상기 제1층간절연막(27)을 식각하여 콘택홀(28)을 형성하고, 상기 콘택홀을 매립하도록 티타늄/티타늄질화막 및 텅스텐막을 형성한 후에 상기 제1층간절연막(27)이 노출되도록 에치백(Etch-Back)을 실시한다.Referring to FIG. 1E, after the first interlayer insulating layer 27 is formed on the substrate resultant, the first interlayer insulating layer 27 is etched to form a contact hole 28 to fill the contact hole. After forming the titanium nitride film and the tungsten film, an etch-back is performed to expose the first interlayer insulating film 27.
그 다음, 상기 기판 결과물 상에 제2층간절연막(29)을 형성한 후에 LCOS 칩의 평탄도를 확보하기 위해 제2층간절연막(29) 표면을 CMP한다. 이어서, 상기 제2층간절연막(29)을 식각하여 제1비아홀(30)을 형성하고, 상기 제1비아홀을 매립하도록 티타늄/티타늄질화막 및 텅스텐막을 형성한 후에 상기 제2층간절연막(29)이 노출되도록 에치백을 실시한다.Next, after forming the second interlayer insulating film 29 on the substrate resultant, the surface of the second interlayer insulating film 29 is CMP to secure the flatness of the LCOS chip. Subsequently, the second interlayer insulating layer 29 is etched to form a first via hole 30, and a titanium / titanium nitride film and a tungsten film are formed to fill the first via hole, and then the second interlayer insulating layer 29 is exposed. Etch back if possible.
도 1f를 참조하면, 상기 기판 결과물 상에 제3층간절연막(31)을 형성한 후에 LCOS 칩의 평탄도를 확보하기 위해 제3층간절연막의 두께가 1㎛가 되도록 제3층간절연막(31) 표면을 CMP한다. 이때, 상기 제3층간절연막(31) 표면을 CMP함으로써 빛의 공명을 방지할 수 있다.Referring to FIG. 1F, after the third interlayer dielectric layer 31 is formed on the substrate, the third interlayer dielectric layer 31 has a surface thickness of 1 μm so as to secure flatness of the LCOS chip. CMP. In this case, the resonance of the light may be prevented by CMPing the surface of the third interlayer insulating layer 31.
이어서, 상기 제3층간절연막(31)을 식각하여 제2비아홀(32)을 형성하고, 상기 제2비아홀을 매립하도록 티타늄/티타늄질화막 및 텅스텐막을 형성한 후에 상기 제3층간절연막(31)이 노출되도록 에치백을 실시한다.Subsequently, the third interlayer insulating layer 31 is etched to form a second via hole 32, and a titanium / titanium nitride film and a tungsten film are formed to fill the second via hole, and then the third interlayer insulating layer 31 is exposed. Etch back if possible.
도 1g에 도시된 바와 같이, 상기 기판 결과물 상에 알루미늄막(33)을 증착하여 미러 금속막(Mirror Metal)을 형성하고, 상기 알루미늄막(33)을 식각하여 트렌치(34)를 형성한다. 그 다음, 상기 트렌치(34) 표면 상에 TEOS막(35)을 형성한 후에 상기 트렌치를 매립되도록 필드 산화막(36)을 형성하고, 상기 알루미늄막(33)이 노출되도록 TEOS막(35)에 에치백을 실시하여 금속배선(37)을 형성한다. As illustrated in FIG. 1G, an aluminum film 33 is deposited on the substrate resultant to form a mirror metal, and the aluminum film 33 is etched to form a trench 34. Next, after forming the TEOS film 35 on the trench 34 surface, the field oxide film 36 is formed to fill the trench, and the TEOS film 35 is exposed to expose the aluminum film 33. The back wiring is performed to form the metal wiring 37.
여기에서, 필드 산화막으로 트렌치를 매립하는 이유는 LCOS 소자의 반사율 특성을 확보하기 위해서이며, 필드 산화막은 에치백 물질이 아니지만, LCOS 공정 특성상 알루미늄막이 그대로 노출되므로, HSG막보다는 무기 물질인 필드 산화막이 유리하기 때문이다.The reason for filling the trench with the field oxide film is to secure reflectance characteristics of the LCOS element. The field oxide film is not an etch back material, but the aluminum film is exposed as it is due to the LCOS process characteristics. Because it is advantageous.
이어서, 상기 기판 결과물 상에 보호막(38)을 형성한다. 이때, 상기 보호막(38)은 실리콘질화막으로 형성하며, 반사율에 영향을 미치지 않는 범위에서 형성한다.Subsequently, a protective film 38 is formed on the substrate resultant. In this case, the protective film 38 is formed of a silicon nitride film and is formed in a range that does not affect the reflectance.
이후, 공지의 후속 공정을 진행하여 LCOS 소자를 완성한다.Thereafter, known subsequent steps are performed to complete the LCOS device.
전술한 바와 같이, LCOS 소자 특성 확보를 위해 반도체 기판 상의 고전압 영역(HVR)에 고농도의 불순물 이온을 주입하여 드리프트 영역을 형성하고, 고전압 영역(HVR)의 NMOS를 위한 필드 스탑 이온을 소자분리막 형성 후에 주입함으로써 LCOS 화소의 누설전류를 개선할 수 있다. As described above, in order to secure the characteristics of the LCOS device, a high concentration of impurity ions are implanted into the high voltage region (HVR) on the semiconductor substrate to form a drift region, and the field stop ions for the NMOS of the high voltage region (HVR) are formed after the device isolation layer is formed. The injection can improve the leakage current of the LCOS pixel.
또한, 본 발명은 0.6㎛ 공정에 층간절연막 공정을 추가하여 5％ 이하의 칩 평탄도를 확보할 수 있으며, 미러 금속막을 증착하여 80％ 이상의 반사율을 확보할 수 있다.In addition, the present invention can secure a chip flatness of 5% or less by adding an interlayer insulating film process to a 0.6 μm process, and obtain a reflectance of 80% or more by depositing a mirror metal film.
이상, 본 발명을 몇 가지 예를 들어 설명하였으나, 본 발명은 이에 한정되는 것은 아니며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 본 발명의 사상에서 벗어나지 않으면서 많은 수정과 변형을 가할 수 있음을 이해할 것이다.In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person of ordinary skill in the art may make many modifications and variations without departing from the spirit of the present invention. I will understand.
이상에서와 같이, 본 발명은 LCOS 소자 특성 확보를 위해 반도체 기판 상의 고전압 영역에 고농도의 불순물 이온을 주입하여 드리프트 영역을 형성하고, 고전압 영역의 NMOS를 위한 필드 스탑 이온을 소자분리막 형성 후에 주입함으로써 LCOS 화소의 누설전류를 개선할 수 있으며, 0.6㎛ 공정에 층간절연막 공정을 추가하여 5％ 이하의 칩 평탄도를 확보할 수 있으며, 미러 금속막을 증착하여 80％ 이상의 반사율을 확보할 수 있다.As described above, the present invention forms a drift region by implanting a high concentration of impurity ions into a high voltage region on the semiconductor substrate to secure the characteristics of the LCOS device, and by implanting field stop ions for NMOS in the high voltage region after forming the device isolation film The leakage current of the pixel can be improved, a chip flatness of 5% or less can be secured by adding an interlayer insulating film process to a 0.6 μm process, and a reflectance of 80% or more can be secured by depositing a mirror metal film.
도 1a 내지 도 1g는 본 발명의 실시예에 따른 LCOS 소자의 제조방법을 설명하기 위한 공정별 단면도.1A to 1G are cross-sectional views illustrating processes for manufacturing a LCOS device according to an exemplary embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 기판 13a, 13b : N웰 및 P웰10: substrate 13a, 13b: N well and P well
14a, 14b : 드리프트 영역 15 : 소자분리막14a, 14b: Drift region 15: Device isolation film
16 : 고전압용 게이트 산화막 17 : 저전압용 게이트 산화막16: high voltage gate oxide film 17 low voltage gate oxide film
18a, 18b : 고전압 및 저전압 게이트 19a, 19b : LDD 영역18a, 18b: high and low voltage gates 19a, 19b: LDD region
21a, 21b: 소오스/드레인 영역 23 : 화소용 제1게이트21a, 21b: source / drain regions 23: first gate for pixels
26 : 화소용 제2게이트 33 : 알루미늄막26 second gate 33 for pixels 33 aluminum film
34 : 트렌치 35 : TEOS막34: trench 35: TEOS film
36 : 필드산화막 37 : 금속배선36: field oxide film 37: metal wiring
38 : 보호막38: protective film
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020040031106A KR101032116B1 (en) | 2004-05-03 | 2004-05-03 | Manufacturing method of LC OS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020040031106A KR101032116B1 (en) | 2004-05-03 | 2004-05-03 | Manufacturing method of LC OS device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20050105834A true KR20050105834A (en) | 2005-11-08 |
| KR101032116B1 KR101032116B1 (en) | 2011-05-02 |
Family
ID=37282941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020040031106A Expired - Fee Related KR101032116B1 (en) | 2004-05-03 | 2004-05-03 | Manufacturing method of LC OS device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR101032116B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024186093A1 (en) * | 2023-03-06 | 2024-09-12 | 주식회사 알바트레이스 | Lcos and manufacturing method therefor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030054019A (en) * | 2001-12-24 | 2003-07-02 | 주식회사 하이닉스반도체 | Method for manufacturing of semiconductor device |
| KR100590249B1 (en) * | 2002-10-14 | 2006-06-15 | 삼성에스디아이 주식회사 | Organic light emitting display device and manufacturing method thereof |
-
2004
- 2004-05-03 KR KR1020040031106A patent/KR101032116B1/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024186093A1 (en) * | 2023-03-06 | 2024-09-12 | 주식회사 알바트레이스 | Lcos and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101032116B1 (en) | 2011-05-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8049283B2 (en) | Semiconductor device with deep trench structure | |
| US7256092B2 (en) | Method for fabricating integrated circuits having both high voltage and low voltage devices | |
| KR101032116B1 (en) | Manufacturing method of LC OS device | |
| US6987038B2 (en) | Method for fabricating MOS field effect transistor | |
| US7033932B2 (en) | Method for fabricating a semiconductor device having salicide | |
| KR20040007949A (en) | Method of manufacture semiconductor device | |
| KR100929428B1 (en) | Liquid Crystal Display Manufacturing Method | |
| KR100934828B1 (en) | MOSFET forming method of semiconductor device | |
| US20090090991A1 (en) | Method for Manufacturing Semiconductor Device | |
| KR100459930B1 (en) | Method of making partial self-aligned salicide contact | |
| KR100774801B1 (en) | Multi-gate insulating film formation method | |
| KR100314478B1 (en) | A method for forming a gate electrode of a semiconductor device | |
| KR100588781B1 (en) | Semiconductor device and manufacturing method | |
| KR20030052481A (en) | Method of manufacturing a semiconductor device | |
| KR100982961B1 (en) | Method for fabricating semiconductor device | |
| KR20030049352A (en) | Method of manufacturing a semiconductor device | |
| KR100395911B1 (en) | Method for manufacturing semiconductor device | |
| KR100741908B1 (en) | Manufacturing method of semiconductor device | |
| KR100564432B1 (en) | Transistor manufacturing method | |
| KR100905182B1 (en) | Semiconductor device formation method | |
| JP2001326347A (en) | Semiconductor device and its manufacturing method | |
| KR20040002137A (en) | method for fabricating of semiconductor device | |
| KR20020051504A (en) | Method for forming contact in semiconductor device | |
| KR20030050681A (en) | Method for fabricating dual gate oxide | |
| KR20040099617A (en) | Manufacturing method for semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20040503 |
|
| N231 | Notification of change of applicant | ||
| PN2301 | Change of applicant |
Patent event date: 20041006 Comment text: Notification of Change of Applicant Patent event code: PN23011R01D |
|
| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20090430 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 20040503 Comment text: Patent Application |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20101025 Patent event code: PE09021S01D |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20110419 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20110422 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 20110425 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| FPAY | Annual fee payment |
Payment date: 20140318 Year of fee payment: 4 |
|
| PR1001 | Payment of annual fee |
Payment date: 20140318 Start annual number: 4 End annual number: 4 |
|
| FPAY | Annual fee payment |
Payment date: 20160318 Year of fee payment: 6 |
|
| PR1001 | Payment of annual fee |
Payment date: 20160318 Start annual number: 6 End annual number: 6 |
|
| FPAY | Annual fee payment |
Payment date: 20170316 Year of fee payment: 7 |
|
| PR1001 | Payment of annual fee |
Payment date: 20170316 Start annual number: 7 End annual number: 7 |
|
| FPAY | Annual fee payment |
Payment date: 20180316 Year of fee payment: 8 |
|
| PR1001 | Payment of annual fee |
Payment date: 20180316 Start annual number: 8 End annual number: 8 |
|
| FPAY | Annual fee payment |
Payment date: 20190318 Year of fee payment: 9 |
|
| PR1001 | Payment of annual fee |
Payment date: 20190318 Start annual number: 9 End annual number: 9 |
|
| PC1903 | Unpaid annual fee |
Termination category: Default of registration fee Termination date: 20220203 |