KR20050105834A - Method of manufacturing lcos device - Google Patents

Abstract

The present invention discloses an LCOS device manufacturing method capable of improving flatness and reflectance of an LCOS chip. The disclosed invention forms a drift region by implanting a high concentration of impurity ions into a high voltage region (HVR) on a semiconductor substrate to secure LCOS device characteristics, and implants field stop ions for NMOS in the high voltage region (HVR) after forming an isolation layer. As a result, leakage current of the LCOS pixel can be improved. In addition, the present invention can secure a chip flatness of 5% or less by adding an interlayer insulating film process to a 0.6 μm process, and obtain a reflectance of 80% or more by depositing a mirror metal film.

Description

Manufacturing Method of LCOS Device {METHOD OF MANUFACTURING LCOS DEVICE}

The present invention relates to a liquid crystal on silicon (hereinafter referred to as LCOS), and more particularly, to a method of manufacturing an LCOS device capable of improving flatness and reflectance of a chip. .

Recently, LCOS, one of the micro displays, uses a liquid crystal in a reflection mode by using a silicon wafer as a substrate as a reflection type and a metal electrode having good reflectance. In addition, since the silicon wafer is used as the substrate, it has the advantage of having electrons of higher mobility than the display of the HTPS (High Temperature Poly Silicon) method. This makes it possible to produce circuits of good quality for both on-screen and off-screen. In addition, the LCOS display can hide on-screen transistors and address lines underneath the reflective top electrode, which increases aperture ratio and density, and saves costs due to the simple manufacturing process.

It refers to the device using the 0.6μm and 16V process conditions for implementing the LCOS chip, that is, the device having the double doped drain (DDD) structure.If the same structure is applied to the LCOS pixel structure, the standby current per pixel depends on the voltage. It is not suitable because (Standby Current) is over 100fA / cell, so the standby current is out of the specification to satisfy 100fA / cell or less.

Therefore, when the device using the 0.6㎛ and 16V process conditions are applied to implement the LCOS chip, the unique characteristics of the LCOS chip can be obtained due to the leakage current of the pixel and the chip roughness of the chip. There will be no.

Accordingly, an object of the present invention is to provide a method for manufacturing an LCOS device capable of improving the flatness and reflectivity of a chip, which has been devised to solve the above problems.

In order to achieve the above object, the present invention provides a semiconductor substrate comprising a high voltage region and a low voltage region; Forming N well and P well regions in the high voltage region and the low voltage region on the substrate; Implanting a high concentration of impurity ions into a high voltage region on the substrate to form a drift region; Forming a high voltage gate oxide film in a low voltage region and a high voltage region on the substrate; Implanting ions to adjust the threshold voltages of the low voltage region and high voltage region transistors on the substrate; Removing the high voltage gate oxide film formed in the low voltage region on the substrate and forming a low voltage gate oxide film in the low voltage region; Forming low and high voltage gates in a low voltage region and a high voltage region on the substrate; Forming an LDD region by performing an ion implantation process on both substrates of the low voltage gate; Forming a source / drain region by performing an ion implantation process on both of the low voltage and high voltage gate substrates; Forming a buffer oxide film on a substrate product including the low voltage and high voltage gates; Forming a first gate for pixels formed of a polysilicon layer on the buffer oxide layer on the device isolation layer; Forming an oxide film and a nitride film on the buffer oxide film including the pixel first gate; Forming a second gate for pixels made of a polysilicon film on the nitride film so that a predetermined portion of the first gate for pixels is exposed; CMPing the interlayer dielectric surface after forming the interlayer dielectric on the substrate resultant; Etching the interlayer insulating layer to form a contact hole; Depositing a titanium / titanium nitride film and a tungsten film on the contact hole surface and etching back the tungsten film to expose the interlayer insulating film; Forming a trench by etching an aluminum film after depositing an aluminum film on the substrate resultant; Forming a field oxide film to fill the trench after forming a TEOS film on the trench surface; And forming a metal wiring by etching back to the TEOS film so that the aluminum film is exposed.

And forming a drift region by implanting a high concentration of impurity ions into the high voltage region on the substrate between the step of forming a drift region and the step of forming a high voltage gate oxide film; Implanting field stop ions for an NMOS transistor in the low voltage region and a PMOS transistor in a high voltage region; Forming a device isolation film by forming a field oxide film on a region other than the active region of the substrate; And implanting field stop ions for an NMOS transistor in the high voltage region.

CMP the surface of the interlayer insulating film is characterized in that the CMP to have a thickness of 1㎛.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1G are cross-sectional views of processes for describing a method of manufacturing an LCOS device according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, a semiconductor substrate 10 including a high voltage region HVR and a low voltage region LVR is provided. After forming the N well and P well regions 13a and 13b in the high voltage region HVR and the low voltage region LVR on the substrate 10, and then implanting the ions implanted in the N well and P well regions. The heat treatment is performed.

Subsequently, high concentrations of N-type and P-type impurity ions are implanted to form NMOS and PMOS in the high-voltage region HVR on the substrate 10 to form N-type and P-type drift regions (Drift: 14a, 14b). Next, heat treatment is performed on the substrate resultant so that the ions implanted in the N-type and P-type drift regions are diffused.

The active region is then masked with a photoresist (not shown) to form an isolation layer in the substrate 10, and then field stop ions for the NMOS transistor are implanted into the low voltage region LVR. Subsequently, the field oxide film 15a is formed after implanting field stop ions for the PMOS transistor into the high voltage region HVR. After that, field stop ions for the NMOS transistor are implanted into the high voltage region HVR to form the device isolation layer 15 in the low voltage region LVR and the high voltage region HVR.

Referring to FIG. 1B, after forming the high voltage gate oxide layer 16 in the low voltage region LVR and the high voltage region HVR on the substrate 10, an ion implantation process is performed to adjust threshold voltages of NMOS and PMOS transistors. do. Next, after the ion implantation process is performed to adjust the threshold voltages of the NMOS and PMOS transistors in the low voltage region LVR, the high voltage gate oxide layer 16 formed on the low voltage region LVR is removed, and then on the substrate 10. A low voltage gate oxide film 17 is formed in the low voltage region LVR.

Referring to FIG. 1C, high-voltage and low-voltage gates 18a and 18b formed of a laminated structure of a polysilicon film, a tungsten silicide film, and a hard mask film in the low voltage region LVR and the high voltage region HVR on the substrate 10 are illustrated. To form. Herein, the polysilicon film, the tungsten silicide film, and the hard mask film are formed to have thicknesses of 1500, 1200, and 1500 GPa, respectively.

Subsequently, an ion implantation process is performed on both sides of the low voltage gate 18b to form LDD regions 19a and 19b, and then spacers 20 are formed on both side walls of the low voltage and high voltage gates 18a and 18b. Form.

Then, an ion implantation process is performed on the substrates on both sides of the low voltage and high voltage gates 18a and 18b to form source / drain regions 21a and 21b, and then the source / drain regions 21a and 21b. Heat treatment is performed on the substrate resultant to activate the impurity ions implanted in the.

Referring to FIG. 1D, a buffer oxide layer 22 is formed on a substrate product including the low voltage and high voltage gates 18a and 18b to form a pixel. Subsequently, after the polysilicon layer is formed on the buffer oxide layer 22, the polysilicon layer is etched to form the first gate 23 for pixels. Here, the buffer oxide film 22 and the polysilicon film are each formed to a thickness of 2000 kPa.

Next, an oxide film 24 and a nitride film 25 are formed on the buffer oxide film 22 including the pixel first gate 23, and then a polysilicon film is formed on the nitride film 25. The polysilicon layer is etched to expose a predetermined portion of the pixel first gate 23 to form the pixel second gate 26. Here, the oxide film 24 and the nitride film 25 are formed to a thickness of 70 and 140 kHz.

Referring to FIG. 1E, after the first interlayer insulating layer 27 is formed on the substrate resultant, the first interlayer insulating layer 27 is etched to form a contact hole 28 to fill the contact hole. After forming the titanium nitride film and the tungsten film, an etch-back is performed to expose the first interlayer insulating film 27.

Next, after forming the second interlayer insulating film 29 on the substrate resultant, the surface of the second interlayer insulating film 29 is CMP to secure the flatness of the LCOS chip. Subsequently, the second interlayer insulating layer 29 is etched to form a first via hole 30, and a titanium / titanium nitride film and a tungsten film are formed to fill the first via hole, and then the second interlayer insulating layer 29 is exposed. Etch back if possible.

Referring to FIG. 1F, after the third interlayer dielectric layer 31 is formed on the substrate, the third interlayer dielectric layer 31 has a surface thickness of 1 μm so as to secure flatness of the LCOS chip. CMP. In this case, the resonance of the light may be prevented by CMPing the surface of the third interlayer insulating layer 31.

Subsequently, the third interlayer insulating layer 31 is etched to form a second via hole 32, and a titanium / titanium nitride film and a tungsten film are formed to fill the second via hole, and then the third interlayer insulating layer 31 is exposed. Etch back if possible.

As illustrated in FIG. 1G, an aluminum film 33 is deposited on the substrate resultant to form a mirror metal, and the aluminum film 33 is etched to form a trench 34. Next, after forming the TEOS film 35 on the trench 34 surface, the field oxide film 36 is formed to fill the trench, and the TEOS film 35 is exposed to expose the aluminum film 33. The back wiring is performed to form the metal wiring 37.

The reason for filling the trench with the field oxide film is to secure reflectance characteristics of the LCOS element. The field oxide film is not an etch back material, but the aluminum film is exposed as it is due to the LCOS process characteristics. Because it is advantageous.

Subsequently, a protective film 38 is formed on the substrate resultant. In this case, the protective film 38 is formed of a silicon nitride film and is formed in a range that does not affect the reflectance.

Thereafter, known subsequent steps are performed to complete the LCOS device.

As described above, in order to secure the characteristics of the LCOS device, a high concentration of impurity ions are implanted into the high voltage region (HVR) on the semiconductor substrate to form a drift region, and the field stop ions for the NMOS of the high voltage region (HVR) are formed after the device isolation layer is formed. The injection can improve the leakage current of the LCOS pixel.

In addition, the present invention can secure a chip flatness of 5% or less by adding an interlayer insulating film process to a 0.6 μm process, and obtain a reflectance of 80% or more by depositing a mirror metal film.

In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person of ordinary skill in the art may make many modifications and variations without departing from the spirit of the present invention. I will understand.

As described above, the present invention forms a drift region by implanting a high concentration of impurity ions into a high voltage region on the semiconductor substrate to secure the characteristics of the LCOS device, and by implanting field stop ions for NMOS in the high voltage region after forming the device isolation film The leakage current of the pixel can be improved, a chip flatness of 5% or less can be secured by adding an interlayer insulating film process to a 0.6 μm process, and a reflectance of 80% or more can be secured by depositing a mirror metal film.

1A to 1G are cross-sectional views illustrating processes for manufacturing a LCOS device according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: substrate 13a, 13b: N well and P well

14a, 14b: Drift region 15: Device isolation film

16: high voltage gate oxide film 17 low voltage gate oxide film

18a, 18b: high and low voltage gates 19a, 19b: LDD region

21a, 21b: source / drain regions 23: first gate for pixels

26 second gate 33 for pixels 33 aluminum film

34: trench 35: TEOS film

36: field oxide film 37: metal wiring

38: protective film

Claims (3)

Providing a semiconductor substrate comprising a high voltage region and a low voltage region; Forming N well and P well regions in the high voltage region and the low voltage region on the substrate; Implanting a high concentration of impurity ions into a high voltage region on the substrate to form a drift region; Forming a high voltage gate oxide film in a low voltage region and a high voltage region on the substrate; Implanting ions to adjust the threshold voltages of the low voltage region and high voltage region transistors on the substrate; Removing the high voltage gate oxide film formed in the low voltage region on the substrate and forming a low voltage gate oxide film in the low voltage region; Forming low and high voltage gates in a low voltage region and a high voltage region on the substrate; Forming an LDD region by performing an ion implantation process on both substrates of the low voltage gate; Forming a source / drain region by performing an ion implantation process on both of the low voltage and high voltage gate substrates; Forming a buffer oxide film on a substrate product including the low voltage and high voltage gates; Forming a first gate for pixels formed of a polysilicon layer on the buffer oxide layer on the device isolation layer; Forming an oxide film and a nitride film on the buffer oxide film including the pixel first gate; Forming a second gate for pixels made of a polysilicon film on the nitride film so that a predetermined portion of the first gate for pixels is exposed; CMPing the interlayer dielectric surface after forming the interlayer dielectric on the substrate resultant; Etching the interlayer insulating layer to form a contact hole; Depositing a titanium / titanium nitride film and a tungsten film on the contact hole surface and etching back the tungsten film to expose the interlayer insulating film; Forming a trench by etching an aluminum film after depositing an aluminum film on the substrate resultant; Forming a field oxide film to fill the trench after forming a TEOS film on the trench surface; And And forming a metal wiring by etching back to the TEOS film so that the aluminum film is exposed. 2. The method of claim 1, wherein the step of forming a drift region and forming a high voltage gate oxide film is performed. Implanting a high concentration of impurity ions into a high voltage region on the substrate to form a drift region; Implanting field stop ions for an NMOS transistor in the low voltage region and a PMOS transistor in a high voltage region; Forming a device isolation film by forming a field oxide film on a region other than the active region of the substrate; And And implanting field stop ions for an NMOS transistor in the high voltage region. The method of claim 1, wherein the CMP of the surface of the interlayer insulating film is performed so that the interlayer insulating film has a thickness of 1 μm.