KR20050104826A - Method forming landing plug poly of semiconductor device - Google Patents
Method forming landing plug poly of semiconductor device Download PDFInfo
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- KR20050104826A KR20050104826A KR1020040030242A KR20040030242A KR20050104826A KR 20050104826 A KR20050104826 A KR 20050104826A KR 1020040030242 A KR1020040030242 A KR 1020040030242A KR 20040030242 A KR20040030242 A KR 20040030242A KR 20050104826 A KR20050104826 A KR 20050104826A
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- 238000000034 method Methods 0.000 title claims abstract description 72
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000010438 heat treatment Methods 0.000 claims abstract description 13
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 150000004767 nitrides Chemical class 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 8
- 238000001816 cooling Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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Abstract
본 발명의 반도체 소자의 랜딩플러그 폴리 형성방법을 개시한다. 개시된 본 발명은 게이트가 형성된 실리콘 기판을 제공하는 단계; 상기 게이트 양측벽에 질화막 스페이서를 형성하는 단계; 상기 게이트를 포함한 기판 결과물 상에 층간절연막을 형성하는 단계; 상기 층간절연막을 식각한 후에 랜딩플러그 폴리를 형성하기 위한 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘막 상에 이온주입을 실시하는 단계; 상기 폴리실리콘막을 CMP하는 단계; 및 상기 기판 결과물에 대하여 열처리 공정을 진행하는 단계를 포함하는 것을 특징으로 한다. 본 발명에 따르면, 랜딩플러그 폴리 형성시 CMP 공정을 진행하기 전에 후속의 이온주입 공정을 진행함으로써 CMP 공정을 진행하기 전에 실시하는 에치백 또는 추가의 CMP 공정을 생략할 수 있으므로, 공정을 단순화 시킬 수 있다.Disclosed is a method for forming a landing plug poly of a semiconductor device of the present invention. The disclosed subject matter provides a method comprising: providing a gated silicon substrate; Forming a nitride film spacer on both sidewalls of the gate; Forming an interlayer insulating film on a substrate resultant including the gate; Forming a polysilicon film for forming a landing plug poly after etching the interlayer insulating film; Performing ion implantation on the polysilicon film; CMPing the polysilicon film; And performing a heat treatment process on the substrate resultant. According to the present invention, since the subsequent ion implantation process is performed before the CMP process in forming the landing plug poly, an etch back or an additional CMP process performed before the CMP process can be omitted, thereby simplifying the process. have.
Description
본 발명은 반도체 소자의 랜딩플러그 폴리 형성방법에 관한 것으로, 보다 상세하게는, 랜딩플러그 폴리 형성시 CMP 공정을 진행하기 전에 후속의 이온주입 공정을 진행함으로써 공정을 단순화 시킬 수 있는 반도체 소자의 랜딩플러그 폴리 형성방법에 관한 것이다.The present invention relates to a method of forming a landing plug poly of a semiconductor device, and more particularly, to a landing plug of a semiconductor device which can simplify the process by performing a subsequent ion implantation process before proceeding with the CMP process when forming the landing plug poly. It relates to a poly forming method.
최근, 반도체 제조 기술의 진보와 더불어 반도체 소자의 고집적화가 급속하게 진행되고 있는 바, 기판 상에 형성되는 패턴에 대한 미세화 및 고정밀화의 필요성이 점점 높아지고 있다. 이에 수반해서, 반도체 소자는 다층의 배선 구조를 가지게 되며, 이러한 다층 배선간을 연결하기 위해 많은 방법이 제시되고 있다.In recent years, with the progress of semiconductor manufacturing technology, high integration of semiconductor devices has been rapidly progressed, and the necessity of miniaturization and high precision of patterns formed on substrates is increasing. In connection with this, a semiconductor device has a multi-layered wiring structure, and many methods have been proposed for connecting such multi-layered wiring.
도 1a 내지 도 1d는 종래 기술에 의한 랜딩플러그 폴리 형성방법을 설명하기 위한 공정별 단면도이다.1A to 1D are cross-sectional views illustrating processes for forming a landing plug poly according to the prior art.
도 1a에 도시된 바와 같이, 실리콘 기판(1) 상에 게이트(2)를 형성한 후에 게이트 양측벽에 질화막 스페이서(3)를 형성하고, 게이트를 포함한 기판 결과물 상에 층간절연막(4)을 형성한다. 그 다음, 상기 층간절연막(4)을 식각한 후에 소오스/드레인 영역을 각각 스토리지 노드 및 비트 라인과 연결하기 위해 층간절연막(4) 상에 폴리실리콘막(5)을 형성한다.As shown in FIG. 1A, after forming the gate 2 on the silicon substrate 1, the nitride film spacers 3 are formed on both side walls of the gate, and the interlayer insulating film 4 is formed on the substrate resultant including the gate. do. After the etching of the interlayer insulating film 4, a polysilicon film 5 is formed on the interlayer insulating film 4 to connect the source / drain regions with the storage node and the bit line, respectively.
도 1b에 도시된 바와 같이, 상기 폴리실리콘막(5)을 랜딩플러그 폴리로 구현하기 위해 아이솔레이션(Isolation) 공정이 필요하며, 이를 위해 1차 CMP를 실시한다.그 다음, CMP 공정 진행시 폴리싱(Polishing) 단차를 줄여 균일도(Uniformity)를 개선하기 위해 폴리실리콘막(5)을 에치백(Etch-Back)을 실시한다.As shown in FIG. 1B, an isolation process is required to implement the polysilicon film 5 as a landing plug poly, and a first CMP is performed for this purpose. Polishing) The polysilicon film 5 is etched back in order to reduce uniformity and improve uniformity.
도 1c에 도시된 바와 같이, 상기 CMP 실시 후 게이트 하드마스크막을 식각정지막으로 사용하여 2차 CMP를 실시한다.As shown in FIG. 1C, after the CMP, the second CMP is performed using the gate hard mask layer as an etch stop layer.
도 1d에 도시된 바와 같이, 상기 기판 결과물 상에 N형 이온주입을 실시한다.As shown in FIG. 1D, an N-type ion implantation is performed on the substrate resultant.
그러나, 상기와 같이 종래 비트라인 형성방법은 2차 CMP 공정을 진행하기 전에 1차 CMP 공정 및 CMP 공정 진행시 폴리싱 단차를 줄여 균일도를 개선하기 위한 에치백 공정이 추가되어 공정 증가에 따른 원가 상승의 문제점을 가지고 있다.However, in the conventional bit line forming method as described above, an etch back process is added to improve the uniformity by reducing the polishing step during the first CMP process and the CMP process before the second CMP process. I have a problem.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 랜딩플러그 폴리 형성시 CMP 공정을 진행하기 전에 후속의 이온주입 공정을 진행함으로써 공정을 단순화 시킬 수 있는 반도체 소자의 랜딩플러그 폴리 형성방법을 제공하는데 그 목적이 있다.Accordingly, the present invention devised to solve the above problems, a method of forming a landing plug poly of a semiconductor device that can simplify the process by proceeding the subsequent ion implantation process before proceeding to the CMP process when forming the landing plug poly. The purpose is to provide.
상기 목적을 달성하기 위한 본 발명은, 게이트가 형성된 실리콘 기판을 제공하는 단계; 상기 게이트 양측벽에 질화막 스페이서를 형성하는 단계; 상기 게이트를 포함한 기판 결과물 상에 층간절연막을 형성하는 단계; 상기 층간절연막을 식각한 후에 랜딩플러그 폴리를 형성하기 위한 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘막 상에 이온주입을 실시하는 단계; 상기 폴리실리콘막을 CMP하는 단계; 및 상기 기판 결과물에 대하여 열처리 공정을 진행하는 단계를 포함하는 것을 특징으로 한다.The present invention for achieving the above object, providing a silicon substrate with a gate formed; Forming a nitride film spacer on both sidewalls of the gate; Forming an interlayer insulating film on a substrate resultant including the gate; Forming a polysilicon film for forming a landing plug poly after etching the interlayer insulating film; Performing ion implantation on the polysilicon film; CMPing the polysilicon film; And performing a heat treatment process on the substrate resultant.
여기에서, 상기 폴리실리콘막 상에 이온주입을 실시하는 단계는 마스크 추가 공정없이 블랭킷(Blanket)으로 전면 이온주입 공정을 실시하는 것을 특징으로 한다.Here, the ion implantation on the polysilicon film is characterized in that the entire surface ion implantation process is performed by a blanket without a mask addition process.
상기 폴리실리콘막 상에 이온주입을 실시하는 단계는 P 및 As 이온의 에너지를 100∼200KeV로, 도우즈를 1E15∼1E16으로, 이온주입 기울기(Tilt)를 0∼45°, 꼬임(Twist)을 0∼180°, 회전(Rotation)을 0∼4회로 실시하는 것을 특징으로 한다.The ion implantation on the polysilicon film is performed by applying energy of P and As ions to 100 to 200 KeV, dose to 1E15 to 1E16, ion implantation tilt (Tilt) of 0 to 45 °, and twist (Twist). It is characterized by performing 0 to 180 degrees and rotation for 0 to 4 times.
상기 열처리 공정은 퍼니스 어닐링 또는 고속 열처리 공정인 것을 특징으로 한다.The heat treatment process is characterized in that the furnace annealing or high speed heat treatment process.
상기 퍼니스 어닐링 공정은 400∼1000℃의 온도에서 NH3, Ar, N2 및 N2O 가스를 사용하여 승온 및 냉각 속도를 5∼25℃/min로 하여 5분 내지 6시간 동안 수행하는 것을 특징으로 한다.The furnace annealing process is characterized in that for 5 minutes to 6 hours at a temperature of 400 ~ 1000 ℃ using NH3, Ar, N2 and N2O gas temperature and cooling rate 5-25 ° C / min.
상기 고속 열처리 공정은 500∼1100℃의 온도에서 NH3, Ar, N2 및 N2O 가스를 사용하여 승온 및 냉각 속도를 15∼100℃/sec로 하여 5초 내지 1000초 동안 수행하는 것을 특징으로 한다.The high-speed heat treatment process is carried out for 5 seconds to 1000 seconds at a temperature of 500 to 1100 ℃ using NH3, Ar, N2 and N2O gas temperature and cooling rate of 15 to 100 ℃ / sec.
(실시예)(Example)
이하, 본 발명의 바람직한 실시예에 대해 첨부된 도면을 참조하여 보다 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 랜딩플러그 폴리 형성방법을 설명하기 위한 각 공정별 단면도이다. 2A through 2C are cross-sectional views of respective processes for describing a method of forming a landing plug poly of a semiconductor device according to an embodiment of the present invention.
도 2a에 도시된 바와 같이, 실리콘 기판(21) 상에 게이트(22)를 형성한 후에 게이트 양측벽에 질화막 스페이서(23)를 형성하고, 게이트를 포함한 기판 결과물 상에 층간절연막(24)을 형성한다. 그 다음, 상기 층간절연막(24)을 식각한 후에 소오스/드레인 영역을 각각 스토리지 노드 및 비트 라인과 연결하기 위해 층간절연막(24) 상에 폴리실리콘막(25)을 형성한다.As shown in FIG. 2A, after forming the gate 22 on the silicon substrate 21, the nitride film spacer 23 is formed on both sidewalls of the gate, and the interlayer insulating film 24 is formed on the substrate product including the gate. do. After etching the interlayer insulating layer 24, a polysilicon layer 25 is formed on the interlayer insulating layer 24 to connect the source / drain regions with the storage node and the bit line, respectively.
도 2b에 도시된 바와 같이, 상기 폴리실리콘막(25) 상에 N형 이온주입을 실시하며, P 및 As 이온을 주입할 수 있다. 이때, 이온주입 공정은 마스크 추가 공정없이 블랭킷(Blanket)으로 전면 이온주입 공정을 실시한다. 이때, P 및 As 이온주입 공정은 에너지를 100∼200KeV로, 도우즈를 1E15∼1E16으로, 이온주입 기울기(Tilt)를 0∼45°, 꼬임(Twist)을 0∼180°, 회전(Rotation)을 0∼4회로 실시한다.As shown in FIG. 2B, N-type ion implantation may be performed on the polysilicon layer 25 and P and As ions may be implanted. In this case, the ion implantation process is a front surface ion implantation process with a blanket (blanket) without the mask addition process. At this time, the P and As ion implantation process uses energy of 100 to 200 KeV, dose of 1E15 to 1E16, ion implantation tilt of 0 to 45 °, twist of 0 to 180 °, and rotation. Is carried out 0 to 4 times.
도 2c에 도시된 바와 같이, 상기 N형 이온이 주입된 폴리실리콘막(25)을 CMP한 다음, 상기 기판 결과물에 대하여 열처리 공정을 진행하여 랜딩플러그 폴리(26)를 형성한다. 여기에서, 열처리 공정은 퍼니스 어닐링(Furnace)을 진행하며, 열처리 공정 조건은 400∼1000℃의 온도에서 NH3, Ar, N2 및 N2O 가스를 사용하여 승온 및 냉각 속도를 5∼25℃/min로 하여 5분 내지 6시간 동안 진행한다.As shown in FIG. 2C, the polysilicon film 25 into which the N-type ion is implanted is CMP, and then a landing plug poly 26 is formed by performing a heat treatment process on the substrate resultant. Here, the heat treatment process is a furnace annealing (Furnace), the heat treatment process conditions using a NH 3, Ar, N 2 and N 2 O gas at a temperature of 400 ~ 1000 ℃ to raise the temperature and cooling rate to 5 ~ 25 ℃ / min Run for 5 minutes to 6 hours.
또한, 본 발명에서는 열처리 공정을 고속 열처리 공정(Rapid Thermal Process)을 사용할 수 있다. 이때, 고속 열처리 공정 조건은 500∼1100℃의 온도에서 NH3, Ar, N2 및 N2O 가스를 사용하여 승온 및 냉각 속도를 15∼100℃/sec로 하여 5초 내지 1000초 동안 진행한다.In the present invention, a rapid thermal process may be used as the thermal treatment process. At this time, the high-speed heat treatment process conditions for 5 seconds to 1000 seconds at a temperature of 500 ~ 1100 ℃ using NH3, Ar, N2 and N2O gas temperature and cooling rate 15 to 100 ℃ / sec.
따라서, 본 발명은 랜딩플러그 폴리 형성시 에치백 및 1차 CMP 공정을 진행한 후에 2차 CMP 공정을 진행한 다음, 이온주입 공정을 실시하는 종래 공정과 달리, 랜딩플러그 폴리 형성시 CMP 공정을 진행하기 전에 후속의 이온주입 공정을 진행함으로써 CMP 공정을 진행하기 전에 실시하는 에치백 또는 추가의 CMP 공정을 생략할 수 있으므로, 공정을 단순화 시킬 수 있다.Therefore, the present invention proceeds with the secondary CMP process after the etch back and the first CMP process when forming the landing plug poly, and then proceeds with the CMP process when forming the landing plug poly, unlike the conventional process of performing the ion implantation process. By proceeding with the subsequent ion implantation step before the etch back or additional CMP process before the CMP process can be omitted, the process can be simplified.
이상, 본 발명을 몇 가지 예를 들어 설명하였으나, 본 발명은 이에 한정되는 것은 아니며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 본 발명의 사상에서 벗어나지 않으면서 많은 수정과 변형을 가질 수 있음을 이해할 것이다.In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto. Those skilled in the art may have many modifications and variations without departing from the spirit of the present invention. I will understand.
이상에서와 같이, 본 발명은 랜딩플러그 폴리 형성시 CMP 공정을 진행하기 전에 후속의 이온주입 공정을 진행함으로써 CMP 공정을 진행하기 전에 실시하는 에치백 또는 추가의 CMP 공정을 생략할 수 있으므로, 공정을 단순화 시킬 수 있다.As described above, the present invention can omit the etch back or the additional CMP process before the CMP process by proceeding the ion implantation process before the CMP process when forming the landing plug poly, so that the process Can be simplified.
또한, 본 발명은 공정 단순화로 인해 반도체 소자 제조시 원가 절감 효과를 얻을 수 있다.In addition, the present invention can obtain a cost reduction effect in the manufacture of semiconductor devices due to the simplified process.
도 1a 내지 도 1d는 종래 기술에 의한 반도체 소자의 랜딩플러그 폴리 형성방법을 설명하기 위한 공정 단면도.1A to 1D are cross-sectional views illustrating a method for forming a landing plug poly of a semiconductor device according to the prior art.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 랜딩플러그 폴리 형성방법을 설명하기 위한 공정 단면도.2A to 2C are cross-sectional views illustrating a method for forming a landing plug poly of a semiconductor device according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
21 : 실리콘 기판 22 : 게이트21 silicon substrate 22 gate
23 : 질화막 스페이서 24 : 층간절연막23 nitride film spacer 24 interlayer insulating film
25 : 폴리실리콘막 26 : 랜딩 플러그 폴리25 polysilicon film 26 landing plug poly
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| CN111430226A (en) * | 2020-04-10 | 2020-07-17 | 中国科学院微电子研究所 | Deposition method of polycrystalline silicon and application thereof |
| CN111430226B (en) * | 2020-04-10 | 2023-04-07 | 中国科学院微电子研究所 | Deposition method of polycrystalline silicon and application thereof |
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