KR20050101682A - Voltage driver circuit for semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage driver circuit of a semiconductor device, wherein a driving controller is provided in a voltage driver circuit to control an output voltage that is excessively driven. The voltage driver circuit of the semiconductor device can be discharged, thereby reducing the current consumption, improving the efficiency of the voltage driver, and adjusting the overdriving range to sink by adjusting the resistance ratio in the driving controller. to provide.

Description

Voltage driver circuit for semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage driver circuit of a semiconductor device, and more particularly to a voltage driver circuit capable of preventing excessive current of a power supply driver used in a DRAM memory device.

Currently, the driver for the power supply used in most DRAM memory devices greatly increases the driving capability of the final transistor of the driver, causing a problem that the current is excessively supplied than the current required in the actual product.

1 is a circuit diagram of a conventional voltage driver.

Referring to FIG. 1, a differential amplifier 10 generates a differential voltage Vdf according to a reference voltage Vrc and an output voltage Vout, and an output voltage Vout according to the differential voltage Vdf. It includes an output unit 20 to.

The differential amplifier 10 is connected between the power supply voltage and the output of the differential voltage Vdf and is driven between the first PMOS transistor P1 and the power supply voltage and the first node Q1 that are driven according to the first node Q1. A first NMOS connected between the second PMOS transistor P2 connected to and driven according to the first node Q1 and the differential voltage Vdf output terminal and the second node Q2 to be driven according to the reference voltage Vrc. The second NMOS transistor N2, the second node Q2, and the ground power source connected between the transistor N1, the first node Q1, and the second node Q2 and driven according to the output voltage Vout. And a third NMOS transistor N3 connected between and driven according to the power supply voltage.

The output unit 20 includes a third PMOS transistor P3 connected between the power supply voltage and the output voltage Vout output terminal and driven according to the differential voltage Vdf.

The operation of the conventional voltage driver circuit having the above-described configuration is as follows.

The differential voltage Vdf is generated by receiving the comparison voltage and the output voltages Vrc and Vout, and the third PMOS transistor P3 in the output unit 20 is generated according to the differential voltage Vdf. To generate an output voltage. At this time, the driving capability of the third PMOS transistor P3 is greatly increased so that the current is excessively supplied than the amount of current actually used. This excessive current causes the current loss of the device to become very large, resulting in a problem of low efficiency of the device.

Therefore, in order to solve the above problem, the present invention provides a voltage driver circuit of a semiconductor device capable of reducing current loss of a device by causing a current of an output voltage to flow to a ground power supply when a force voltage is overdrived over a specific voltage. To provide.

A first input for transmitting a first comparison voltage having a lower voltage level than the control voltage according to the control voltage and the reference voltage according to the present invention, and a second comparison of the voltage level lower than the control voltage according to the control voltage and the output voltage A second input unit for transmitting a voltage, a differential amplifier for generating a differential voltage according to the control voltage and the first and second comparison voltages, and an output for generating the output voltage according to the differential voltage and the overdriving control signal And a driving controller configured to generate the overdriving control signal for preventing overdriving of the output voltage according to the first and second comparison voltages or the reference voltage and the output voltage. to provide.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

2 is a circuit diagram of a voltage driver according to the present invention.

Referring to FIG. 2, the control voltage generator 100 generating the control voltage Vc and the first input unit transmitting the first comparison voltage Vrci according to the control voltage Vc and the reference voltage Vrc ( 110, a second input unit 120 for transmitting the second comparison voltage Vouti according to the control voltage Vc and the output voltage Vout, and the control voltage Vc and the first and second comparison voltages Vrci. And the differential amplifier 130 generating the differential voltage Vdf according to Vouti, and the overdriving control signal according to the first and second comparison voltages Vrci and Vouti or the reference voltage and the output voltage Vrc and Vout. And a driving controller 140 for generating a vodc, and an output unit 150 for generating an output voltage Vout according to the differential voltage Vdf and the overdriving control signal Vodc.

The control voltage generation unit 100 is connected in series between the power supply voltage Vcc and the control voltage Vc output terminal and is driven in accordance with the ground power supply Vss and the power supply voltage, respectively, and the tenth PMOS transistor P10 and the tenth NMOS. The eleventh NMOS transistor N11 and the twelfth NMOS transistor N12, which are connected in parallel between the transistor N10, the output terminal of the control voltage Vc, and the ground power supply, respectively, are driven in accordance with the ground voltage and the control voltage Vc. Include. The control voltage generator 100 may operate in accordance with an external enable signal to generate various types of control voltages.

The first input unit 110 is connected between the power supply voltage and the first comparison voltage Vrci output terminal and is operated according to the reference voltage Vrc, the thirteenth NMOS transistor N13 and the first comparison voltage Vrci output terminal and ground. The fourteenth NMOS transistor N14 is connected between power supplies and operates according to the control voltage Vc.

The second input unit 120 is connected between a power supply voltage and an output terminal of the second comparison voltage Vouti and is connected to a fifteenth NMOS transistor N15 that operates according to the output voltage Vout, a second comparison voltage Vouti output terminal, and a ground. The sixteenth NMOS transistor N16 is connected between power supplies and operates according to the control voltage Vc.

The differential amplifier 130 is connected between the power supply voltage and the output of the differential voltage Vdf and is driven between the eleventh PMOS transistor P11 driving along with the tenth node Q10 and between the power supply voltage and the tenth node Q10. A twelfth PMOS transistor P12 connected to and driven according to the tenth node Q10 and a differential voltage Vdf output terminal and an eleventh node Q11 to be driven according to the first comparison voltage Vrci. A seventeenth NMOS transistor N17 and an eighteenth NMOS transistor N18 and an eleventh node Q11 connected between the tenth node Q10 and the eleventh node Q11 and driven according to the second comparison voltage Vouti. ) And a nineteenth NMOS transistor N19 connected between the ground power source and the ground power source and driven according to the control voltage Vc.

The driving controller 140 drives the thirteenth PMOS transistor according to the first variable resistor R1 and the reference voltage Vrc or the first comparison voltage Vrci connected in series between the power supply voltage and the twentieth node Q20. P14 and the fourteenth PMOS transistor P14 driven according to the second variable resistor R2 and the output voltage Vout or the second comparison voltage Vouti connected in series between the power supply voltage and the twenty-first node Q21. And a twentieth NMOS transistor N20 connected between the twentieth node Q20 and the ground power source and driven according to the twenty-first node Q21, and the twenty-first node Q21 connected to the ground power source. And a control signal output unit 142 for outputting an overdriving control signal Vodc according to the twentieth node Q20. The control signal output unit 142 inverts the signal of the first inverter I1 and the first inverter I1 which inverts the signal of the twentieth node Q20 and outputs the overdriving control signal Vodc. A second inverter I2 is included. The driving controller 140 may further include a separate NMOS transistor (not shown) connected between the ground power source and the twentieth and twenty-first NMOS transistors N20 and N21 and driven according to the control voltage Vc. The driving controller 140 preferably uses a new current miller type amplifier that receives the first and second comparison voltages Vrci and Vouti or the reference voltage and the output voltages Vrc and Vout. In addition, various overdriven levels may be detected using ratios of the first and second variable resistors R1 and R2. That is, an overdriven output voltage level of 0.1 to 0.3V can be detected by varying the ratio of the first and second variable resistors R1 and R2. It is preferable to make the resistance value of the first variable resistor R1 larger than the resistance value of the second variable resistor R2.

The output unit 150 is connected between the power supply voltage and the output voltage Vout output terminal and is connected between the fifteenth PMOS transistor P15 for driving according to the differential voltage Vdf, and between the output voltage Vout output terminal and the ground power source. And a twenty-second NMOS transistor N22 driving according to the overdriving control signal Vodc. As the fifteenth PMOS transistor P15, it is preferable to use a device having a driving capability capable of applying a sufficient current to a load to which the output voltage Vout is applied. In addition, in order to prevent the 15th PMOS transistor P15 and the 22nd NMOS transistor P22 from being turned on at the same time, it is preferable to operate the 22nd NMOS transistor P22 at a full CMOS level. It is desirable to allow operation at full logic high.

Hereinafter, the operation of the voltage driver circuit of the present invention having the above-described configuration will be described.

When the device starts to operate, the control voltage generator 100 uses the tenth PMOS transistor P10, the tenth NMOS transistor N10, and the twelfth NMOS transistor N12 to generate a control voltage Vc of a high logic state. Create As a result, the 14th, 16th, and 19th NMOS transistors 14, 16, and 19 of the first input unit 110, the second input unit 120, and the differential amplifier 130 are turned on so that the first input unit 110, The second input unit 120 and the differential amplifier 130 operate.

A reference voltage Vrc of a predetermined level is applied to the first input terminal 110 through a reference voltage generator (not shown). The first input terminal 110 applies the first comparison voltage Vrci, which changes the voltage level of the reference voltage Vrc, to the differential amplifier 130. The first comparison voltage Vrci preferably has a voltage level lowered by the threshold voltage of the thirteenth NMOS transistor N13 compared to the reference voltage Vrc.

The differential amplifier 130 receiving the first comparison voltage Vrci outputs the differential voltage Vdf of the ground power level. That is, since there is no output of the voltage drive circuit at the moment of operation of the device, the second comparison voltage Vouti applied to the differential amplifier 130 becomes logic low.

The differential voltage Vdf drives the fifteenth PMOS transistor P15 of the output unit 150 to generate an output voltage Vout. Thereafter, since the level of the output voltage Vout gradually increases, the output of the second input unit 120 gradually increases. Thereafter, when the output voltage Vout reaches the reference voltage Vrc level, a constant swing is performed. That is, the 15th PMOS transistor P15 of the output unit 150 is turned on or turned off by the difference in the voltage applied to the 17th and 18th NMOS transistors N17 and N18 of the differential amplifier 130. The output voltage Vout of the target level is generated.

The driving controller 140 detects the level of the output voltage Vout and operates when the output voltage Vout is greater than or equal to a specific voltage to apply an overdriving control signal Vodc of logic high to the 22nd NMOS transistor N22. Adjust the level of the output voltage (Vout).

Hereinafter, the operation of the driving control unit 140 in the voltage driving circuit of the present invention will be described in detail with reference to the level of the output voltage.

The case where the output voltage (Vout) is overdriven is as follows. That is, the case where the output voltage Vout is overdriven by about 0.1 to 0.3V excessively than the peak voltage of the normal case will be described.

The second comparison voltage Vouti increases due to the increase in the output voltage Vout. As a result, the Vgs of the fourteenth PMOS transistor P14 of the driving controller 140 decreases from the Vgs of the thirteenth PMOS transistor P13 so that the current flowing through the twenty-first node Q21 decreases slightly than that of the twentieth node Q20. do. The time point of decrease depends on the ratio of the first and second variable resistors R1 and R2 described above. As a result, the twenty-first node Q21 gradually approaches a logic low, thereby reducing the Vgs of the twentieth and twenty-first NMOS transistors N20 and N21. As a result, the twentieth node Q20 gradually rises to logic high. Accordingly, the over driving control signal Vodc of logic high is applied to the twenty-second NMOS transistor N22 by the first and second inverters I1 and I2. In response to the overdriving control signal Vodc, the twenty-second NMOS transistor N22 is turned on to discharge the excessively increased output voltage Vout to ground.

The case where the output voltage Vout maintains the same level as the reference voltage Vrc which is the input voltage is as follows.

When the output voltage Vout and the reference voltage Vrc are at the same level, the first and second comparison voltages Vrci and Vouti are also at the same voltage level. Therefore, two signals applied to the input terminal of the driving controller 140 are applied with the same level of voltage.

However, as described above, since the resistance value of the first variable resistor R1 is greater than the resistance value of the second variable resistor R2, the same level of voltage is applied, but the Vgs of the fourteenth PMOS transistor P14 is set to 13th. It becomes larger than Vgs of the PMOS transistor P13. As a result, the twenty-first node Q21 rises to logic high to increase the Vgs of the twentieth and twenty-first NMOS transistors N20 and N21, and the twentieth node Q20 gradually becomes logic low. Accordingly, the 22nd NMOS transistor N22 is turned off by applying an overdriving control signal Vodc of a logic low by the first and second inverters I1 and I2. This prevents the output voltage Vout from being discharged to ground.

The output voltage Vout is lower than the reference voltage Vrc as an input voltage.

When the output voltage Vout is at a lower level than the reference voltage Vrc, the second comparison voltage Vouti is lower than the level of the first comparison voltage Vrci. Therefore, the Vgs of the fourteenth PMOS transistor P14 of the driving controller 140 is increased than the Vgs of the thirteenth PMOS transistor P13. As a result, the twenty-first node Q21 rises to logic high to increase the Vgs of the twentieth and twenty-first NMOS transistors N20 and N21, and the twentieth node Q20 gradually becomes logic low. Accordingly, the 22nd NMOS transistor N22 is turned off by applying an overdriving control signal Vodc of a logic low by the first and second inverters I1 and I2. This prevents the output voltage Vout from being discharged to ground.

Meanwhile, referring to the differential amplifier 130, the Vgs of the seventeenth NMOS transistor N17 is greater than the Vgs of the eighteenth NMOS transistor N18, and the differential voltage Vdf level gradually decreases to logic high. Therefore, the fifteenth PMOS transistor P15 is driven by the differential voltage Vdf of logic high to increase the voltage level of the lowered output voltage Vout.

3 is an operation simulation graph of the voltage driver circuit according to the present invention.

3 is a simulation graph when assuming that the Vcc voltage is 3.0V, the reference voltage is 1.6V, and the output voltage is rising / polling with an amplitude of ± 0.4V based on 1.6V. In the A section, the output voltage Vot is overdried and the overdriving control signal Vodc becomes logic high. As a result, the 22nd NMOS transistor N22 is turned on to discharge the output voltage Vout. At this time, the differential voltage Vdf is maintained at 3.0V to turn off the fifteenth PMOS transistor P15. In the period B, the output voltage Vout is lower than or close to the reference voltage, and the overdriving control signal Vodc becomes logic low to turn off the twenty-second NMOS transistor N22. In addition, according to circumstances, the fifteenth PMOS transistor P15 is driven by the differential voltage Vdf to increase the output voltage Vout.

As described above, according to the present invention, a driving control unit may be provided in the voltage driver circuit to control an excessive driving of the output voltage.

In addition, the output voltage can be discharged only when the output voltage is overdrifted above a specific voltage, thereby reducing current consumption and improving the efficiency of the voltage driver.

In addition, an overdriving range to be sinked may be adjusted by adjusting a resistance ratio in the driving controller.

1 is a circuit diagram of a conventional voltage driver.

2 is a circuit diagram of a voltage driver according to the present invention.

3 is an operation simulation graph of the voltage driver circuit according to the present invention.

<Description of the symbols for the main parts of the drawings>

10, 130: differential amplifier 20: output unit

100: control voltage generation unit 110, 120: input unit

140: driving control unit 142: control signal output unit

150: output unit

Claims (7)

A first input unit configured to transmit a first comparison voltage having a voltage level lower than the control voltage according to a control voltage and a reference voltage; A second input unit configured to transmit a second comparison voltage having a voltage level lower than the control voltage according to the control voltage and the output voltage; A differential amplifier generating a differential voltage according to the control voltage and the first and second comparison voltages; An output unit generating the output voltage according to the differential voltage and the overdriving control signal; And And a driving controller configured to generate the overdriving control signal for preventing overdriving of the output voltage according to the first and second comparison voltages or the reference voltage and the output voltage. The method of claim 1, wherein the driving control unit, A first PMOS transistor driven according to the first variable resistor and the reference voltage or the first comparison voltage connected in series between a power supply voltage and a first node; A second PMOS transistor driven according to the second variable resistor and the output voltage or the second comparison voltage connected in series between a power supply voltage and a second node; A first NMOS transistor connected between the first node and a ground power source and driven according to the second node; A second NMOS transistor connected to the second node and a ground power source and driven according to the second node; And And an output unit configured to output the overdriving control signal according to a first node. The method of claim 2, And over-driving the output voltage of 0.1 to 0.3V by increasing the resistance value of the first variable resistor greater than the resistance value of the second variable resistor. The method of claim 1, wherein the output unit, A PMOS transistor connected between a power supply voltage and the output voltage output terminal and driven according to the differential voltage; And And an NMOS transistor connected between the output voltage output terminal and a ground power supply and driven according to the overdriving control signal. The method of claim 1, wherein the first input unit, A first NMOS transistor connected between a power supply voltage and the first comparison voltage output terminal and operated according to the reference voltage; And And a second NMOS transistor connected between the first comparison voltage output terminal and a ground power source to operate according to the control voltage. The method of claim 1, wherein the second input unit, A first NMOS transistor connected between a power supply voltage and the second comparison voltage output terminal and operating according to the output voltage; And And a second NMOS transistor connected between the second comparison voltage output terminal and a ground power source to operate according to the control voltage. The method of claim 1, A PMOS transistor and a first NMOS transistor connected in series between a power supply voltage and the control voltage output terminal and respectively driven according to a ground power supply and a power supply voltage, and connected in parallel between the control voltage output terminal and a ground power supply, respectively, the ground power supply and the And a control voltage generation unit including a second NMOS transistor and a third NMOS transistor driven according to the control voltage.