KR20050101604A - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention discloses a method of manufacturing a semiconductor device for preventing profile damage of a cell edge pattern through double exposure using a dummy open mask. The disclosed method includes forming a polysilicon film on a semiconductor substrate; Coating a photosensitive film on the polysilicon film; Firstly exposing the photosensitive film using an exposure mask having a mask pattern including a cell region and a dummy cell region outside the cell region; Second exposure of the first exposed photoresist using a dummy open mask that opens only the dummy cell region; Developing the second exposed photoresist to form a photoresist pattern only in the cell region; And etching the polysilicon layer using the photoresist pattern as an etch barrier to form a cell pattern only in the cell region.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to manufacturing a semiconductor device capable of preventing damage to a profile of a cell edge pattern through double exposure using a dummy open mask. It is about a method.

In the semiconductor manufacturing process, various patterns having a predetermined shape including contact holes are formed through a photolithography process. The photolithography process includes a first process of forming a photoresist pattern by applying, exposing and developing a photoresist on an etching target layer, and using the photoresist pattern formed through the first process to form a pattern having a predetermined shape as an etching barrier. And a second process of etching the etching target layer.

However, as the integration of semiconductor devices increases, design rules are reduced, and thus, conventional photolithography processes cannot form cell patterns having good profiles for the entire cell region.

For example, when a 140 nm high resolution pattern is implemented by a conventional photolithography process, a profile defect occurs in a pattern disposed at a cell edge due to a different pattern density. In particular, the poor pattern is a cause of particles, causing a decrease in production yield.

1 is a photograph illustrating a pattern defect generated at the cell edge and a particle generation process accordingly.

1 (a) and (b) are photographs showing photoresist patterns of cell edges formed through exposure and development, and a capacitor lower electrode pattern obtained as a result of etching using the same. It can be seen that less than the size of, i.e., an electrode pattern of good profile was not obtained.

In addition, Figure 1 (c) is a photograph after performing a meta stable polysilicon (MPS) process for the lower electrode pattern of (b), it can be seen that the pattern defect occurs at the cell edge.

1 (d) is a photograph after deposition of polysilicon for the capacitor upper electrode with respect to the resultant of (c), and it can be seen that particles are generated at the edge of the cell due to a poor pattern.

Therefore, various techniques for implementing a pattern having a high resolution of 140 nm have been proposed. As one example, a technique of additionally forming a dummy pattern outside the cell may be mentioned. According to this technique, by forming a dummy pattern on the outside of the cell, it is possible to prevent profile damage of the actual pattern disposed at the cell edge.

In detail, the actual pattern disposed at the edge of the cell block causes profile damage due to the different pattern density. However, when the dummy pattern is formed together in the shape of the cell pattern on the outside of the cell, the damage of the pattern of the pattern due to the different pattern densities is received by the dummy pattern, so that the actual pattern disposed at the edge of the cell is responsible for the damage of the profile. You will not receive.

Therefore, the method of including a dummy pattern on the outside of the cell for stabilization of the pattern profile can be very useful for implementing a high resolution pattern.

However, the method of providing a dummy pattern on the outside of the cell is very useful in itself, but as the size of the chip becomes smaller, the formation of the dummy pattern is restricted, which makes it difficult to use.

In detail, the formation of the dummy pattern described above is very useful for preventing the profile damage of the actual pattern disposed at the edge of the cell, and the larger the number, the more the actual pattern of the good profile can be obtained. However, since the chip size must be reduced for high integration, a sufficient number of dummy patterns cannot be formed, or the formation of the dummy patterns becomes difficult.

On the other hand, in order to reduce the chip size, the formation of the dummy pattern may be reduced or omitted, but in this case, as described above, a pattern of a good profile cannot be obtained at the edge of the cell, thereby causing a greater problem. do.

Accordingly, the present invention has been made to solve the above problems, and provides a method of manufacturing a semiconductor device that can overcome the limitation of the formation of the dummy pattern by reducing the chip size while preventing the profile damage of the cell edge pattern. Has its purpose.

Method for manufacturing a semiconductor device of the present invention for achieving the above object, the step of forming a polysilicon film on a semiconductor substrate; Coating a photosensitive film on the polysilicon film; Firstly exposing the photosensitive film using an exposure mask having a mask pattern including a cell region and a dummy cell region outside the cell region; Second exposure of the first exposed photoresist using a dummy open mask that opens only the dummy cell region; Developing the second exposed photoresist to form a photoresist pattern only in the cell region; And etching the polysilicon layer using the photoresist pattern as an etch barrier to form a cell pattern only in the cell region.

Here, after forming the cell pattern, the method may further include performing an MPS process on the cell pattern.

According to the present invention, since the second exposure is performed with the dummy open mask exposing only the dummy cells after performing the first exposure with the exposure mask including the dummy cells, it is possible to prevent the profile of the cell edge pattern from being damaged.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 to 4 are views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, Figure 2 is a cell block of the conventional exposure mask for capacitor manufacturing, Figure 3 is a exposure mask for capacitor manufacturing of the present invention 4 shows a cell block and a cell block of the dummy open mask of the present invention.

Referring to FIGS. 2 and 3, the capacitor manufacturing exposure mask 20 of the present invention is different from the conventional capacitor manufacturing exposure mask 10 having only a mask pattern for the cell region 2. Of course, it further comprises a mask pattern for the outer dummy cell region (4).

Referring to FIG. 4, the dummy open mask 30 of the present invention has a structure in which the cell region 24 is shielded, but only the dummy cell region 22 is opened. Here, the light shielded cell region 24 may be formed by forming a non-transparent film such as chromium.

A method of manufacturing a semiconductor device using the exposure masks, that is, the capacitor manufacturing exposure mask 20 and the dummy open mask 30 of the present invention will be briefly described as follows.

First, a photosensitive film is coated on the polysilicon film while an etching target layer, for example, a polysilicon film for a capacitor lower electrode is formed on a semiconductor substrate. Then, in the state where the semiconductor substrate is loaded into a stepper which is an exposure apparatus, after performing the first exposure to the photosensitive film using the exposure mask 20 for manufacturing a capacitor of the present invention, without unloading the substrate. The first exposed photosensitive film is secondarily exposed using the dummy open mask 30 of the present invention.

Subsequently, the second exposed photoresist film is developed to form a photoresist pattern only in the cell region 2, and then the polysilicon film is etched using the photoresist pattern as an etch barrier to form a cell pattern, that is, a capacitor in the cell region 2 only. The lower electrode is formed.

Here, in the cell patterns formed in the cell region 2, the cell pattern 1 disposed at the cell edge may be applied to the dummy cell region 4 as well as the cell region 2 during the first exposure. When exposure is performed together, the damage of the profile is prevented. In addition, although the formation of the dummy cell is restricted in terms of reducing the chip size, as described above, when the secondary exposure using the dummy open mask 30 is performed, the dummy cell area 4 is subjected to the primary exposure. Since the dummy pattern 1a which can be formed is exposed, no dummy pattern is formed in the dummy cell region 4.

Subsequently, a meta stable polysilicon (MPS) process is performed on the cell pattern 1 to increase the surface area of the cell pattern 1, that is, the capacitor lower electrode.

As a result, when the exposure process is performed by using the exposure masks of the present invention, the abnormal pattern is formed at the edge of the cell, and the chip size can be reduced as much as possible by omitting the dummy pattern. do.

In particular, when more dummy patterns 1a are put in the dummy cell regions 4 in the exposure mask of the present invention, the profile of the cell patterns 1 disposed at the edges of the cells during the first exposure can be further improved. do.

5 is a photograph showing the shape of a cell pattern according to the presence or absence of a dummy pattern. The photo on the left shows the cell pattern formed at the cell edge without the dummy pattern, and the photo on the right shows the cell pattern when the dummy pattern is formed. Photo shows the formed cell pattern.

As shown in FIG. 5, when only the cell pattern 1 is formed without the dummy pattern 1a, the cell pattern 1 at the edge of the cell is formed in an abnormally large or small state, whereas the dummy pattern 1a is formed. In this case, it can be seen that the cell pattern 1 is normally formed.

As described above, the present invention can prevent the damage of the profile of the cell edge pattern by performing the primary exposure with the exposure mask including the dummy cell, followed by the secondary exposure with the dummy open mask exposing only the dummy cell. In addition, since the formation of the dummy cell outside the cell pattern is omitted, the limitation of the dummy cell formation due to the reduction of the chip size may be overcome, and the process yield may be increased.

1 is a photograph for explaining a pattern defect generation and particle generation process at the cell edge.

2 is a view showing a cell block of an exposure mask for manufacturing a conventional capacitor.

3 is a view showing a cell block of an exposure mask for manufacturing a capacitor of the present invention.

4 illustrates a cell block of a dummy open mask of the present invention.

5 is a photo showing a cell pattern of the cell edge with or without a dummy pattern.

-Explanation of symbols for the main parts of the drawing-

1: cell pattern 1a: dummy pattern

2, 24: cell area 4, 22: dummy cell area

20: exposure mask for capacitor manufacturing

30: Dummy Open Mask

Claims (2)

Forming a polysilicon film on the semiconductor substrate; Coating a photosensitive film on the polysilicon film; Firstly exposing the photosensitive film using an exposure mask having a mask pattern including a cell region and a dummy cell region outside the cell region; Second exposure of the first exposed photoresist using a dummy open mask that opens only the dummy cell region; Developing the second exposed photoresist to form a photoresist pattern only in the cell region; And And etching the polysilicon layer using the photoresist pattern as an etch barrier to form a cell pattern only in the cell region. The method of claim 1, further comprising, after forming the cell pattern, performing an MPS process on the cell pattern.