KR20050097153A - Semiconductor memory device - Google Patents

Abstract

The present invention is to provide a semiconductor memory device that can be tested by turning off the over-driver to determine the need for over-driving, the present invention for the memory cell array; A sense amplifier array comprising a plurality of bit line sense amplifiers for sensing and amplifying data carried on bit line pairs of the memory cell array; First driving means for driving the first power line of the bit line sense amplifier to a normal voltage; Second driving means for driving the second power line of the bit line sense amplifier to a ground voltage; Third driving means for driving the first power line of the bit line sense amplifier to an overdriving voltage; Test mode signal generation means for generating an overdriver test signal having an activation section including an overdriving section of the bit line sense amplifier; And sensing amplifier power line driving control means for generating first to third control signals for controlling the first to third driving means, and deactivating the third control signal in response to the overdriver test signal. A semiconductor memory device is provided.

Description

Semiconductor memory device {SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly to overdriving structures of semiconductor memory devices.

In general, as a low driving voltage is used to reduce the power of memory devices, there have been various technical supplements to help the operation of the bit line sense amplifiers in memory devices including DRAM, and one of them is overdriving the bit line sense amplifiers. Structure.

Typically, data of a plurality of memory cells connected to a word line activated by a row address is transferred to a bit line, and the bit line sense amplifier senses and amplifies the voltage difference between the pair of bit lines.

During the above process, since the thousands of bit line sense amplifiers start to operate at the same time, the bit line sense amplifier driving time is determined depending on whether it is possible to supply a sufficient amount of current to drive it. However, it is difficult to supply a sufficient amount of current at a moment due to the decrease in the operating voltage according to the trend of lowering the power consumption of the memory device. In order to solve this problem, a voltage higher than the normal voltage (typically, an internal core voltage) is instantaneously supplied to the power line (RTO) of the bit line sense amplifier at the initial stage of operation of the bit line sense amplifier (just after charge sharing between the cell and the bit line). A bit line sense amplifier overdriving scheme is adopted.

1 is a block diagram illustrating a semiconductor memory device having an overdriving structure according to the related art.

Referring to FIG. 1, a semiconductor memory device may include a memory cell array block 10 and a bit line sensing amplification block for sensing and amplifying data of bit line pairs BL and / BL of the memory cell array block 10. 20), a normal voltage driver PM1 and a ground voltage driver NM1 for supplying and driving the core voltage Vcore and the ground voltage Vss to the bit line sense amplification block 20, and a bit line sense amplification block. In the initial operation of the operation 20, the over driver PM2 for supplying the power supply voltage Vdd temporarily, the normal voltage driver PM1, and the power control signals in1 to in4 are applied to the normal voltage driver PM1, The SA power line driver controller 30 is configured to generate the control signals out1, out2, and out3 for activating the ground voltage driver NM1 and the overdriver PM2.

For reference, the equalization signal eq is precharged by connecting the first BL sense amplifier power line RTO and the second BL sense amplifier power line SB of the bit line sense amplifier in the bit line sense amplifier block 20. This is a signal to do.

FIG. 2 is an internal circuit diagram of the SA power line driver controller 30 of FIG. 1.

Referring to FIG. 2, the SA power line driver control unit 30 receives the power control signals in1 to in3 during activation of the power control signal in4 and overdrive control signal out1, normal driving control signal out2, and ground driving control. And a signal generator 32 for generating a signal out3, and an output 34 for converting and inverting the level of each output signal of the signal generator 32 and outputting it.

FIG. 3 is an operation waveform diagram of FIG. 1, and with reference to this, the operation of the semiconductor memory device from the activation of the active signal act until the precharge signal pcg is activated will be described.

The power supply control signals in1 to in4 are activated by the active signal act and the row address. The SA power line driver controller 30 outputs the power control signal in1 as the ground driving control signal out3 in response to the power control signal in4, and activates the overdriving control signal out1 when the power control signals in2 and in3 are activated. To print. The overdriver PM2 applies the power voltage Vdd to the first BL sense amplifier power line RTO of the bit line sense amplifier block 20 in response to the overdriving control signal out1, and provides the ground voltage driver NM1. ) Applies a ground voltage Vss to the second BL sensing amplifier power line SB in response to the ground driving control signal out3. Accordingly, the first BL sensing amplifier power line RTO among the first BL sensing amplifier power line RTO and the second BL sensing amplifier power line SB having the same voltage level rises above the core voltage Vcore. The second BL sensing amplifier power line SB drops to the ground voltage level Vss. Subsequently, when the power supply control signals in2 and in3 are deactivated, the SA power line driver control unit 30 activates the normal driving control signal out2 in response thereto. Since the normal voltage driver PM1 applies the core voltage Vcore to the first BL sense amplifier power line RTO in the bit line sense amplifier block 20 in response to the normal driving control signal out2, the first BL sense is detected. The amplifier power line RTO drops to the core voltage Vcore. After the precharge signal pcg is activated, when the power control signals in4 and in1 are deactivated, the SA power line driver control unit 30 deactivates the ground driving control signal out3 and the normal driving control signal out2.

On the other hand, in the case of using the prior art as described above, since overdriving is always performed regardless of whether or not it is necessary, it is used even when overdriving is not necessary, thereby generating unnecessary current consumption.

The present invention has been proposed in order to solve the above problems of the prior art, and provides a semiconductor memory device capable of determining whether overdriving is necessary because the test can be performed while the overdriver is turned off.

According to an aspect of the present invention for achieving the above technical problem, a semiconductor memory device comprises a memory cell array; A sense amplifier array comprising a plurality of bit line sense amplifiers for sensing and amplifying data carried on bit line pairs of the memory cell array; First driving means for driving the first power line of the bit line sense amplifier to a normal voltage; Second driving means for driving the second power line of the bit line sense amplifier to a ground voltage; Third driving means for driving the first power line of the bit line sense amplifier to an overdriving voltage; Test mode signal generation means for generating an overdriver test signal having an activation section including an overdriving section of the bit line sense amplifier; And sensing amplifier power line driving control means for generating first to third control signals for controlling the first to third driving means, and deactivating the third control signal in response to the overdriver test signal. do.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a block diagram illustrating a semiconductor memory device for testing by turning off an overdriver according to an embodiment of the present invention.

Referring to FIG. 4, the semiconductor memory device according to the present embodiment detects and amplifies data of a memory cell array block 100 and a plurality of bit line pairs BL and / BL in the memory cell array block 100. A normal voltage driver PM3 and a ground voltage driver NM2 for supplying a core voltage Vcore and a ground voltage Vss to the bit line sense amplification block 200 and the bit line sense amplification block 200; An activation period including an over driver PM4 for temporarily supplying the power supply voltage Vdd at the initial operation of the bit line detection amplification block 200 and an operation period (overdriving period) of the over driver PM4 is provided. A test mode signal generator 300 generating an overdriver test signal tm_saovd;

Generates control signals out1, out2, and out3 for activating the normal voltage driver PM3, the ground voltage driver NM2, and the overdriver PM4 by receiving the power control signals in1 to in4. and a SA power line driver controller 400 which deactivates the ground driving control signal out3 in response to tm_saovd.

Comparing this with the semiconductor memory device (see FIG. 1) according to the related art, it can be seen that the test mode signal generator 300 for generating the overdriver test signal tm_saovd is added. In addition, the SA power line driver controller 400 may determine that the overdrive control signal out1 is activated by being controlled by the test signal tm_saovd.

Accordingly, while it was not possible to test whether the use of the overdriver PM4 is necessary in the related art, in the present invention, the overdrive test signal tm_saovd is generated and controlled by the test mode signal generator 300 to be controlled by the SA power line driver. The controller 400 may test whether overdriving is necessary by activating the overdriver PM4.

FIG. 5 is an internal circuit diagram of the SA power line driver controller 400 of FIG. 4.

Referring to FIG. 5, the SA power line driver control unit 400 receives the power control signals in1 to in3 during activation of the power control signal in4, and the overdriving control signal out1, the normal driving control signal out2, and the ground driving control. A signal generator 420 which generates a signal out3 and deactivates the overdriving control signal out1 when the overdriver test signal tm_saovd is activated, and converts the level of each output signal of the signal generator 420. And an output unit 440 for inverting and outputting the same.

The signal generator 420 may include an inverter I1 for inverting the power supply control signal in1, a NAND gate ND1 having an output signal of the inverter I1 and a power supply control signal in4, and a NAND gate ND1. Inverters I2 and I3 for delaying the output signal of the output signal as the ground driving control signal out3, NAND gate ND2 having the power supply control signals in2 and in3 as inputs, and output signals of the NAND gate ND2. And a three-input NAND gate ND3 having the overdriver test signal tm_saovd and the power control signal in4 as inputs, and an inverter for delaying the output signal of the NAND gate ND3 as an overdriving control signal out1 ( I4 and I5 and the output signals of the inverters I2 and I5 are input and implemented as NAND gates ND4 for outputting the normal driving control signal out2.

For reference, the output unit 440 includes a plurality of output units 442, 444, and 446 for converting and inverting the levels of the output signals out1, out2, and out3 of the signal generator 420. do.

FIG. 6 is an operation waveform diagram of FIG. 4, and with reference to this, the operation of a semiconductor memory device for turning off and testing an overdriver is described.

Referring to FIG. 6, the power control signals in1 to in4 are activated by the active signal act and the row address. The over driver test signal tm_saovd is activated by the test mode signal generator 300.

The SA power line driver control unit 400 activates the ground driving control signal out3 in response to the activation of the power control signals in1 and in4, and even when the power control signals in2 and in3 are applied, In response to the activation, the normal driving control signal out2 is activated without activating the overdriving control signal out1.

Subsequently, in response to the control signals out2 and out3, the normal voltage driver PM3 applies a core voltage Vcore to the first BL sensing amplifier power line RTO of the bit line sensing amplifier block 200, and supplies a ground voltage driver ( NM2 applies the ground voltage Vss to the second BL sense amplifier power line SB in response to the ground voltage driving signal out3. Therefore, the first BL sensing amplifier power line RTO among the first BL sensing amplifier power line RTO and the second BL sensing amplifier power line SB having the same voltage level rises to the core voltage Vcore. The second BL sense amplifier power line SB drops to the ground voltage level Vss.

Thereafter, when the precharge signal pcg is activated and the power control signals in4 and in1 are deactivated, the SA power line driver controller 400 deactivates the ground driving control signal out3 and the normal driving control signal out2.

When using the semiconductor memory device for the over-driver test according to the present invention, it can be seen through the test whether or not the gain can be obtained through the over-driving.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention described above can determine whether or not overdriving is required.

1 is a block diagram of a semiconductor memory device according to the prior art.

FIG. 2 is an internal circuit diagram of the BL drive controller of FIG. 1. FIG.

3 is an operational waveform diagram of FIG. 1.

4 is a block diagram of a semiconductor memory device for testing by turning off the overdriver according to the present invention.

5 is an internal circuit diagram of an overdriver on / off and driving control unit of FIG. 4;

6 is an operational waveform diagram of FIG. 4.

* Explanation of the symbols of the main parts of the drawings

300: test mode signal generator

400: S / A power line driver control unit

Claims (2)

Memory cell arrays; A sense amplifier array comprising a plurality of bit line sense amplifiers for sensing and amplifying data carried on bit line pairs of the memory cell array; First driving means for driving the first power line of the bit line sense amplifier to a normal voltage; Second driving means for driving the second power line of the bit line sense amplifier to a ground voltage; Third driving means for driving the first power line of the bit line sense amplifier to an overdriving voltage; Test mode signal generation means for generating an overdriver test signal having an activation section including an overdriving section of the bit line sense amplifier; And Sensing amplifier power line driving control means for generating first to third control signals for controlling the first to third driving means and deactivating the third control signal in response to the overdriver test signal. A semiconductor memory device having a. The method of claim 1, The sensing amplifier power line drive control means, A signal generator for generating the first to third control signals by receiving a power control signal and deactivating only the third control signal when the overdriver test signal is activated; and converting a level of an output signal of the signal generator; And output unit for inverting and outputting A semiconductor memory device comprising: a.