KR20050092564A - Method of manufacturing soi device - Google Patents

Abstract

The present invention discloses a method for manufacturing an SOH element. The disclosed method for manufacturing the SOH device of the present invention comprises the steps of sequentially forming an oxide film and a polysilicon film on a silicon substrate; Etching the polysilicon film to form an active region and a device isolation region, followed by ion implantation to form N wells and P wells; Forming a nitride film on an oxide film surface of the device isolation region and on both sidewalls of the polysilicon film; Forming a gate oxide film on the polysilicon film in the active region; Forming a polysilicon film for metallization on the nitride film surface; Forming a polysilicon film for a floating gate on the gate oxide film; Etching the polysilicon layer and the gate oxide layer for the floating gate to form a floating gate; Performing ion implantation on a surface of the polysilicon film to adjust the threshold voltage of the floating gate; Forming an HLD oxide layer on the substrate resultant, and then etching back the HLD oxide layer to form LDD spacers on both sidewalls of the floating gate; Implanting ions into surfaces of both sides of the floating gate to form source / drain regions; And forming a titanium silicide layer on the floating gate, the source / drain region, and the device isolation region.

Description

Manufacturing method of SOHI element {METHOD OF MANUFACTURING SOI DEVICE}

The present invention relates to a method of manufacturing a SOI device, and more particularly, to form a thin doped polysilicon film in the device isolation region before forming the silicide film on the substrate and to minimize the area by using this as a metal wiring The present invention relates to a method for manufacturing an SOH element.

As the demand for higher speed and lower power of semiconductor memory devices increases, various researches on them are being conducted in terms of devices and circuits. For example, in terms of devices, a conventional semiconductor integrated technology using a silicon wafer made of bulk silicon obtains a high speed and low power semiconductor memory device. However, due to its limitation, recently, a silicon on insulator (hereinafter referred to as silicon on insulator) is used. , Semiconductor integrated technology using SOI wafers is in progress.

Here, the SOI wafer has a structure in which a buried oxide film is interposed between the supporting substrate supporting the whole and the silicon layer on which the device is formed. When manufacturing a semiconductor memory device using such an SOI wafer, a low junction capacity and a large drain current are used. Since it is possible to have characteristics, it is possible to improve the speed and the power reduction characteristics of the semiconductor memory device.

On the other hand, along with the demand for higher speed and lower power of semiconductor memory devices, there is an increasing demand for higher integration. However, when the device area is reduced, the capacitor capacity is reduced, so that the height of the capacitor must be increased in order to obtain a satisfactory capacitor capacity in the semiconductor memory device. That is, the capacitance of the capacitor is generally inversely proportional to the distance between the capacitor electrodes, and is proportional to the area of the capacitor electrode and the dielectric constant of the dielectric film. When the device area is reduced, the area of the capacitor electrode is also reduced. By increasing the height of the capacitor electrode, the result is an increase in the height of the capacitor.

However, when the height of the capacitor is increased as described above, a satisfactory capacitor capacity can be obtained. On the other hand, the step difference between the cell region and the peripheral circuit region is increased, so that in the subsequent metallization process, the peripheral circuit region is increased. It is very difficult to form contact holes, and process margins are required in consideration of electromigration.

As illustrated in FIGS. 1A to 1B, since an area for bulk contact is required when manufacturing an SOI device, an area efficiency of the device is deteriorated.

Therefore, in order to solve the above problems, the present invention, before forming the silicide film on the substrate, before forming the silicide film doped polysilicon film is formed on the thin film and used as metal wiring SOS to minimize the area Its purpose is to provide a method for manufacturing an eye device.

SOI device manufacturing method of the present invention for achieving the above object comprises the steps of sequentially forming an oxide film and a polysilicon film on a silicon substrate; Etching the polysilicon film to form an active region and a device isolation region, followed by ion implantation to form N wells and P wells; Forming a nitride film on an oxide film surface of the device isolation region and on both sidewalls of the polysilicon film; Forming a gate oxide film on the polysilicon film in the active region; Forming a polysilicon film for metallization on the nitride film surface; Forming a polysilicon film for a floating gate on the gate oxide film; Etching the polysilicon layer and the gate oxide layer for the floating gate to form a floating gate; Performing ion implantation on a surface of the polysilicon film to adjust the threshold voltage of the floating gate; Forming an HLD oxide layer on the substrate resultant, and then etching back the HLD oxide layer to form LDD spacers on both sidewalls of the floating gate; Implanting ions into surfaces of both sides of the floating gate to form source / drain regions; And forming a titanium silicide layer on the floating gate, the source / drain region, and the device isolation region.

Here, the step of forming the N well and P well is performed at a temperature of 1000 ~ 1100 ℃.

The nitride film is formed to a thickness of 400 to 700 kPa, and the polysilicon film for metal wiring is formed to a thickness of 700 to 1200 kPa.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views illustrating a method of manufacturing an SOI device according to an exemplary embodiment of the present invention.

As shown in FIG. 2A, an oxide film 22 and a polysilicon film 23 are formed on the silicon substrate 21, and then a photoresist pattern for defining an active region on the polysilicon film 23 is not shown. C).

As shown in FIG. 2B, the polysilicon layer 23 is etched using the photosensitive layer pattern to form active regions 23a and 23b and device isolation regions 24. Subsequently, P-type impurity ions are implanted into the active region 23a to form a P well, and N-type impurity ions are implanted into the surface of the active region 23b to form an N well. At this time, ion implantation proceeds at the temperature of 1000-1100 degreeC.

As shown in FIG. 2C, after the nitride film 25 is formed on both the oxide film surface 22 and the polysilicon film 23 on both sides of the device isolation region 24, a photoresist pattern (not shown) is formed on the nitride film 25. ). Here, the nitride film 25 is formed to a thickness of 400 to 700 GPa.

Then, after the photoresist pattern is dry-etched to remove a predetermined portion, a gate oxide layer 26 is formed on the polysilicon layer 23 of the active regions 23a and 23b, and then the polysilicon layer 23 is formed. The photosensitive film pattern remaining in the portion is etched and removed.

As shown in FIG. 2D, the polysilicon film 27 for metal wiring is thinly formed on the surface of the nitride film 25, and then the polysilicon film for metal wiring of the active regions 23a and 23b except the device isolation region 24 is formed. Etch and remove (27). Here, the polysilicon film 27 for metal wiring is a film containing impurities, and is formed in the thickness of 700-1200 kPa.

Subsequently, a floating silicon polysilicon layer 28 is formed on the gate oxide layer 26. In this case, the floating gate polysilicon film 28 is formed on both sides of the nitride film 25 and the polysilicon film 27 for metal wiring. Next, the floating gate polysilicon layer 28 and the gate oxide layer 26 are sequentially etched to form the floating gate 29.

As shown in FIG. 2E, polysilicon including the floating gate 29 and the polysilicon film 27 for metal wiring after implanting ions into the surface of the polysilicon film 23 to control the threshold voltage of the transistor. An HLD oxide film 30 is formed on the film 23 surface. Subsequently, the HLD oxide layer 30 is etched back to form LDD spacers on both sidewalls of the floating gate.

As shown in FIG. 2F, N-type and P-type impurity ions are implanted into both surfaces of the floating gate 29 to form source / drain 31a and 31b regions, and the floating gate and source / drain regions are formed. Titanium silicide films 32a and 32b are formed on the surface. Next, after the rapid thermal process (RTP) is performed on the substrate resultant, the titanium silicide layer formed on both sidewalls of the floating gate 29 is removed, and then the rapid heat treatment process is performed again.

Subsequently, although not shown, a subsequent process is performed to complete the SOI device.

As described above, in the method of manufacturing the SOI device of the present invention, a thin doped polysilicon film is formed on the surface of the nitride film, a titanium silicide film is formed on the doped polysilicon film, and used as a metal wiring to form a metal wiring for a gate or power supply. Process margins can be secured at.

In addition, the present invention can be simplified by using a contact connecting the well and the source as a doped polysilicon film without performing a separate process for forming an ohmic contact, and an electrical fatigue phenomenon during high voltage driving (Electro Stable power supply can be achieved by increasing migration.

In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person of ordinary skill in the art may make many modifications and variations without departing from the spirit of the present invention. I will understand.

As described above, the present invention can secure the process margin in the metal wiring by forming a thin doped polysilicon film in the device isolation region before forming the silicide film on the substrate and using it as a metal wiring.

In addition, in the present invention, the contact connecting the well and the source is used as the doped polysilicon film, and thus, a separate process for forming an ohmic contact may not be performed, thereby simplifying the process.

1a to 1b is a view for explaining a problem with the conventional method of manufacturing the S-eye element.

2A to 2F are cross-sectional views illustrating a method of manufacturing an SOH element according to an exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

21 silicon substrate 22 oxide film

23 polysilicon film 24 device isolation region

25 nitride film 26 gate oxide film

27 polysilicon film for metal wiring 28 polysilicon film for floating gate

29: floating gate 30: LDD spacer

31a, 31b: source / drain regions 32a, 32b: titanium silicide film

Claims (4)

Sequentially forming an oxide film and a polysilicon film on the silicon substrate; Etching the polysilicon film to form an active region and a device isolation region, followed by ion implantation to form N wells and P wells; Forming a nitride film on an oxide film surface of the device isolation region and on both sidewalls of the polysilicon film; Forming a gate oxide film on the polysilicon film in the active region; Forming a polysilicon film for metallization on the nitride film surface; Forming a polysilicon film for a floating gate on the gate oxide film; Etching the polysilicon layer and the gate oxide layer for the floating gate to form a floating gate; Performing ion implantation on a surface of the polysilicon film to adjust the threshold voltage of the floating gate; Forming an HLD oxide layer on the substrate resultant, and then etching back the HLD oxide layer to form LDD spacers on both sidewalls of the floating gate; Implanting ions into surfaces of both sides of the floating gate to form source / drain regions; And And forming a titanium silicide film on the floating gate, the source / drain region, and the device isolation region. The method of claim 1, wherein the forming of the N well and the P well is performed at a temperature of 1000 to 1100 ° C. The method of claim 1, wherein the nitride film is formed to a thickness of 400 ~ 700 GPa. The method of claim 1, wherein the polysilicon film for metallization is formed to a thickness of 700 to 1200 GPa.