KR20050082332A - Nonvolatile memory device with improved on cell threshold voltage characteristics and method for manufacturing the same - Google Patents

Abstract

A nonvolatile memory device including a memory cell having improved on-cell threshold voltage characteristics is provided. The nonvolatile memory cell has a memory transistor having a relatively shallow implantation depth in the source region, which is a double junction structure, than the floating junction region and the drain region.

Description

Nonvolatile memory device with improved on cell threshold voltage characteristics and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device having a Flotox type EEPROM cell providing a source region for improving on cell threshold voltage characteristics and a method of manufacturing the same.

Unlike SRAMs and DRAMs, EEPROM cells are electrically volatile and non-volatile memory cells, and data is not erased even when power is not supplied. EEPROM cells have recently been expanded in various fields.

There are two types of EEPROM cells: a flash type, in which one transistor consists of one cell, and a floating gate tunnel oxide (FLOTOX) type, in which two transistors constitute one cell. Since the flash type cell is composed of one transistor, the unit cell size has the advantage that the unit cell size is small, but the reliability thereof is considerably lower than that of the Flotox type cell.

For this reason, the application of Flotox type EEPROM cells has become common to memory cells embedded in smart card IC products. FIG. 1 is a cross-sectional view showing an example of the structure of a Flotox type EEPROM cell. It is.

According to the cross-sectional view of Figure 1, it can be seen that the conventional Flotox type EEPROM cell is configured as follows.

That is, a thin tunnel oxide film 75 is formed in a predetermined portion of the active region on the semiconductor substrate 10, and a thickness thicker than the tunnel oxide film is formed in the active region on the substrate 10 except for a portion where the tunnel oxide film 75 is formed. A gate oxide film 60 is formed.

A memory transistor (MTR) having a floating gate 80F / interlayer insulating film 82I / control gate 30C stacked structure is formed over a portion of the tunnel oxide film 75 and the gate oxide film 60 positioned at the periphery thereof. A select transistor STR having a stacked structure of a first select gate 80S / interlayer insulating layer 82S / second select gate 30S is formed on the gate oxide layer 60 on one side of the memory transistor MTR.

In the substrate 10 under the tunnel oxide film 75, a junction region FJR having an elongated structure so as to overlap a predetermined portion with the memory and the select transistors MTR and STR, respectively (reference numeral 72 denotes an N + type first junction region). Reference numeral 62 denotes an N-type second junction region), and the memory transistor MTR and the predetermined portion are formed inside the substrate 10 at a point spaced apart from the first junction region 72 by a predetermined distance. The source line S of the double junction structure (the structure in which the N + type junction region 92 is formed inside the N-type junction region 82) is formed to overlap, and is spaced apart from the second junction region 62 by a predetermined distance. A bit line of a double junction structure (a structure in which an N + type junction region 94 is formed inside the N-type junction region 64) so as to overlap a predetermined portion with the selection transistor STR in the substrate 10 at a predetermined point ( D) is formed.

In this case, the floating gate 80F and the first selection gate 80S are formed of a polysilicon conductive film, and the control gate 30C and the second selection gate 30S are polysilicon or polyside (polysilicon / W). It is formed of a conductive film of silicide material, and the interlayer insulating film 82I is formed of an ONO structure.

However, as the memory capacity of the EEPROM cell increases, shrinking of the unit cell size is required, resulting in poor cell characteristics.

In order to reduce the cell size, all parts of the unit cell must be reduced. In this case, the common source region serving as the current path is also reduced so that the current rapidly decreases, resulting in an on cell failure.

The process is described below with reference to FIG. If N- ion implantation and N + ion implantation are applied to the common source S, the resistance of the N-ion implantation is very low and the resistance is high, and the implantation amount of the N + ion implantation is very high, but the spacer ( spacer) Since it is formed after forming, the area applied to the common source S is very small and does not contribute significantly to the reduction of resistance.

On the other hand, when NLDD (N-type Lightly Doped Drain) implantation and N + ion implantation are applied to a common source, the source resistance of the cell can be reduced due to the high injection amount of NLDD ion implantation, but the low voltage NMOS transistor is used for NLDD ion implantation. Since it is applied to the LV NMOS TR device, the N-halo ion implantation (p-type) is matched with the NLDD ion implantation, and the effect of reducing the resistance of the NLDD structure source region is eliminated by the N-halo ion implantation.

In addition, since NLDD ion implantation is implanted with low energy to target a thin oxide of LV NMOS TR, it is implanted too high into a high voltage thick oxide, which is a cell source region, thereby increasing cell source resistance. have.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a nonvolatile memory device capable of reducing an increase in resistance of a common source region due to a decrease in cell unit area.

According to an aspect of the present invention, there is provided a nonvolatile memory device including: a tunnel oxide film, a gate oxide film thicker than the tunnel oxide film, and continuously formed on the tunnel oxide film, on the tunnel oxide film, and the gate oxide film; And a floating gate formed of a floating gate, an inter-gate insulating film, and a control gate, a source region formed to be aligned with one side wall of the stacked gate, and aligned with the other side wall of the stacked gate, and formed under the tunnel oxide layer and the gate oxide layer. A memory transistor comprising a region; And a gate oxide film, a gate formed on the gate oxide film in parallel with the stacked gate, a floating junction region arranged on one side wall of the gate facing the other side wall of the stacked gate, and a drain region formed on the other side wall of the gate. A source transistor has a double junction structure in which a high concentration impurity region is defined within a low concentration impurity region, and a depth of the source region is relatively shallower than that of a floating junction region and a drain region. It is provided.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, a Flotox type EEPROM will be described in detail as a nonvolatile memory according to the present invention with reference to the drawings.

Referring to FIG. 3, the active region in which the EEPROM cell TR is formed is defined by the device isolation region FI. The sense line S / L is positioned perpendicular to the device isolation region FI, and the word line W / L is disposed in parallel with the sense line S / L. T / W represents a tunneling window. The floating junction region FJR is in the active region between one side of the sense line S / L and one side of the word line W / L and below the tunneling window T / W, and the active region on the other side of the sense line S / L. In the source region S, a drain region D is disposed in the active region on the other side of the word line W / L. In the drain region D, a bit line contact hole BC to be connected to the bit line B / L is disposed. The word line W / L is connected to the upper wiring through the first and second contact holes MC1 and MC2, and the sense line S / L is connected to the upper wiring through the third contact hole MC3. do. MCI represents a mask pattern for memory cell separation.

Referring to FIG. 4, an EEPROM cell TR is formed on a P-type substrate 100 according to an embodiment of the present invention. In particular, MTR and STR are spaced apart from each other on an active region defined by shallow trench isolation (STI). High voltages are applied to the MTR and STR. The MTR is formed of the tunnel oxide film 175 and the memory gate oxide film 160M, the stacked gate 252, and the source region S on both sides of the stacked gate 252 and the floating junction region FJR formed on the P-type substrate 100. It is composed. The tunnel oxide layer 175 is formed under the tunneling window T / W of FIG. 3, and is formed to have a thickness capable of tunneling F-N (Fowler-Nordheim) when programming or erasing the memory cell. Preferably, the tunnel oxide film 175 is formed in a thickness of 70-90 kV and the memory gate oxide film 160M is formed in a thickness of 200-400 kPa. The stacked gate 252 includes a floating gate 180F, an inter-gate insulating film 182I, and a control gate 230C. The inter-gate insulating film 182I is preferably composed of an oxide film (O) -nitride film (N) -oxide film (O). The STR is composed of a select gate oxide film 160S formed on the P-type substrate 100, a pseudo stacked gate 254, a drain region D on both sides of the pseudo stacked gate 254, and a floating junction region FJR. do. The similarly stacked gate 254 includes a gate 180S formed simultaneously with the floating gate 180F, an insulating film pattern 182S formed simultaneously with the inter-gate insulating film 182I, and a similar gate 230S formed simultaneously with the control gate 230C. It is desirable in terms of process simplification.

The floating junction region FJR is effectively comprised of the N + region 172 under the tunnel oxide layer 175, the memory gate oxide layer 160M, and the N- region 262 under the select gate oxide layer 160S. It is suitable for preventing punch-through with (D). The drain region D may be a mask island double diffused drain formed by restricting the N + impurity region 294 in the N− impurity region 264 to maintain high breakdown voltage characteristics. The mask island refers to the N + impurity region 294 formed limited to only a predetermined region by an ion implantation mask.

The source region S is a mask island type double junction region formed by defining the N + impurity region 292 in the N− impurity region 282. The depth of the source region S is relatively higher than the depth of the floating junction region FJP and the drain region D. FIG. Therefore, by reducing the resistance of the source region (S) it is possible to improve the on-cell characteristics of the cell.

In the present embodiment, the Flotox EEPROM cell is described as an example of the nonvolatile memory. However, the present invention may be applied to other nonvolatile memories.

Hereinafter, a method of manufacturing an EEPROM cell according to an embodiment of the present invention will be described with reference to FIGS. 5A to 5K.

Referring to FIG. 5A, the pad insulating layer 103 is formed by sequentially forming the oxide film 101 and the nitride film 102 on the integrated circuit board 100, for example, the P-type substrate 100.

Subsequently, an organic anti reflection coating (ARC) (not shown) and a photoresist 104 are coated on the pad insulating film 103. The oxide film 101 is formed to reduce the stress between the substrate 100 and the nitride film 102 and is formed to a thickness of about 100 GPa.

The nitride film 102 is used as an etching mask for etching the STI region, and is formed by depositing a silicon nitride film with a thickness of about 800 to 850 Å.

The deposition method may be a conventional method such as chemical vapor deposition (CVD), sub-atmospheric CVD (SACVD), low pressure CVD (LPCVD) or plasma enhanced CVD (PECVD).

Referring to FIG. 5B, a photoresist pattern 104a defining an active region is formed. Thereafter, the pad insulating film 103 is patterned by a dry etching method using the photoresist pattern 104a as a mask to form a pad mask 103a including the nitride film pattern 102a and the thermal oxide film pattern 101a. When etching the nitride film 102, a carbon fluoride gas is used. For example, CxFy-based, CaHbFc-based gases such as CF ₄ , CHF ₃ , C ₂ F ₆ , C ₄ F ₈ , CH ₂ F ₂ , CH ₃ F, CH ₄ , C ₂ H ₂ , C ₄ F Gas such as ₆ or a mixture thereof. At this time, Ar gas can be used as an atmospheric gas.

Referring to FIG. 5C, after the photoresist pattern 104a is removed, the trench 105 defining an active region by anisotropic dry etching the exposed P-type substrate 100 using the pad mask 103a as an etching mask is formed. Form. Photoresist pattern 104a may be ashed using conventional methods such as oxygen plasma and then removed with an organic strip.

Referring to FIG. 5D, ion implantation for adjusting the threshold voltage V _THN is performed. Preferably, indium ions (In +) are implanted with energy of 180 KeV at 1-7 × 10 ¹² atoms / cm 2 dose to form the V _THN control region 144.

Referring to FIG. 5E, the gate oxide layer 160 is formed on the entire surface of the substrate 100. The gate oxide film 160 is formed to a thickness of 200-400 Å. The gate oxide layer 160 is a dry oxidation using O ₂ gas at a temperature of 1000 to 1100 ℃, wet oxidation using a steam atmosphere at a temperature of 1000 to 1100 ℃, HCl oxidation using a mixed gas of O ₂ gas and HCl gas, O _{It is formed} by oxidation using a mixed gas of ₂ gas and C ₂ H ₃ Cl ₃ gas, and oxidation using a mixed gas of O ₂ gas and C ₂ H ₂ Cl ₂ gas. Subsequently, after forming the photoresist pattern 170 exposing the region where the N + region under the tunnel oxide film is to be formed among the floating junction regions of the EEPROM cell TR, ion implantation is performed to form the N + region 172. Preferably, As + is injected at an energy of 100 KeV at an injection amount of 1-9x10 ¹³ atoms / cm 2 to form the N + region 172 of the floating junction region.

Referring to FIG. 5F, after the photoresist pattern 170 is removed by ashing and an organic strip, a photoresist pattern (not shown) defining a tunnel window is formed. Subsequently, the gate oxide layer 160 exposed by the photoresist pattern is removed by wet etching, and then the tunnel oxide layer 175 is formed in the tunnel window. The tunnel oxide film 175 is formed to a thickness of 60-80 Å. Subsequently, the lower conductive film 180 to be the floating gate electrode of the EEPROM cell TR is formed. The lower conductive layer 180 is formed to a thickness of 1350 to 1650 Å.

As the lower conductive film 180, a polysilicon film is suitable, and may be formed by CVD, SACVD, LPCVD, or PECVD, and most preferably, LPCVD. After forming polysilicon film by LPCVD using N ₂ and SiH ₄ gas, POCl ₃ gas was used to deposit phosphorus to adjust the resistance, or N ₂ , SiH ₄ (or Si ₂ H ₆ ) and PH ₃ gas were A polysilicon film doped with LPCVD to be used is formed. After the anti-reflection film is formed on the lower conductive layer 180, the lower conductive layer 180 is patterned for each cell. Subsequently, an inter-gate insulating film 182 is formed over the entire substrate 100. The inter-gate insulating film 182 is preferably formed of an ONO film in which an oxide film is 30-70 kPa thick, a nitride film 50-80 kPa thick, and an oxide film 30-70 kPa thick.

Referring to FIG. 5G, after removing the inter-gate insulating film 182, the lower conductive film 180, and the gate oxide film 160 on the region where the LV NMOS TR is formed, the control gate of the EEPROM cell TR is disposed on the entire surface of the substrate 100. An upper conductive film 230 to be the gate electrode of the LV NMOS TR is formed. The upper conductive film 230 is preferably formed of a laminated film of a polysilicon film and a metal silicide film. After the polysilicon film is formed, phosphorus ions are deposited to control resistance or to form a doped polysilicon film, and then a metal silicide film is formed thereon. As the metal silicide film, a tungsten silicide film or the like is suitable. The polysilicon film was formed to a thickness of about 1350-1650 mmW, and the tungsten silicide film was formed to about 1000 mmW by LPCVD using SiH ₂ Cl ₂ and WF ₆ gas.

Referring to FIG. 5H, a photoresist pattern 240 defining a gate is sequentially formed on the upper conductive layer 230. The upper conductive layer 230 is etched using the photoresist pattern 240 as an etch mask to form the LV TR gate 230L.

Referring to FIG. 5I, a photoresist pattern 250 defining a gate structure of the EEPROM cell TR is formed. Using the photoresist pattern 250 as an etching mask, the upper conductive layer 230, the inter-gate insulating layer 182, and the lower conductive layer 180 are sequentially etched in a self-aligned manner to form a gate structure of the EEPROM MTR. ) And similar gate structure 254.

Referring to FIG. 5J, after the photoresist pattern 250 is removed with ashing and an organic strip, a photoresist pattern 260 defining an N-region is formed. Subsequently, N-type impurities are implanted using the photoresist pattern 260 as an ion implantation mask. Preferably, P + is ion implanted with 90 KeV energy at a 5-9 x 10 ¹² atoms / cm 2 implantation amount to form an N- region 262 of the floating junction region of the EEPROM cell TR and an N- region 264 of the drain region.

Referring to FIG. 5K, a photoresist pattern 280 defining an N- region of a source region is formed. Subsequently, N-type impurities are implanted using the photoresist pattern 280 as an ion implantation mask to form the N-region 282 of the source region of the EEPROM cell TR.

Here, the N- impurity implantation region 282 of the source region is ion implanted relatively shallower than the N-region 262 of the floating junction region and the N-region 264 of the drain region of the step illustrated in FIG. 5J.

Referring to FIG. 5L, a photoresist pattern 281 defining an LDD N− region of the LV NMOS TR is formed. Subsequently, an N-type impurity is implanted using the photoresist pattern 281 as an ion implantation mask to form the LDD N-region 284 of the LV NMOS TR.

Referring to FIG. 5M, spacers S are formed on sidewalls of the gate. The spacer is formed by depositing a nitride film on the entire surface of the substrate and then dry etching it. Subsequently, a photoresist pattern 290 defining an N + region is formed. Subsequently, N-type impurities are implanted using the photoresist pattern 290 as an ion implantation mask. Preferably, As + is ion-implanted with 50KeV energy at 10 ¹⁴ -10 ¹⁵ atoms / cm 2 dose to form N + region 292 of the source region of the EEPROM cell TR, N + region 294 of the drain region, and N + region of the LV NMOS TR. (299) is formed.

Here, the source region of the EEPROM cell TR has a mask island type double junction region structure formed by defining the N + impurity region 292 in the N− impurity region 282, and the LV NMOS TR has an NLDD structure.

Referring to FIG. 5N, an interlayer insulating layer 310 is formed on the entire surface of the substrate 100. The interlayer insulating film 310 is formed by sequentially forming a SiON film, an HDP oxide film, and a TEOS film by CVD, and then planarizing it by chemical mechanical polishing (CMP) so that the thickness of the interlayer insulating film 310 is 8100-9900 8. After the contact hole BC exposing the drain region is formed, the bit line contact plug ion implantation is performed, and then the bit line contact plug is formed. The bit line contact plug is formed by sequentially depositing a barrier metal film and a tungsten film by CVD and then CMP. Subsequently, the metal film is formed, and then patterned to form the bit line 330. The metal film is formed by sequentially stacking a titanium film, an aluminum film, and a titanium nitride film, thereby completing the process.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the present invention, the N-LDD of a low voltage transistor has a Flotox type EEPROM cell structure by adding a separate photoresist layer when forming a low concentration region of a cell source region, which is a DDD structure, in an ion implantation step for a cell source during a manufacturing process. By implanting N-type impurity ions to a depth that is independent of the region and shallower than the N-region of the drain region, the resistance of the cell source region is reduced to improve the on-cell threshold voltage characteristics of the EEPROM cell, and the current is reduced by the unit area of the EEPROM cell. There is an effect of resolving the defect caused by the reduction.

1 is a vertical sectional view of a prior art Flotox type EEPROM cell.

FIG. 2 is a partial layout diagram of the Flotox type EEPROM cell shown in FIG. 1.

3 is a partial layout diagram of a Flotox type EEPROM cell according to an embodiment of the present invention.

4 is a vertical sectional view of a Flotox type EEPROM cell according to an embodiment of the present invention.

5A to 5K are vertical cross-sectional views showing the method of manufacturing the cell structure of the Flotox type EEPROM shown in FIG.

(Explanation of symbols for the main parts of the drawing)

MTR: memory transistor STR: select transistor

100: P-type substrate S: source region

D: drain region FJR: floating junction region

160: gate oxide film 175: tunnel oxide film

252: stacked gate 254: pseudo stacked gate

Claims (5)

Tunnel oxide film, A gate oxide film thicker than the tunnel oxide film and continuously formed in the tunnel oxide film; A stacked gate formed over the tunnel oxide film and the gate oxide film and composed of a floating gate, an inter-gate insulating film, and a control gate; A source region formed to be aligned with one side wall of the stacked gate; A memory transistor formed on the other sidewall of the stacked gate and including a floating junction region formed under the tunnel oxide layer and under the gate oxide layer; And The gate oxide film, A gate formed on the gate oxide film in parallel with the stacked gate; The floating junction region aligned with one side wall of the gate facing the other side wall of the stacked gate; A selection transistor including a drain region formed in alignment with the other side wall of the gate, The source region has a double junction structure in which a high concentration impurity region is defined in a low concentration impurity region, and the depth of the source region includes a nonvolatile memory cell that is relatively shallower than the depth of the floating junction region and the drain region. Non-volatile memory device characterized in that. The method of claim 1, And the nonvolatile memory cell is a FLOTOX EEPROM cell. The method of claim 1, And a low voltage transistor to which a voltage lower than that of the nonvolatile memory cell is applied. Forming a conductive region having a first depth by performing ion implantation after forming a gate oxide film over the entire substrate; Forming a tunnel oxide film having a thickness thinner than that of the gate oxide film on the conductive region having the first depth; Sequentially forming a first conductive film, an insulating film, and a second conductive film on the gate oxide film including the tunnel oxide film; The second conductive film, the insulating film, and the first conductive film are sequentially etched to partially expose the surface of the gate oxide film, and a memory transistor stacked gate structure including floating gate / inter-gate insulating film / control gate in an active region on the substrate; Simultaneously forming a select transistor stacked gate structure including a first select gate, an inter-gate insulating film, and a second select gate on the gate oxide film; And Implanting low concentration impurities of a type opposite to the substrate into the substrate to form a low concentration of a floating junction region and a drain region of a second depth overlapping the selection transistor with a predetermined depth; Implanting low concentration impurities of a type opposite to the substrate into the substrate to form a low concentration source region having a third depth that is relatively shallower than the second depth; And And implanting high concentration impurities of a type opposite to the substrate into the substrate to form a high concentration source region and a high concentration drain region having a fourth depth shallower than the second and third depths. Manufacturing method. The method of claim 4, wherein The nonvolatile memory device further includes a low voltage transistor, and wherein forming the low concentration source region of the third depth is ion implanted independently of forming the NLDD region of the low voltage transistor. Manufacturing method.