KR20050079678A - Display apparatus and method of manufacturing the same - Google Patents

Abstract

Disclosed are a display device capable of preventing a malfunction and a method of manufacturing the same. In the display device, the lower substrate includes a display area in which a pixel array is provided to display an image and a peripheral area adjacent to the display area and in which a driving circuit driving the pixel array is provided. The upper substrate faces the lower substrate, and the coupling member is interposed between the lower substrate and the upper substrate so as to correspond to the peripheral area to couple the lower substrate and the upper substrate. The spacer member corresponds to the display area and the peripheral area and is interposed between the lower substrate and the upper substrate to space the lower substrate and the upper substrate at predetermined intervals. Therefore, the spacer in the peripheral area can prevent corrosion of the driving circuit provided in the lower portion of the coupling member.

Description

DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME}

The present invention relates to a display device and a manufacturing method thereof, and more particularly, to a display device and a method for manufacturing the same that can prevent a malfunction.

In general, a liquid crystal display device includes a liquid crystal display panel having a plurality of gate lines and a plurality of data lines, a gate driving circuit for outputting gate signals to the plurality of gate lines, and a data driving circuit for outputting data signals to the plurality of data lines. Is made of.

The gate driving circuit and the data driving circuit have a chip shape and are mounted on the liquid crystal display panel. However, in recent years, in order to increase productivity while reducing the overall size of the liquid crystal display, a structure in which a gate driving circuit is incorporated in the liquid crystal display panel has been developed.

The liquid crystal display panel includes a lower substrate having a plurality of gate lines and a plurality of data lines, an upper substrate facing the lower substrate, a liquid crystal layer interposed between the lower substrate and the upper substrate, and a coupling for coupling the lower substrate and the upper substrate. It consists of members.

In the structure in which the gate driving circuit is embedded in the lower substrate of the liquid crystal display panel, parasitic capacitance is generated between the gate driving circuit and the common electrode formed on the upper substrate. This parasitic capacitance causes a malfunction of the gate driving circuit.

Recently, a structure for disposing a coupling member between a gate driving circuit and a common electrode has been proposed as a method for reducing parasitic capacitance. In this case, the coupling member is positioned at the outermost side of the liquid crystal display panel to be exposed to air and has moisture permeability. Therefore, the gate driving circuit provided under the coupling member generates corrosion due to moisture. In particular, an impact applied to the gate driving circuit from the outside becomes a factor in accelerating corrosion of the gate driving circuit. Accordingly, there is a need for a method capable of alleviating the impact applied to the gate driving circuit in order to prevent corrosion of the gate driving circuit.

Accordingly, it is an object of the present invention to provide a display device for preventing malfunction.

Another object of the present invention is to provide a method applied to manufacturing the display device.

The display device according to an aspect of the present invention includes a lower substrate, an upper substrate, a coupling member, and a spacer.

The lower substrate includes a display area in which a pixel array is provided to display an image, and a peripheral area adjacent to the display area and in which a driving circuit for driving the pixel array is provided. The upper substrate faces the lower substrate.

The coupling member is interposed between the lower substrate and the upper substrate so as to correspond to the peripheral area to couple the lower substrate and the upper substrate. The spacer corresponds to the display area and the peripheral area and is interposed between the lower substrate and the upper substrate to space the lower substrate and the upper substrate at predetermined intervals.

According to another aspect of the present invention, there is provided a method of manufacturing a display device, including: a lower substrate having a pixel array including a display area for displaying an image and a peripheral area adjacent to the display area and having a driving circuit driving the pixel array; Forming a top substrate; forming a spacer on the upper substrate so as to correspond to the display area and the peripheral area; and in a state where the spacer is interposed between the bottom substrate and the upper substrate. Opposing the lower substrate and the upper substrate by interposing between the lower substrate and the upper substrate so as to correspond to the peripheral region.

According to such a display device and a method of manufacturing the same, it is possible to prevent the moisture retained by the moisture-permeable coupling member from penetrating into the gate driving circuit due to the impact from the outside. Therefore, malfunction of the display device due to corrosion of the gate driving circuit can be prevented.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a liquid crystal display according to an exemplary embodiment of the present invention. FIG. 2A is a cross-sectional view taken along a cutting line A-A 'shown in FIG. 1, and FIG. 2B is a cross-sectional view taken along a B-B' shown in FIG. 1.

1 to 2B, the liquid crystal display device 600 according to an exemplary embodiment of the present invention includes a liquid crystal display panel 300 for displaying an image and a liquid crystal display panel 300 embedded in the liquid crystal display panel 300. A gate driving circuit 400 outputting a gate signal to the 300 and a data driving chip 500 mounted on the liquid crystal display panel 300 to output a data signal to the liquid crystal display panel 300 are included.

The liquid crystal display panel 300 includes a lower substrate 100, an upper substrate 200 facing the lower substrate 100, and a liquid crystal layer interposed between the lower substrate 100 and the upper substrate 200. 330 and a coupling member (hereinafter, sealant) 350 for coupling the lower substrate 100 and the upper substrate 200.

The liquid crystal display panel 300 substantially includes a display area DA in which an image is displayed and first to fourth peripheral areas PA1, PA2, PA3, and PA4 adjacent to the display area DA and in which no image is displayed. Separated by.

The lower substrate 100 is provided with a pixel array 110 corresponding to the display area DA. The gate driving circuit 400 is provided in the lower substrate 100 corresponding to the first peripheral area PA1 to output the gate signal to the pixel array 110. The data driving chip 500 is mounted on the lower substrate 100 corresponding to the mounting area EA adjacent to the second peripheral area PA2 to output the data signal to the pixel array 110.

As shown in FIG. 2B, the mounting area EA is an area of the lower substrate 100 in which the lower substrate 100 extends longer than the upper substrate 200. Since the mounting area EA of the lower substrate 100 is exposed to the outside, the data driving chip 500 may be mounted on the mounting area EA.

The dummy circuit DC is further provided in the second peripheral area PA2, the third peripheral area PA3, and the fourth peripheral area PA4.

The dummy circuit DC is provided in the second peripheral area PA2 to discharge an electrostatic discharge circuit 550 for discharging a signal (for example, static electricity) other than the data signal output from the data driving chip 500. Include. The electrostatic discharge circuit 550 prevents malfunction of the liquid crystal display panel 300 due to the static electricity.

The dummy circuit DC further includes a dummy gate driving circuit 450 provided in the third and fourth peripheral regions PA3 and PA4 and having the same configuration as the gate driving circuit 400. The first thickness t1 of the gate driving circuit 400 is substantially the same as the second thickness t2 of the dummy gate driving circuit 450.

In FIG. 1, the dummy circuit DC includes one dummy gate driving circuit 450 extending from the third peripheral area PA3 to the fourth peripheral area PA4. The first and second dummy gate driving circuits may be provided in the third and fourth peripheral regions PA3 and PA4, respectively.

A color array 210 is provided on the upper substrate 200 in correspondence with the display area DA, and a dummy color is provided on the upper substrate 200 in correspondence with the first to fourth peripheral areas PA1 to PA4. An array 220 is provided. The third thickness t3 of the color array 210 is substantially the same as the fourth thickness t4 of the dummy color array 220.

Between the lower substrate 100 and the upper substrate 200 is provided with a spacer member 230 for maintaining a constant distance (hereinafter, cell gap) of the lower substrate 100 and the upper substrate 200. .

The spacer 230 may correspond to the first spacer 231 provided on the color array 210 and the first to fourth peripheral areas PA1 to PA4 corresponding to the display area DA. The second spacer 232 is provided on the dummy color array 220. The first spacer 231 is interposed between the pixel array 110 and the color array 210, and the second spacer 232 is disposed between the gate driving circuit 400 and the dummy color array 220. Interposed between the dummy circuit DC and the dummy color array 220.

As described above, since the first thickness t1 of the gate driving circuit 400 is substantially the same as the second thickness t2 of the dummy circuit DC, the first to fourth peripheral areas PA1 ˜to. In PA4), the second spacer 232 has a uniform height. Therefore, the cell gap of the liquid crystal display panel 300 is uniformly maintained in the first to fourth peripheral areas PA1 to PA4.

The sealant 350 is interposed between the lower substrate 100 and the upper substrate 200 in the first to fourth peripheral regions PA1 to PA4 and has an open loop shape. An injection hole 351 is formed at one side of the sealant 350, and the lower substrate 100 and the upper substrate 200 are coupled by the sealant 351 through the injection hole 351. Liquid crystal is injected. Therefore, the liquid crystal layer 330 is formed between the lower substrate 100 and the upper substrate 200. Thereafter, the injection hole 351 is sealed by a sealing member 360 made of the same material as the sealant 350.

3 is a plan view of the lower substrate shown in FIG. 1.

Referring to FIG. 3, the display area DA of the lower substrate 100 is perpendicular to the first to nth gate lines GL1 to GLn extending in the first direction D1 and perpendicular to the first direction D1. The first to m th data lines DL1 to DLm extending in the second direction D2 are provided.

The pixel array 110 is provided in the pixel area defined by the first to nth gate lines GL1 to GLn and the first to mth data lines DL1 to DLm. The pixel array 110 includes n × m pixels, and each pixel includes a thin film transistor (TFT) 111 and a pixel electrode 112 connected to a drain of the TFT 111. Include. The pixel electrode 112 is made of indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material.

The gate driving circuit 400 is electrically connected to first ends of the first to nth gate lines GL1 to GLn to sequentially output gate signals to the first to nth gate lines GL1 to GLn. do. The gate driving circuit 400 will be described in detail later with reference to FIG. 5.

Meanwhile, the data driving chip 500 is electrically connected to first ends of the first to m th data lines DL1 to DLm to output data signals to the first to m th data lines DL1 to DLm. do. An electrostatic discharge circuit 550 is further provided between the data driving chip 500 and the first ends of the first to m th data lines DL1 to DLm. The electrostatic discharge circuit 550 will be described in detail later with reference to FIG. 6.

The dummy gate driving circuit 450 is adjacent to a second end of the first to nth gate lines GL1 to GLn and a second end of the first to mth data lines DL1 to DLm.

FIG. 4A is an enlarged view of portion C shown in FIG. 2A, and FIG. 4B is an enlarged view of portion D shown in FIG. 2A.

4A and 4B, the color array 210 and the first spacer 231 are provided in the display area DA of the upper substrate 200, and the dummy is formed in the third peripheral area PA3. The color array 220 and the second spacer 232 are provided.

The color array 210 includes a light blocking film 211, a color filter 212, and a common electrode 213. The color filter 212 is composed of red (R), green (G), and blue (B) color pixels, and the light shielding film 211 is provided between the color pixels R, G, and B, and each color. The area of the pixel is bounded. The common electrode 213 is made of ITO or IZO, which is a transparent conductive material, and is provided on the color filter 212 and the light blocking film 211.

The first spacer 231 is disposed on the common electrode 213 and is formed in a region where the light blocking film 211 is formed, and thus the liquid crystal display device 600 (see FIG. 1) due to the first spacer 231. It is possible to prevent the decrease in the aperture ratio (shown).

The dummy color array 220 includes a dummy light blocking film 221, a dummy color filter 222, and a dummy common electrode 223. The dummy light blocking film 221 is formed in the third peripheral area PA3 to block light provided to the third peripheral area PA3. In addition, the dummy light blocking film 221 may include the dummy gate driving circuit 450 (shown in FIG. 3) provided in the lower substrate 100 (shown in FIG. 3) corresponding to the third peripheral area PA3. Projection of the liquid crystal display device 600 on the screen is prevented.

A dummy color filter 222 including red, green, and blue color pixels R, G, and B is provided on the dummy light blocking film 221, and the dummy color filter 222 is the same patterning as the color filter 212. Through the process is formed at the same time with the color filter 212. The dummy common electrode 221 is formed on the dummy color filter 222 simultaneously with the common electrode 211. The common electrode 211 and the dummy common electrode 221 are entirely formed in the display area DA and the first to fourth peripheral areas PA1 to PA4 through the deposition process. Thus, the dummy common electrode 221 and the common electrode 211 are physically connected to each other.

The second spacer 232 is formed on the dummy common electrode 223 simultaneously with the first spacer 231 through the same patterning process as the first spacer 231.

5A through 5E are process diagrams illustrating a manufacturing process of the LCD shown in FIG. 2.

Referring to FIG. 5A, the color array 210 is formed in the display area DA of the upper substrate 200, and the dummy color array 220 is formed in the first and third peripheral areas PA1 and PA3. . Thereafter, as shown in FIG. 5B, first and second spacers 231 and 232 are formed on the color array 210 and the dummy color array 220, respectively.

Referring to FIG. 5C, the pixel array 110 is formed in the display area DA of the lower substrate 100, and the gate driving circuit 400 is formed in the first peripheral area PA1. The dummy gate driving circuit 450 is formed in the peripheral area PA3. 5D, sealants 350 are formed in the first and third peripheral areas PA1 and PA3 of the lower substrate 100.

5E, the upper substrate 200 and the lower substrate 100 face each other in a state spaced apart by the heights of the first and second spacers 231 and 232. The upper substrate 200 and the lower substrate 100 are coupled by the sealant 350. In particular, in the first peripheral area PA1, the sealant 350 is disposed between the gate driving circuit 400 and the common electrode 213 (shown in FIG. 4A) formed on the upper substrate 200. It serves to reduce the parasitic capacitance formed.

In this case, the second spacer 232 is formed in the first and third peripheral areas PA1 and PA3 together with the sealant 350 to uniform the cell gap of the liquid crystal display 600 (refer to FIG. 1). Keep it. In addition, the sealant 350 couples the upper substrate 200 and the lower substrate 100 through a bonding process, and the second spacer 232 is disposed below the sealant 350 during the bonding process. The impact applied to the gate driving circuit 400 is alleviated. Furthermore, it is possible to prevent corrosion of the gate driving circuit 400 generated due to the impact, and to prevent malfunction of the gate driving circuit 400 due to corrosion.

Referring again to FIG. 2A, the liquid crystal layer 330 is formed between the upper substrate 200 and the lower substrate 100 coupled by the sealant 350.

5A through 5E illustrate a structure in which the first and second spacers 231 and 232 are formed on the upper substrate 200 during the manufacturing process of the upper substrate 200, but the first and second spacers 231 and 232 are formed on the upper substrate 200. Spacers 231 and 232 may be formed on the lower substrate 100 during the manufacturing process of the lower substrate 100.

FIG. 6 is a block diagram specifically illustrating an internal configuration of the gate driving circuit illustrated in FIG. 3.

Referring to FIG. 6, the gate driving circuit 40 includes one shift register made up of a plurality of stages SRC1 to SRCn connected to each other. Each stage of the shift register is composed of one S-R latch and an AND gate.

In operation, the S-R latch is activated by the output signal of the previous stage and deactivated by the output signal of the next stage. The AND gate AND generates gate signals OUT1 to OUTn when the S-R latch is in an activated state and the first or second clocks CKV and CKVB provided are at a high level.

The first clock CKV is applied to the odd stage SRC1, and the second clock CKVB having a phase different from that of the first clock CKV is applied to the even stage SRC2 and SRCn. . Here, the first clock CKV and the second clock CKVB have opposite phases.

Accordingly, the AND gate AND of the odd-numbered stage SRC1 generates the gate signal OUT1 when the S-R latch is activated and the first clock CKV is at a high level. The AND gate AND of the even-numbered stages SRC2 and SRCn generates gate signals OUT2 and OUTn when the S-R latch is activated and the second clock CKVB is at a high level.

FIG. 7 is a circuit diagram specifically illustrating an internal configuration of the electrostatic discharge circuit shown in FIG. 3.

Referring to FIG. 7, the electrostatic discharge circuit 550 includes first to m th PMOS transistors T1-1 to T1-m and first to m th NMOS transistors T2-1 to T2-m. A PMOS transistor and an NMOS transistor are connected in pairs to each of the first to mth data lines DL1 to DLm.

Gates and sources of the first to mth PMOS transistors T1-1 to T1-m are commonly connected to a first driving voltage VDD, and drains thereof correspond to the corresponding first to mth data lines DL1 to m. DLm) respectively. Gates and sources of the first to mth NMOS transistors T2-1 to T2-m are commonly connected to a second driving voltage VSS, and drains thereof correspond to the corresponding first to mth data lines DL1 to m. DLm) respectively.

Here, it is assumed that a signal input to the first to m-th data lines DL1 to DLm and having a predetermined level is a first signal, and the first to m-th data line DL1 deviates from a predetermined level of the first signal. Suppose that the signal input to ~ DLm) is the second signal. In addition, the first to mth PMOS transistors T1-1 to T1-m and the first to mth NMOS transistors T2-1 to T2-m are not driven when the first signal is provided. It is manufactured to satisfy the driving condition when the second signal is provided.

When the first to m th transistors T1 to T1 to m are driven by the second signal to the first to m th data lines DL1 to DLm, the first to m th data lines DL1. The potential of ˜DLm is raised to the first driving voltage VDD. In this case, the first to mth NMOS transistors T2-1 to T2-m are driven by a potential difference between the first driving voltage VDD and the second driving voltage VSS. Therefore, the potentials of the first to mth data lines DL1 to DLm are discharged to the second driving voltage VSS.

Meanwhile, when the first to mth NMOS transistors T2-1 to T2-m are driven by the second signal through the first to mth data lines DL1 to DLm, the first to mth The potential of each of the data lines DL1 to DLm is discharged to the second driving voltage VSS. As such, the electrostatic discharge circuit 550 may block the second signal from being provided to the first to m-th data lines DL1 to DLm.

In FIG. 7, the electrostatic discharge circuit 550 includes a PMOS transistor and an NMOS transistor. However, the electrostatic discharge circuit 550 may be formed of one PMOS transistor or one NMOS transistor, or may be composed of a plurality of diodes.

According to such a display device and a manufacturing method thereof, the spaced apart member interposed between the lower substrate and the upper substrate is provided not only in the display region but also in the peripheral region to mitigate an impact applied to the gate driving circuit provided below the coupling member. Let's do it.

Therefore, it is possible to prevent the moisture retained by the moisture-permeable coupling member from penetrating into the gate driving circuit due to the impact applied from the outside. Therefore, malfunction of the display device due to corrosion of the gate driving circuit can be prevented.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

1 is a plan view of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2A is a cross-sectional view taken along a cutting line AA ′ shown in FIG. 1.

FIG. 2B is a cross-sectional view taken along the cutting line BB ′ shown in FIG. 1.

3 is a plan view of the lower substrate shown in FIG. 1.

4A is an enlarged view of a portion C shown in FIG. 2.

4B is an enlarged view of a portion D shown in FIG. 2.

5A through 5E are process diagrams illustrating a manufacturing process of the LCD shown in FIG. 2.

FIG. 6 is a block diagram specifically illustrating an internal configuration of the gate driving circuit illustrated in FIG. 1.

FIG. 7 is a circuit diagram specifically illustrating an internal configuration of the electrostatic discharge circuit shown in FIG. 1.

<Explanation of symbols for the main parts of the drawings>

100: lower substrate 110: pixel array

200: upper substrate 210: color array

220: dummy color array 231: first spacer

232: second spacer 300: liquid crystal display panel

400: gate driving circuit 450: dummy gate driving circuit

500: data driving chip 550: electrostatic discharge circuit

600: liquid crystal display device

Claims (7)

A lower substrate including a display area having a pixel array to display an image and a peripheral area adjacent to the display area and having a driving circuit driving the pixel array; An upper substrate facing the lower substrate; A coupling member corresponding to the peripheral region and interposed between the lower substrate and the upper substrate to couple the lower substrate and the upper substrate; And And a spacer member corresponding to the display area and the peripheral area and interposed between the lower substrate and the upper substrate to space the lower substrate and the upper substrate at predetermined intervals. The method of claim 1, wherein the spacer member, A first spacer maintaining a gap between the lower substrate and the upper substrate in the display area; And And a second spacer provided in the peripheral area to mitigate an impact applied to the driving circuit while maintaining a gap between the lower substrate and the upper substrate. The method of claim 2, wherein the driving circuit is provided in a portion of the peripheral area, And the lower substrate further comprises a dummy circuit disposed in the remaining portion of the peripheral area and having a height substantially equal to that of the driving circuit. The method of claim 3, wherein the upper substrate, A color array provided in the display area; And And a dummy color array disposed in the peripheral area and having a height substantially equal to that of the color array. The display device of claim 4, wherein the first gap in the display area is substantially the same as the second gap in the peripheral area. Forming a lower substrate including a display area having a pixel array to display an image and a peripheral area adjacent to the display area and having a driving circuit for driving the pixel array; Forming an upper substrate; Forming a spacer on the upper substrate to correspond to the display area and the peripheral area; Opposing the lower substrate and the upper substrate with each other with the spacer member interposed therebetween; And And coupling the lower substrate and the upper substrate with a coupling member interposed between the lower substrate and the upper substrate so as to correspond to the peripheral area. The method of claim 6, wherein the spacer member, A first spacer maintaining a gap between the lower substrate and the upper substrate in the display area; And And a second spacer provided in the peripheral area to mitigate an impact applied to the driving circuit while maintaining a gap between the lower substrate and the upper substrate.