KR20050074752A - Method of controlling traffic between bus master and bus slave - Google Patents

Abstract

The present invention utilizes an ARTRY (Address Retry) signal to transfer data from a bus master to another external bus or device in a CPU bus system such as a Power PC. The present invention relates to a traffic control method between a bus master and a bus slave capable of controlling traffic flow with simple circuits and logic. A traffic control method between a bus master and a bus slave according to the present invention includes: a first step of sensing data transmission from a bus master at a bus slave; And a second step of transmitting, by the bus slave, an ARTRY signal (Address Retry Signal) to the bus master when an overflow state of data occurs in the data storage device of the bus slave. .

Description

Method of controlling traffic between bus master and bus slave}

The present invention relates to a traffic control method between a bus master and a bus slave. More specifically, the present invention relates to an ARTRY (Address Retry) signal in transferring data from a bus master to another external bus or device in a processor bus system such as a power PC. The present invention relates to a traffic control method between a bus master and a bus slave that can control traffic flow using a relatively simple circuit and logic.

1 is a bus configuration diagram for transferring data from the bus master 11 to the bus slave 15 in the prior art, in which there are 32 address buses, 64 data buses, and 18 controls for data transfer. I need a signal bus. The bus master 11 refers to a subject that reads or writes data. The bus master 11 corresponds to a host processor, and the bus slave 15 responds to the request when the bus master 11 tries to read or write data. These include memory controllers and MAC controllers.

In the prior art, when transmitting data from the bus master 11 to the bus slave 15, the bus slave 15 appropriately issues a bus termination signal in consideration of traffic. To control traffic. That is, if the bus master 11 is transmitting data at a high speed and the bus slave 15 has difficulty in processing it, the bus termination signal may be issued to control the amount of data transmitted in unit time. Can be.

In the above-described prior art, the bus slave 15 should be able to accommodate as many as 100 signals in order to receive data transmission from the bus master 11, the internal logic is relatively complicated, and the development time is long. However, skilled personnel are needed.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object of the present invention is to transfer data from a bus master to another external bus or device in a processor (CPU) bus system such as a power PC. It provides traffic control method between bus master and bus slave that can control traffic flow with relatively simple circuit and logic by utilizing ARTRY signal in transmission.

Summary of the Invention

A traffic control method between a bus master and a bus slave according to the present invention includes: a first step of sensing data transmission from a bus master at a bus slave; And a second step of transmitting, by the bus slave, an ARTRY signal (Address Retry Signal) to the bus master when an overflow state of data occurs in the data storage device of the bus slave. .

In the first step, the bus slave may sense a data transfer from the bus master by receiving a chip selector (CS) signal and a read / write (RW) signal from a memory controller. The transmission of the ARTRY signal is continued until the ABB (Address Busy) signal is applied from the bus master.

Example

The construction, operation, effects and other features of the present invention will be clarified by one preferred embodiment according to the present invention described below with reference to the drawings. Figure 2 shows a bus diagram for transferring data from a bus master to a bus slave in one preferred embodiment of the present invention.

In the present invention, unlike the prior art, in the data transfer from the bus master 21 to the bus slave 25, the memory controller 23, which is a kind of bus slave, is utilized. That is, when the bus master 21 transmits data to the bus slave 25, the memory controller 23 receives the address information through the address bus, and sends a CS (Chip Selector) signal and Rd / to the corresponding bus slave 25. The Wr (Read / Write) signal is applied to inform that data is transmitted from the bus master 21.

When transmitting data from the bus master 21 to the bus slave 25, the bus slave 25 appropriately issues an ARTRY signal (Address Retry Signal) in consideration of the amount of data transmitted. Traffic control is possible. The ARTRY signal is a signal set to stop the current operation of the bus master 21 for a predetermined time.

In more detail, when the data transfer rate of the bus master 21 is higher than the speed that the bus slave 25 can accept, the data storage device of the bus slave 25 is FIFO (not shown). If the data is more than the capacity of the FIFO, if the traffic control is not performed, an overflow occurs. Accordingly, when the data is almost full in the FIFO, the FIFO generates an FF_AF signal (FIFO Almost Full) signal, and the bus slave 25 receives an ABB signal (Address Busy Signal) from the bus master 21. The ARTRY signal is generated until the data transfer of the bus master 21 is suspended. If the FIFO is full even after the bus slave 25 receives the ABB signal from the bus master 21, the bus slave 25 transmits the ARTRY signal again.

3 is a state diagram in the bus slave 25. When the bus slave 25 receives a CS signal and an FF_AF signal, an ARTRY signal is applied to the bus master 21 ( assert) Pause data transfer. The application of the ARTRY signal continues until the ABB signal is asserted from the bus master 21 and is deasserted when the ABB signal is applied. If the CS signal is not applied to the bus slave 25 (deassert) or the FF_AF signal is not applied (deassert), the ARTRY signal is also not applied (deassert).

It is apparent to those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit and essential features of the present invention. Accordingly, the above detailed description should not be construed as limiting in all aspects and should be considered as illustrative. The scope of the invention should be determined by reasonable interpretation of the appended claims, and all changes within the equivalent scope of the invention are included in the scope of the invention.

The present invention is a logic that can be actively utilized in the design of an ASIC or FPGA. Since the circuit requires a very small number of signals for data transfer from the muscle master to the bus slave, the circuit is simple and the internal logic can be easily implemented. It has an effect.

1 is a bus diagram for transferring data from a bus master to a bus slave in the prior art.

Figure 2 is a bus diagram for transferring data from a bus master to a bus slave in one preferred embodiment of the present invention.

3 is a state diagram in a bus slave in accordance with the present invention.

<Description of Major Reference Drawings>

21 Bus Master 23 Memory Controller

25 bus slave

Claims (3)

In the traffic control method between the bus master and the bus slave, Detecting a data transmission from the bus master at the bus slave; And A second step of transmitting, by the bus slave, an ARTRY signal (Address Retry Signal) to the bus master when an overflow state of data occurs in the data storage device of the bus slave. Traffic control method. The method of claim 1, In the first step, the bus slave detects data transmission from the bus master by receiving a Chip Selector (CS) signal and a Re / Wr (Read / Write) signal from a memory controller. How to control traffic between slaves. The method of claim 1, The transmission of the ARTRY signal continues until the ABB (Address Busy) signal is applied from the bus master.