KR20050069696A - Apparatus and method for duplexing serdes using the memory - Google Patents

Abstract

The present invention relates to the design of a Sueres (SERDES: Seriallizer / Deseriallizer, hereinafter referred to as "Serdes") having a redundant structure, and in particular, in switching the output of Susdes transmitting high-speed data in a redundant structure, The present invention relates to a sustained duplication device using a memory and a method thereof, which are suitable for a system that needs to transmit data without losing data using the memory.

The constituent means constituting the sustained duplication apparatus using the memory of the present invention proposed as described above comprises: duplicated sustains (SERDES) for converting serial data transferred from the redundant boards into parallel data; A redundant DPRAM for storing and outputting data output from the sources; A control unit controlling the storage and output of the DPRAM; A mux unit for selecting one of data output from the redundant DPRAM; And a detector for controlling the selection of the mux part.

Description

SUDES redundancy device using memory and its method {APPARATUS AND METHOD FOR DUPLEXING SERDES USING THE MEMORY}

The present invention relates to the design of a Sueres (SERDES: Seriallizer / Deseriallizer, hereinafter referred to as "Serdes") having a redundant structure, and in particular, in switching the output of Susdes transmitting high-speed data in a redundant structure, The present invention relates to a sustained duplication device using a memory and a method thereof, which are suitable for a system that needs to transmit data without losing data using the memory.

The components of the conventional dual redundant apparatuses receive serial data received from the redundant boards and converts the serial data into parallel data and outputs the data from the redundant sources. And a detector for generating and transmitting a control signal for selecting one piece of data.

Hereinafter, with reference to the accompanying Figure 1 will be described in detail the operation and preferred embodiment of the prior art consisting of the above configuration means. 1 is a block diagram of a conventional Sudes redundancy device.

Serdes (SERDES) (1, 2) receives the data coming into the serial to convert to parallel data or the data coming into the parallel data to convert to serial data. In FIG. 1, data transmitted from redundant boards are serially received and converted into parallel data.

The MUX unit 3 receives parallel data transmitted from the redundant sources and selects and outputs only one of them. That is, the data transmitted to the mux part corresponds to both data output from the duplicated sources, but only one of them is selected and output. In general, when the operation is divided into an active board and a standby board, only the data coming from the active board is selected and output.

The detector 4 plays a role of generating and transmitting a control signal so that only one piece of data from both sides of the mux unit can be selected. In other words, the detector monitors the redundant boards and if a fail occurs on a specific board (exactly the active board), the detector switches to another board (exactly a standby board) so that the mux selects data from another board. The selection signal is transmitted to the mux part.

Hereinafter, with reference to Figure 1 will be described in detail a preferred embodiment of the prior art having the configuration and operation as described above. For the sake of simplicity, as shown in FIG. 1, it is assumed that board 1 operates as an active board and board 2 operates as a standby board.

First, the boards 1 and 2, which are duplicated boards, output parallel data from a field programmable gate array (FPGA) in which data is stored, and deliver the parallel data to the surface. Then, the duplicated boards 1 and 2 of the boards 2 convert the transferred parallel data into serial data and output the serial data.

The data output from the boards 1 and 2 duplicated as described above are transferred to the first 1 and the second 2 included in the second redundant device. Then, the first one (1) and the second two (2) converts the received serial data into parallel data and outputs it. The output data is delivered to the mux part.

Only data of one side is selected and output from the mux part, and the detector generates a selection signal and transmits the selection signal to the mux part so that the mux part can select only one data.

In a typical case, the detector will generate a selection signal for the MUX unit to select data transmitted from the active board (board 1) (data output from the first one), but the detector is continuously duplicated during the data flow. If it is determined that a failure has occurred in a board (board 1) operating as an active board by monitoring the existing boards, a selection signal is generated and transmitted to the mux unit so that data coming from the board 2 can be selected.

As described above, the data selected by the MUX unit according to the detector selection signal are stored in the FPGA in the Sudred duplexer and then transferred to the corresponding board.

FIG. 2 is a timing diagram (diagram) of a data signal generated according to the operation of the prior art. Referring to this, problems of the prior art will be described below.

In FIG. 2, (a) means a data signal transmitted to the mux part from the suds 1 and (b) means a data signal transmitted to the mux part from the suds 2 and a data signal output from the mux part to the FPGA It shows the timing diagram for (C).

If data from the board 1 acting as the active board fails at the time (A), (A) data signal after this time will be abnormal signal, and (B) the data signal operates normally. It will correspond to a normal signal.

Even if a fail occurs on the board 1 that operates as the active board at the point (A), the point of time when the detector detects the fail is a point (B). At (B), the detector detects a fail and transmits a selection signal for board switching to the MUX, so that the MX selects data from the board 2 operating as the standby board at (C).

Therefore, in conclusion, (C), which is a data signal transmitted from the mux part to the FPGA, includes abnormal data during the time from the time point A to the time point C. As described above, according to the related art, when a fail occurs on the active board, a delay occurs for a predetermined period from when the fail occurs to the point where the mux selects the data coming from the standby board, so abnormal data is output from the mux part. There is a problem that is stored in the FPGA.

The present invention was devised to solve the problems of the prior art as described above. In order to prevent data loss due to a failure in a duplicated board, at least a mux part is transferred from the time point at which an active part board fails to select data. It is an object of the present invention to provide a sustained duplication apparatus and a method using a memory that enables normal data to be output from a mux part even when a fail occurs by using a memory capable of storing data transmitted up to a point in time.

In order to solve the technical problem as described above, the constituent means of forming a sudes duplication apparatus using a memory of the present invention,

Redundant SERDESs for converting serial data transferred from the redundant boards into parallel data; A redundant DPRAM for storing and outputting data output from the sources; A control unit controlling the storage and output of the DPRAM; A mux unit for selecting one of data output from the redundant DPRAM; And a detector for controlling selection of the mux part.

The control unit includes a processor that adjusts the overall operation of the DPRAM, a write counter that counts the number of data stored in the DPRAM, a read counter that counts the number of data output from the DPRAM, the write counter, and a read. Characterized in that it comprises a calculation unit for calculating the difference between the counter and the processor,

When the write counter and the read counter reach a certain value (memory depth), the write counter and the read counter are initialized to "0" again and continue the counter.

On the other hand, the constituent means of the Sudes duplexing method using another memory of the present invention,

Converting serial data transferred from the redundant board into parallel data by the duplicated source and outputting the parallel data;

Writing data output from the duplicated source to a DPRAM under control of a controller;

Determining whether a value of a write counter is greater than or equal to a predetermined value M after storing the data;

If the determination result is greater than or equal to a predetermined value, reading the stored data under the control of the controller and transferring the stored data to the mux part, and if less than the predetermined value, continuously writing to the DPRAM;

And selecting and outputting data in accordance with the selection signal of the detector.

The constant value corresponding to the difference between the write counter and the read counter is equal to or greater than the number of data stored in the DPRAM during the time it takes the MUX to select data at the time when a fail occurs in one of the redundant boards.

Hereinafter, with reference to the accompanying drawings will be described in detail the operation and the preferred embodiment related to the Sudes duplication apparatus and method using a memory of the present invention consisting of the above configuration means.

FIG. 3 is a block diagram of a Sudden duplexing apparatus using a memory according to the present invention, wherein a duplexed SERDES 10, 20, a dual DPRAM 30, 40, and a mux unit 50 are shown. ) And a detector 60 are configured.

The duplicated sudes 10 and 20 perform an operation of converting serial data coming from the duplicated boards (board 1 and board 2) shown in FIG. 3 into parallel data. In general, Sudes plays a role of converting serial data into parallel data by receiving serial data or converting serial data into serial data. It converts data into parallel data.

The redundant DPRAMs 30 and 40 receive the parallel data output from the sources and store the parallel data respectively according to the operation of the processor (not shown) of the controller and then output the same under the control of the processor of the controller. do. The duplicated DPRAM has a certain depth (M), so that starting from address 1 to M is written (read), and written to address M (to be read), starting from address 1 and written (read). .

The MUX unit 50 selects and outputs data of one of the data output from the redundant DPRAM. That is, under the control of the controller, the controller outputs data output from each of the redundant DPRAMs and outputs one data according to a detector selection signal to be described below. Normally, the data is initialized by selecting data output from the active board (or the death 1), and when a fail occurs in the active board, the data is transferred to the standby board and output from the standby board (or the death 2). To choose them.

The detector 60 generates a control signal so that the MUX can select one of the data transmitted from the redundant DPRAM. That is, in the general case, the MUX generates a selection signal for selecting the data output from the active board and transmits the selection signal to the mux part, and then fails the active board while monitoring the redundant boards (board 1 and board 2). If this occurs, the board is switched and generates and transmits a selection signal so that the mux selects data transmitted from the standby board.

On the other hand, the controller (not shown) performs an operation of controlling the operation of the data output from the redundant sources to be written (stored) in the redundant DPRAM and the operation of reading (output) the stored data. That is, a write signal is generated to be written to write data output from the duplicated source to the duplicated DPRAM, and a read signal is generated to output the data to read the stored data from the DPRAM.

Components (not shown) of the controller required to perform the above operation should include a processor, a write counter, a read counter, and a calculator.

The processor performs an operation of controlling the operation of the DPRAM as a whole, for example, generating a write signal for writing data to the DPRAM, and generating a read signal for reading data from the DPRAM.

The write counter is initialized to "0" for the first time, and when the data is stored in the DPRAM under the control of the processor, the counter is executed. When the write counter reaches the counter value corresponding to the depth M of the DPRAM, the write counter is reset to "0". "To initialize the counter. That is, the write counter counts the number of data to be stored in the DPRAM. When the data is stored one by one in the DPRAM, the counter proceeds to a counter, and when the counter value corresponds to the depth M of the DPRAM, the value is "0". Is initialized to

The read counter is initialized to "0" for the first time, and the counter is executed every time data stored in the DPRAM is read one by one. When the read counter reaches the counter value corresponding to the depth M of the DPRAM, the read counter is reset to "0". Proceed to the counter. That is, the read counter counts the number of data read from the DPRAM. When the data is read one by one from the DPRAM, the counter is counted. When the read counter reaches the counter value corresponding to the depth M of the DPRAM, the read counter is initialized to "0". .

The calculation unit periodically reads the values of the write counter and the read counter to obtain a difference, and then transfers them to the processor. That is, when the difference between the value of the write counter and the read counter is calculated and transmitted to the processor, when the processor determines that the value transmitted is greater than or equal to the predetermined value M, a read signal is generated and data is read from the DPRAM and output.

The reason why the processor generates a read signal and outputs data from the DPRAM when the difference between the value of the write counter and the read counter is greater than a constant value M (the depth value of the DPRAM) is caused by a failure in the active board. This is to store the data (abnormal data) output from the duplicated sources in the DPRAM during the time it takes the MUX to select the data coming from the standby board according to the board switching. That is, the data output from the active board among the data output from the sustain for a predetermined time as described above are stored in the DPRAM because they are abnormal data, transferred to the standby board, the data transferred from the standby board is normal data This is to select data of normal standby board by switching board.

FIG. 4 is a timing diagram of data signals (data signals shown in FIG. 3) related to the Sudden duplexing apparatus using the present invention, which will be described below. The data signal (c) refers to the data signal output from the death 1 and transmitted to the DPRAM1, the data signal (d) means the data signal output from the DPRAM to the mux part, and the data signal (e) is the death 2 Means a data signal outputted from and delivered to DPRAM2, and a data signal (bar) means a data signal outputted from DPRAM2 and delivered to the mux part, and the data signal (g) is a data signal selected from the mux part and delivered to the FPGA Means.

If Board 1 operates as an active board for the first time among the redundant boards, and if a failure occurs on Board 1 at time A, the data signal C will continue to move to an abnormal signal. Will be stored on. At this time, the number of data signals to be stored will be as much as the memory depth of DPRAM1. On the other hand, (e), which is a data signal output and moving from the board 2 acting as a standby board, will move to a normal signal, and this signal will be stored in DPRAM2. The stored data will then be read and moved to the mux.

At (B), the fail of the board 1 is detected by the detector, and at (C), the mux unit selects (B), which is a data signal transmitted from the board 2, according to the board switching. Therefore, the data signal (G) output according to the selection of the mux part corresponds to a normal data signal.

In summary, the data output from the sude is stored in the redundant (depth M) DPRAM from the time when the failure occurs on the board 1 to the time when the mux selects the data according to the board switching by the detector selection signal. It prevents the data output from the board 1 in which the fail occurred from being selected in the mux part, and causes the mux part to select the data output from the board 2 to output normal data.

5 is a flowchart illustrating a method for sustain duplication using a memory according to the present invention, which will be described in detail with reference to the present invention.

As shown in FIG. 3, when parallel data is generated in the FPGA of the redundant board and transferred to the sources in the redundant board, the sources of the redundant boards convert the parallel data into serial data and output the parallel data. Then, the duplexed sources of the dudes board using the memory convert the serial data transferred from the duplexed boards into parallel data and output the parallel data (S10). The sources in the redundant board perform an operation of converting parallel data into serial data, and the sources in the redundant device using the memory perform an operation of converting serial data into parallel data.

The data output from the duplicated sources are written to the DPRAM, and the data output from the source is written to the duplicated DPRAM according to a write signal generated by the processor included in the controller (S20). On the other hand, in the case where data output from the sudes is written to the DPRAM according to the write signal of the processor included in the controller as described above, the write counter advances the counter every time data is written. As described above, the write counter is incremented, and when it reaches a certain value (the same value as the depth of DPRAM), the write counter is initialized again and the counter is restarted from 1.

As the data is stored as described above, the value of the write counter is increased. At this time, the calculation unit in the controller must determine whether the difference between the two counter values is greater than or equal to a predetermined value by reading the write counter and the read counter value (S30). That is, it should be determined whether the difference between the values of the counters is greater than the number of data that can be stored in the DPRAM from the time when the fail occurs in the board 1 to the time when the mux selects the data generated from the board 2 according to the board transfer. By the way, as the data is written to the DPRAM, the write counter continues to increase, but the read counter waits with a value of "0". Therefore, it is the same as determining whether the value of the write counter is greater than the number of data that can be stored in the DPRAM from the time when the fail occurs in the board 1 to the time when the mux selects the data generated from the board 2 according to the board transfer.

As a result of the determination, if the difference between the value of the write counter value and the read counter value is equal to or greater than a constant value (the number of data that can be stored in the DPRAM by data movement from the time when a fail occurs on the board 1 to the time when the mux selects data), The data stored in DPRAM is read and transferred to the mux part under the control of the control. If the difference between the value of the write counter and the read counter is less than a certain value, the condition that the mux part can select the normal data does not continue. The data output from the death is written to the DPRAM (S40).

The data transmitted to the mux part is transmitted through two paths, that is, a path from which abnormal data coming from board 1 where a failure occurs and a path from board 2 into which normal data enters. In this way, the mux part selects one of the incoming data, and the mux part selects and outputs the data according to a detector selection signal (a signal for selecting the incoming data from the board 2). That is, by selecting and outputting data from the board 2 which is the normal data, the data is transferred to the FPGA in the sud redundant device using the memory so that the normal data is transferred to other boards (S50).

According to the present invention duplex apparatus and method using the memory having the configuration and operation and the preferred embodiment as described above, it is possible to store the data from the time the failure occurs on the active board to the time when the mux part selects data In case of interface with a redundant board that handles high speed serial data by using the memory, it is possible to build a stable system by performing normal operation without losing data even when the board is switched due to a board failure. There is.

1 is a block diagram of a conventional Sudes redundancy device.

2 is a timing diagram applied to a conventional Sudes redundancy device.

3 is a block diagram of a Sudden duplication apparatus using the present inventors memory.

4 is a timing diagram applied to the present invention.

5 is a flowchart of a method for susden duplication using the present inventors memory.

Claims (5)

Redundant SERDESs for converting serial data transferred from the redundant boards into parallel data; A redundant DPRAM for storing and outputting data output from the sources; A control unit controlling the storage and output of the DPRAM; A mux unit for selecting one of data output from the redundant DPRAM; And a detector for controlling selection of the mux unit. The method according to claim 1, wherein the control unit, A processor for adjusting overall operation of the DPRAM, a write counter for counting the number of data stored in the DPRAM, a read counter for counting the number of data output from the DPRAM, and a difference between the write counter and the read counter. Sude redundant apparatus using a memory, characterized in that it comprises a calculation unit for calculating and transmitting to the processor. The method according to claim 2, The write counter and the read counter are initialized to " 0 " again when a predetermined value (memory depth) is reached, and the sustained duplexing device using the memory of claim 1, wherein the counter continues. Converting serial data transferred from the redundant board into parallel data by the duplicated source and outputting the parallel data; Writing data output from the duplicated source to a DPRAM under control of a controller; Determining whether a value of a write counter is greater than or equal to a predetermined value M after storing the data; If the determination result is greater than or equal to a predetermined value, reading the stored data under the control of the controller and transferring the stored data to the mux part, and if less than the predetermined value, continuously writing to the DPRAM; And selecting and outputting data according to a select signal of the detector. The method according to claim 4, The predetermined value corresponding to the difference between the write counter and the read counter is a memory that is equal to or greater than the number of data stored in the DPRAM during the time that the mux selects data at the time when a fail occurs in one of the redundant boards. Sudes duplication method using.