KR100290560B1 - Apparatus for duplicating and controlling cell bus in ATM system - Google Patents

Abstract

The present invention improves the reliability of the cell bus by implementing a cell bus for ATM cell transmission and reception in a redundant manner, and provides a bypass path in the event of a failure of the cell bus so that cell transmission and reception are stable in an ATM system. And a control device, wherein the present invention comprises first and second cell bus masters to be connected in a one-to-one correspondence with a redundant cell bus and a duplicated cell bus to mediate the cell bus occupation between a plurality of ATM nodes. It is connected to a redundant master node and a duplicated cell bus to generate control signals and synchronization signals for cell transmission and reception, and generates a cell occupancy request signal to the duplicated master node and receives control signals from the duplicated master node. By having a plurality of redundant ATM nodes for transmitting and receiving cells through the redundant cell bus By providing a bypass path even in the event of a cell bus failure, ATM cell transmission and reception can be stabilized.

Description

Apparatus for duplicating and controlling cell bus in ATM system

The present invention relates to cell bus duplication and control thereof in an asynchronous transfer mode (ATM) system. In particular, the present invention relates to a cell bus for ATM cell transmission and reception, which improves the reliability of the cell bus and provides a duplicated cell bus controller. In addition, the present invention relates to a cell bus redundancy and control apparatus in an AMT system that provides a bypass to stably transmit and receive a cell when a failure occurs in the cell bus.

In general, an ATM system implements and uses a cell bus consisting of 37 bits as a single path for ATM cell transmission between blocks.

Figure 1 shows a typical cell bus for transmitting and receiving ATM cells.

As shown, it consists of a master ATM node 1, a plurality of ATM nodes (2 to 32), a common bus cell (CellBus: 33), communication between different ATM nodes through one cell bus 33 This is done. At this time, in order to prevent the case where several ATM nodes 1 to 32 occupy the cell bus 33 at the same time, the master ATM node 1 performs arbitration for each ATM node. The master ATM node 1 is arbitrarily determined by the operator among the ATM nodes 1 to 32 matched to the cell bus 33. The ATM node allowed to occupy the cell bus 33 transmits 57 bytes of data on a 32-bit data bus in synchronization with a control signal CBWC (CellBus Write Clock). The receiving ATM node checks the 32-bit data bus and receives it in synchronization with the control signal CBRC (CellBus Read Clock) when the destination address matches it.

FIG. 2 is a diagram illustrating the types of signal lines used in the cell bus of FIG.

As shown, the master ATM node 1 transmits a CBF signal (CellBus Frame) for synchronizing the cell bus 33 to another ATM node, and controls the cell bus 33 arbitration between ATM nodes. Cell bus occupancy between ATM nodes has its own unique cell bus occupancy address, and when the master ATM node 1 requests cell bus occupancy, the master ATM node 1 requests the cell bus occupancy. Occupancy is granted according to the order of cell bus occupancy requests of nodes.

A total of 37 signal lines make up a cell bus, and a 32-bit data bus (CBD [31..0]) for ATM cell transmission, and CBWC (CellBus), a control signal for synchronizing transmission / reception data and control signals to a clock. Write Clock) and CBRC (CellBus Read Clock). In addition, there is a CBF (CellBus Frame) signal that is a frame synchronization signal supplied from the cell bus master board to synchronize ATM nodes matched to the cell bus. There is an Ack signal, which is a signal indicating that ATM cell reception is normally performed, and a Cong signal, which is a signal indicating that ATM cell reception is abnormally performed. Here, the CBF signal is a signal supplied from the cell bus master board to another ATM node, and Ack and Cong are signals that can be transmitted and received by all ATM nodes matched to the cell bus.

However, since the conventional cell bus for transmitting and receiving ATM cells is composed of a single path, when a cell bus fails, a bypass path cannot be provided and ATM cell transmission is completely blocked between blocks.

In this case, when a failure that blocks transmission of ATM cells between blocks occurs, the entire ATM system may be abnormally operated.

Therefore, the present invention has been proposed to solve various problems occurring in the cell bus for the conventional ATM cell transmission as described above,

An object of the present invention is to implement a cell bus for ATM cell transmission and reception to improve the reliability of the cell bus and to add a redundant cell bus controller to provide a bypass path in the event of a failure in the cell bus, It is to provide a cell bus redundancy and control device in the AMT system to be made stable.

The present invention (apparatus) for achieving the above object,

In an ATM cell transceiver for transmitting and receiving cells between a master node and a plurality of ATM nodes via a cell bus,

The cell bus is implemented in redundancy,

A redundant master node that is selectively connected to the redundant cell bus to mediate cell bus occupancy between the plurality of ATM nodes and generate control signals and synchronization signals for cell transmission and reception;

A plurality of redundant ATM nodes connected to the redundant cell bus and generating a cell occupancy request signal to the redundant master node, receiving control signals from the redundant master node, and transmitting and receiving cells through the plurality of ATM nodes and the redundant cell bus. Characterized in that made.

1 is a configuration diagram of a cell bus (Cell-Bus) for transmitting and receiving ATM cells in a typical ATM system,

2 is an explanatory diagram of signals transmitted and received via the cell bus of FIG. 1;

3 is a conceptual diagram of a cell bus redundancy and control device in an ATM system according to the present invention;

4 is a block diagram of an ATM node for redundant cell bus matching in the present invention.

<Explanation of symbols for main parts of the drawings>

110: redundant master node 111: first cell bus master

112: second cell bus master 120: cell bus

121: first cell bus 122: second cell bus

131: redundant ATM node

Hereinafter, described in detail with reference to the accompanying drawings, preferred embodiments of the present invention according to the spirit as described above.

First, the general concept of the present invention will be briefly described before explaining the preferred embodiment of the present invention.

The cell bus for ATM cell transmission / reception is implemented by redundancy (cell bus A, cell bus B) to select another cell bus when a failure occurs in one cell bus. The two cell buses configured as redundancy are always active. The transmitting ATM node transmits ATM cells to both cell buses A / B, and the receiving ATM node decides which ATM cell to select. The redundancy control unit in the receiving ATM node initially selects the cell bus A, monitors the state of the cell bus A and the cell bus B, and controls the cell bus when the failure occurs in the cell bus currently in use. The cell bus is a bus composed of a clock, 32-bit data and control signals. CUBIT, a cell bus matching block, collects the fault status of the currently received ATM cell and transmits it to the controller. The control unit determines the reception cell bus switching according to the state of the received failure. Redundant ATM cell buses improve reliability and provide a bypass in the event of a failure.

Hereinafter, exemplary embodiments of the present invention will be described with reference to this concept.

Figure 3 is a conceptual diagram of a cell bus redundancy and control device of the present invention.

As shown in the drawing, the first and second cell bus masters 111 and 112 are connected in a one-to-one correspondence with the redundant cell bus 120 to mediate the cell bus occupancy between a plurality of ATM nodes and control for cell transmission and reception. A redundant master node 110 that generates a signal and a synchronization signal, and is connected to the redundant cell bus 120 to generate a cell occupancy request signal to the redundant master node 110 and control from the duplicated master node 110. It is composed of a plurality of ATM nodes 131 to 132 that receive signals and transmit and receive cells through a plurality of ATM nodes and the redundant cell bus.

The cell bus 120 is a CBFA signal for cell bus synchronization, 32-bit data for ATM cell transmission, CBWCA and CBRCA which are control signals for synchronizing transmission / reception data and control signals to a clock, and normal reception of the cell. A first cell bus 121, which is a path through which an AckA / CongA signal indicating an abnormal state is transmitted, a CBFB signal for cell bus synchronization, 32-bit data for ATM cell transmission, and a synchronization signal for transmitting / receiving data and control signals to a clock. CBWCB and CBRCB, which are control signals, and a second cell bus 122, which is a path through which AckB / CongB signals indicating normal and abnormal states of cell reception are transmitted, are duplicated.

The redundant ATM node 131 of the plurality of redundant ATM nodes 131 to 132 may include a first bus matching unit 131a for matching the first cell bus 121 and the first bus. First and second buffers 131c and 131d connected to the matching unit 131a and buffering cell data transmitted and received, and a second bus matching unit for matching the second cell bus 122 ( 131b, third and fourth buffers 131e and 131f connected to the second bus matching unit 131b to buffer cell data transmitted and received, and the first to fourth buffers 131c to 131b to 131b. Interfaces the transmission / reception buffer control unit 131g and 131h for selectively controlling the operation of 131f and the control data of the transmission / reception buffer control unit 131g and 131h, and transmits and receives the buffer control unit 131g ( 131h) is selectively connected to the first to fourth buffers 131c to 131f to receive cell data of another ATM node or to send a cell data to another ATM node. It consists Utopia matching portion (131i) for transmitting the emitter.

The operation and action of the cell bus redundancy and control device according to the present invention configured as described above are as follows.

First, the redundant master node 110 implemented with redundancy includes first and second cell bus masters 111 and 112 to correspond one-to-one with respect to each of the cell buses 120 implemented with redundancy. And the second cell bus masters 111 and 112 both operate in an active state. Here, since the operations of the first and second cell bus masters 111 and 112 are the same, only the operation of one cell bus master (here, the first cell bus master) is described below. That is, the first cell bus master 111 transmits a CBFA signal for synchronization of the first cell bus 121 connected thereto to another redundant ATM node, and controls cell bus arbitration between each redundant ATM node. . A total of 37 signal lines constituting the first cell bus 121 include 32-bit data bus CBDA for ATM cell transmission, and CBWCA and CBRCA for synchronizing transmission / reception data and control signals to a clock. In addition, there is a CBFA, which is a frame synchronization signal, and AckA and CongA signals, which are signals indicating normal and abnormality of a receiving ATM cell.

Meanwhile, a redundant ATM node having first and second bus matching units 131a and 131b in one-to-one correspondence with the first and second cell bus masters 111 and 112 in the redundant master node 110. The first and second bus matching units 131a and 131b may be connected to the first and second cell buses 121 and 122, respectively, so that the first and second cell buses 121 may be connected to each other. All 122 transmits the ATM cell and the control signal. In addition, when receiving the ATM cell and the control signal, it operates to receive the ATM cell and the control signal input from the normal cell bus among the first and second cell buses 121 and 122.

Here, the determination of the reception cell bus for the duplicated cell bus 120 in the redundant ATM node 131 is shown in Table 1-1.

Table <1-1> Cell Bus Decision Table for Reception

First Cell Bus (CellBus-A) Status Second Cell Bus (CellBus-B) Status Receive cell bus Initial state Initial state First cell bus normal normal Keep old normal abnormal First cell bus abnormal normal 2nd cell bus abnormal abnormal Keep old

Each ATM node occupies a normal cell bus under the control of the reception buffer control unit 131h. That is, the first cell bus 121 is selected in the initial state. Thereafter, the states of the first and second cell buses 121 and 122 are checked to maintain the previous state when the two cell buses 121 and 122 are in a normal state, and the two cell buses 121 and 122 are maintained. ) Remains the same even if they are all abnormal. Each ATM node monitors the state of the cell bus currently in use, and determines the switching of the receiving cell bus in the event of a failure as shown in the following table.

Table <1-2> Cell Bus Failure Types and Cell Bus Transfer Decision Table

Error name occurrence condition action Control CBRC error An error has occurred in the cell bus read clock Report fault status to the control Transfer decision based on threshold (two consecutive times) and opponent's status CBWC error An Error Occurs in the Cell Bus Write Clock Report fault status to the control Transfer decision based on threshold (two consecutive times) and opponent's status CBF error An error occurs in a cell bus frame Report fault status to the control Transfer decision based on threshold (two consecutive times) and opponent's status CRC error CRC error in cell bus data Report fault status to the control Transfer decision based on threshold (two consecutive times) and opponent's status LOOPBACK error An error occurs in the loopback data executed by each ATM node. Report fault status to the control Transfer decision based on threshold (two consecutive times) and opponent's status

That is, the transmission buffer control unit 131g controls the transmission data to be written to the first and third buffers 131c and 131e which are transmission buffers using the transmission clock and the control signal output from the utopia matching unit 131i. Generates a signal to control the first and third buffers 131c and 131e, and transmits data stored in the first and third buffers 131c and 131e to the first and second bus matching units 131a. (131b), and controls the control signal for transmission control with the first and second bus matching unit (131a) (131b).

In addition, the reception buffer controller 131h controls to allow data output from the first and second bus matching units 131a and 131b to be written to the second and fourth buffers 131d and 131f which are reception buffers. The first and second bus matching units 131a and 131b interface control signals for transmission control. In addition, the data stored in the second and fourth buffers 131d and 131f outputs received data according to a control signal of the reception buffer control unit 131h, which is selected by the duplication control decision, so that the utopia matching unit 131i is provided. To pass on. The reception clock uses a synchronous clock output from the utopia matching unit 131i to read data of the second and fourth buffers 131d and 131f.

As described above, the present invention provides a single cell by implementing a cell bus for ATM cell transmission / reception in redundancy, and implementing a redundancy of each ATM node and a master ATM node performing cell bus arbitration of each ATM node. Even in the event of a bus failure, it is possible to improve the reliability of ATM systems by enabling data transmission through the bypass path.

Claims (4)

In an ATM cell transceiver for transmitting and receiving cells between a master node and a plurality of ATM nodes via a cell bus, Implement the cell bus in a redundant manner, consisting of first and second cell bus masters to be connected in a one-to-one correspondence with the duplicated cell bus to mediate cell bus occupancy between a plurality of ATM nodes, and control signals and synchronization for cell transmission and reception. A redundant master node generating a signal; A plurality of redundant ATM nodes connected to the redundant cell bus and generating a cell occupancy request signal to the redundant master node, receiving control signals from the redundant master node, and transmitting and receiving cells through the plurality of ATM nodes and the redundant cell bus. Cell bus redundancy and control device in the AT system, characterized in that configured to include. 2. The apparatus of claim 1, wherein the first and second cell bus masters in the redundant master node are activated and operated simultaneously at the time of system driving. The CBWCA and CBRCA of claim 1, wherein the cell bus is a CBFA signal for cell bus synchronization, 32-bit data for ATM cell transmission, a control signal for synchronizing transmission / reception data, and a control signal to a clock; Control for synchronizing a clock with a first cell bus, which is a path through which AckA / CongA signals indicating normal and abnormal conditions, a CBFB signal for cell bus synchronization, 32-bit data for ATM cell transmission, transmission / reception data, and a control signal The CBWCB and CBRCB signals, and the second cell bus, which is a path through which AckB / CongB signals indicating normal and abnormal states of cell reception are transmitted, are duplicated. The cell of claim 1, wherein one of the plurality of redundant ATM nodes comprises: a first bus matching unit for matching the first cell bus and a cell connected to and transmitting and receiving the first bus matching unit; First and second buffers for buffering data, a second bus matcher for matching the second cell bus, and a third bus for buffering cell data connected to and transmitted from the second bus matcher And a fourth buffer, a transmit / receive buffer controller for selectively controlling the operations of the first to fourth buffers, and control data of the transmit / receive buffer controller, and under the control of the transmit / receive buffer controller. Cell server in the ATM system, which is selectively connected to the first to fourth buffers and comprises a utopia matching unit for receiving cell data of another ATM node or transmitting cell data to another ATM node. Redundancy and control unit.