KR100374721B1 - Dual board device and method of cellbus and block state - Google Patents

Abstract

The present invention relates to an apparatus and method for cell bus and block state board redundancy, and more particularly, to an apparatus and method for cell bus and block state board redundancy that prevents unnecessary switching by independently controlling a processor, a cell bus, and a cell bus clock in a system board. According to the present invention, by independently controlling and switching blocks in the system board, not only can stabilize the system, but also maximize the use of the blocks in the system board.

Description

DELL BOARD DEVICE AND METHOD OF CELLBUS AND BLOCK STATE}

The present invention relates to a cell bus and block state board redundancy apparatus and method in an International Moblile Telecommunication (IMT) -2000 system, and more particularly, to a processor and a cell in a system board. The present invention relates to a cell bus and block state board redundancy apparatus and method for independently controlling buses, cell bus clocks, and the like, thereby preventing unnecessary switching.

In the conventional IMT-2000 system, the cell bus and block state board redundancy device is composed of an active board and a stand-by board, and the entire board is transferred even when a specific block in the active board fails. The procedure was performed.

Therefore, the above-described cell bus and block state board redundancy device in the conventional IMT-2000 system is a problem in which unnecessary internal resources are wasted and normal blocks cannot be efficiently used as state management and switching are performed as a whole board. There was this.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is not only to stabilize the system by independently controlling and switching blocks in the system board, but also to use the blocks in the system board. To provide a cell bus and block state board redundancy apparatus and method for maximizing performance.

In order to achieve the above object, the cell bus and block state board redundancy apparatus of the present invention is connected to the master cell bus clock controller for supplying a clock to the cell bus and the master cell bus clock controller to control the cell bus and to control the cell bus clock. A master cell bus controller which checks a state and outputs a result value, and is connected to the master cell bus controller and checks its own state, the state of the master cell bus clock controller, and the state of the master cell bus controller, and corresponds thereto. An active processor board having a master processor control unit which outputs a switching control signal; And

The slave cell bus clock, which is connected to the master cell bus clock controller and is in a stand-by state and transitions to an active state when a transfer control signal is input from a master cell bus clock controller in the master processor controller when a failure occurs in the master cell bus clock controller. A slave cell bus controller which is connected to the master cell bus controller and is in a standby state, and transitions to an active state when a transfer control signal is input from a master cell bus controller in the master processor controller when a failure occurs in the master cell bus controller; And a stand-by state connected to the master processor controller, when the master processor controller receives a transfer control signal from the master processor when a failure occurs in the master processor controller. Characterized in that it consists of a stand-by processor board having a slave processor control unit for performing the operation.

In order to achieve the above object, the present invention provides a cell bus and block state board redundancy method, comprising: a tenth step of the master processor controller determining whether its state is normal;

A twenty step of determining, by the master processor control unit, whether the state of the master cell bus control unit is normal if its state is normal in the tenth step;

A thirtieth step in which the master processor controller determines whether the master cell bus clock controller is in a normal state when the master cell bus controller is in a normal state; And

In the thirtieth step, if the state of the master cell bus clock controller is normal, the master processor controller proceeds to the tenth step again. If the master cell bus clock controller is abnormal, the master processor controller controls the master cell. And a 40-step transition of the bus clock control unit to the stand-by state and the transition of the slave cell bus clock control unit to the active state.

1 is a functional block diagram showing an internal configuration of a cell bus and block state board redundancy apparatus according to an embodiment of the present invention;

2 is an operation flowchart showing a cell bus and block state board redundancy method according to an embodiment of the present invention;

3 is an operation flowchart showing a detailed operation of the forty-stage step (S40) of the cell bus and block state board redundancy method according to FIG.

4 is an operation flowchart showing a detailed operation of the 50th step (S50) of the cell bus and block state board redundancy method according to FIG.

FIG. 5 is an operation flowchart illustrating a detailed operation of the 60th step S60 in the cell bus and block state board duplexing method according to FIG. 2.

<Description of the symbols for the main parts of the drawings>

100: master processor control unit 200: master cell bus control unit

300: master cell bus clock control unit 400: slave processor control unit

500: slave cell bus controller 600: slave cell bus clock controller

1000: Active Processor Board 2000: Stand By Processor Board

Hereinafter, a cell bus and a block state board redundancy apparatus and method according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a functional block diagram showing a cell bus and block state board redundancy apparatus according to an embodiment of the present invention, the cell bus and block state board redundancy apparatus according to an embodiment of the present invention is a master processor control unit 100, An active processor board 1000 having a master cell bus controller 200 and a master cell bus clock controller 300, and a slave processor controller 400, a slave cell bus controller 500, and a slave cell bus clock controller ( And a stand by processor board 2000 provided with a 600.

First, the master processor control unit 100 provided in the active processor board 1000 is connected to the master cell bus control unit 200 and the slave processor control unit 400 in the stand-by processor board 2000, respectively. After checking the state of the entire active processor board 1000, the switching control signal corresponding thereto is output to the master cell bus controller 200 and the master cell bus clock controller 300.

The master cell bus controller 200 provided in the active processor board 1000 is connected to the master processor controller 100 and the master cell bus clock controller 300 and at the same time the stand-by processor board 2000. Connected to the slave cell bus control unit to control the cell bus, and after checking the state of the cell bus clock, outputs a status signal to the master processor control unit 100, and controls switching from the master processor control unit 100. When a signal is received, it serves to output it to the slave cell bus controller.

In addition, the master cell bus clock controller 300 included in the active processor board 1000 is connected to the master cell bus controller 200 and the slave cell bus clock controller 600 of the stand by processor board 2000. When the clock is supplied to the cell bus and the transfer control signal is received from the master processor bus controller 200 through the master cell bus controller 200, the clock is transmitted to the slave cell bus clock controller 600. .

The slave processor controller 400 included in the stand-by processor board 2000 is connected to the master processor controller 100 in the active processor board 1000 and the slave cell bus controller 500 in its own board. When the master processor controller 100 receives a transfer control signal from the master processor controller 100 in the master processor board 1000 when the master processor controller 100 fails in the stand-by state, the master processor controller 100 is placed in the stand-by state. At the same time, it transitions its state to the active state, and outputs various control signals to the master processor controller 100 and the slave cell bus controller 500.

In addition, the slave cell bus controller 500 included in the stand-by processor board 2000 is connected to the slave processor controller 400 and the slave cell bus clock controller 600 in its own board, and at the same time the active processor board ( Connected to the master cell bus controller 200 in the stand-by state, when the master cell bus controller 100 fails, the master cell bus controller 200 switches from the master processor bus controller 200 to the master cell bus controller 200. When the control signal is input, the master cell bus controller 200 transitions to the stand-by state and at the same time serves to transition its state to the active state.

The slave cell bus clock controller 600 provided in the stand-by processor board 2000 is connected to the slave cell bus controller 500 in its own board and the active processor controller 100 in the active processor board 1000. Connected to the master cell bus when the master cell bus clock controller 300 receives a transfer control signal through the master cell bus clock controller 300 when a failure occurs in the master cell bus clock controller 300. At the same time, the clock controller 300 transitions from the stand-by state to its active state.

Next, an operation process of the cell bus and block state board redundancy apparatus and method having the above configuration will be described with reference to FIG. 2.

First, the master processor controller 100 determines whether its state is normal (S10).

At this time, if the master processor controller 100 is in a normal state (YES) in the tenth step (S10), the master processor controller 100 determines whether the master cell bus controller 200 is normal. (S20).

If the master cell bus controller 200 is in a normal state (YES) in the twentieth step (S20), the master cell bus controller 200 determines whether the master cell bus clock controller 300 has a failure ( S30).

At this time, if the state of the master cell bus clock controller 300 is normal (YES) in the thirtieth step (S30), the master processor controller 100 proceeds to the tenth step (S10) again, When the master cell bus clock controller 300 is in an abnormal state (NO), the master processor controller 100 transitions the master cell bus clock controller 300 to the stand-by state and simultaneously the slave cell bus clock controller ( 600 transitions to the active state (S40).

Hereinafter, a detailed operation process of the above-described 40th step S40 will be described with reference to FIG. 3.

First, the master processor controller 100 receives a state signal of the master cell bus clock controller 300 from the master cell bus controller 200 (S41).

Then, the master processor control unit 100 receives the status signal for the slave cell bus clock control unit 600 from the master cell bus clock control unit 300 and then the slave cell bus clock control unit 600 is in a normal state. It is determined whether (S42).

Subsequently, when the slave cell bus clock controller 600 is in a normal state (YES) in operation 42 (S42), the master processor controller 100 transmits a clock switching control signal through the master cell bus clock controller 300. While outputting to the slave cell bus clock controller 600, the master cell bus clock controller 300 is transitioned to the standby state, while the slave cell bus clock controller 600 is transitioned to the active state (S43).

On the other hand, if the slave cell bus clock controller 600 is not in the normal state (NO) in step 42 (S42), the master processor controller 100 provides an operator with the active processor board 1000 and the stand-by processor. A message indicating that an abnormality has occurred is displayed on the board 2000 (S44).

On the other hand, if the master processor control unit 100 is not in a normal state (NO) in the tenth step (S10), the master processor control unit 100 transmits a transfer control signal to the slave processor control unit 400 by itself. The transition to the stand-by state and at the same time transitions the slave processor control unit 400 to the active state (S50).

Hereinafter, a detailed operation process of the above-described fifty step S50 will be described with reference to FIG. 4.

First, the master processor control unit 100 determines whether the state of the slave processor control unit 400 is normal (S51).

Then, if the slave processor control unit 400 is in the normal state (YES) in step 51, the master processor control unit 100 transmits a transfer control signal to the slave processor control unit 400, and at the same time it is a stand-by state. In operation S52, the slave processor controller 400 transitions to the active state.

On the other hand, if the slave processor controller 400 is not normal (NO) in the 51 st operation S51, the master processor controller 100 may provide an operator with the active processor board 1000 and the stand-by processor board ( In step S53, a message indicating that an abnormality has occurred is displayed.

On the other hand, if the master cell bus controller 200 does not have a normal state (NO) in the twentieth step S20, the master cell bus controller 200 stands the slave cell bus controller 500. At the same time, the slave cell bus controller 500 transitions to the active state (S60).

Hereinafter, a detailed operation process of the above-described sixty sixth step S60 will be described with reference to FIG. 5.

First, the master processor controller 100 receives an abnormal state signal of the master cell bus controller from the master cell bus controller 200 (S61).

Then, the master processor controller 100 determines whether the slave cell bus controller 500 is normal after receiving an abnormal state signal from the master cell bus controller 200 and before outputting a switching control signal ( S62).

Subsequently, when the slave cell bus controller 500 is in the normal state (YES) in the 62 th step S62, the master processor controller 100 controls the slave cell bus controller (200) through the master cell bus controller 200. At the same time, the transfer control signal is transmitted to the master cell bus controller 200 in the stand-by state while the slave cell bus controller 500 is transferred to the active state (S63).

On the other hand, if the slave cell bus controller 500 is not in a normal state (NO) in operation 62 (S62), the master processor controller 100 transmits to the operator the active processor board 1000 and the stand-by processor board. In operation S64, a message indicating that an abnormality has occurred is displayed.

As described above, according to the cell bus and block state board redundancy apparatus and method of the present invention, not only can stabilize the system by independently controlling and switching the blocks in the system board, but also maximizes the use of the blocks in the system board. It has an excellent effect.

Claims (10)

A master cell bus clock controller for supplying a clock to a cell bus, a master cell bus controller connected to the master cell bus clock controller for controlling the cell bus, checking a state of the cell bus clock, and outputting a result value; An active processor board having a master processor controller connected to the master cell bus controller to check its state, the master cell bus clock controller, and a state of the master cell bus controller, and output a corresponding switching control signal. ; And The slave cell bus clock, which is connected to the master cell bus clock controller and is in a stand-by state and transitions to an active state when a transfer control signal is input from a master cell bus clock controller in the master processor controller when a failure occurs in the master cell bus clock controller. A slave cell bus controller which is connected to the master cell bus controller and is in a standby state, and transitions to an active state when a transfer control signal is input from a master cell bus controller in the master processor controller when a failure occurs in the master cell bus controller; And a stand-by state connected to the master processor controller, when the master processor controller receives a transfer control signal from the master processor when a failure occurs in the master processor controller. Cell bus and block status board redundancy device comprising a stand-by processor board having a slave processor control unit performing the operation A tenth step of determining, by the master processor controller, whether its state is normal; A twenty step of determining, by the master processor control unit, whether the state of the master cell bus control unit is normal if its state is normal in the tenth step; A thirtieth step in which the master processor controller determines whether the master cell bus clock controller is in a normal state when the master cell bus controller is in a normal state; And In the thirtieth step, if the state of the master cell bus clock controller is normal, the master processor controller proceeds to the tenth step again. If the master cell bus clock controller is abnormal, the master processor controller controls the master cell. And a forty second step of translating the bus clock control unit to the stand-by state and simultaneously translating the slave cell bus clock control unit to the active state. The method of claim 2, The forty-seventh step may include the forty-first step in which the master processor controller receives an abnormal state signal of the master cell bus clock controller from the master cell bus controller; A step 42 in which the master processor controller determines whether the slave cell bus clock controller is in a normal state after receiving a status signal for the slave cell bus clock controller from the master cell bus clock controller; In step 42, when the slave cell bus clock controller is in a normal state, the master processor controller outputs a switching control signal to the slave cell bus clock controller through the master cell bus clock controller and stands the master cell bus clock controller. And a forty-third step of transitioning the slave cell bus clock controller to an active state while transitioning to a by state. The method of claim 3, wherein In step 42, if the slave cell bus clock controller is not in a normal state, the master processor controller may further include step 44 of displaying an error message to the operator indicating that an error has occurred in the active processor board and the stand-by processor board. Cellbus and block status board redundancy method characterized by. The method of claim 2, In the tenth step, if the master processor control unit is not in a normal state, the master processor control unit transmits a transfer control signal to the slave processor control unit so that it transitions to a stand-by state and simultaneously transitions the slave processor control unit to an active state. And a fifty-stage step further. The method of claim 5, The fifty-seventh step may include: the fifteenth step of determining, by the master processor controller, whether the state of the slave processor controller is normal; In step 51, when the slave processor controller is in a normal state, the master processor controller transmits a transfer control signal to the slave processor controller and at the same time transitions itself to a stand-by state while transitioning the slave processor controller to an active state. Cell bus and block status board redundancy method comprising the 52 steps. The method of claim 6, In step 51, if the slave processor controller is not normal, the master processor controller is configured to display a message indicating that an error has occurred in the active processor board and the stand-by processor board. How to duplicate bus and block status boards. The method of claim 2, In step 20, when the master cell bus controller does not have a normal state, the master processor controller transitions the master cell bus controller to the stand-by state and simultaneously transitions the slave cell bus controller to the active state. Cell bus and block status board redundancy method comprising 60 steps. The method of claim 8, In the sixty-sixth step, the master processor controller receives an abnormal state signal of the master cellbus controller from the master cellbus controller; Determining whether the slave cell bus controller is normal after the master processor controller receives the status signal from the master cell bus controller and before transmitting a transfer control signal to the slave cell bus controller; In step 62, when the slave cell bus controller is in a normal state, the master processor controller transmits a transfer control signal to the slave cell bus controller through the master cell bus controller and simultaneously moves the master cell bus controller to the standby state. And a sixty-sixth step of transitioning the slave cell bus controller to an active state while transitioning. The method of claim 9, In step 62, if the slave cell bus controller is not in a normal state, the master processor controller is configured to display a message indicating that an error has occurred in the active processor board and the stand-by processor board. Cellbus and block state board redundancy.