KR20050069351A - Method for manufacturing photo mask - Google Patents

Abstract

In the mask manufacturing method according to the present invention, in forming a plurality of cell patterns (50, 60) side by side in a repeating form with a light-shielding material on the light-transmissive substrate, the cell patterns (50, 60) are each extended in the vertical direction Formed to have a rectangular shape, and contact hole forming portions 51 and 61 extend in a direction perpendicular to the longitudinal direction in the central portion of the cell patterns 50 and 60, and the adjacent other cell patterns 60 are formed. Except for the region 52 facing the contact hole forming portion 61, the line width of the cell pattern 50 is uniformly increased by predetermined intervals b1 and b2 along the longitudinal direction to perform optical proximity compensation. It is characterized by. According to the present invention, the pattern bridge of the cell patterns 50 and 60 can be prevented even in the underexposure state, and the cell line width can be kept uniform.

Description

Method for manufacturing photo mask

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor photomask, and more particularly, a photomask capable of effectively compensating for a pattern distortion phenomenon due to an optical proximity effect on a repetitive pattern of a semiconductor cell transistor, and producing a precise line width. It relates to a manufacturing method.

The patterning technique of the photomask has a close influence on the accuracy of the actual pattern formed on the semiconductor substrate. In particular, when the degree of integration of the semiconductor pattern is very high, there is insufficient space for inserting an optical proximity correction (OPC) pattern, and a line width bridge between patterns occurs unlike the lithography original exposure intention, It is bad.

Semiconductor photolithography technology can precisely control the amount of light emitted from the photomask by elaborating the design of the photomask. In order to elaborate the design of the photomask, an optical proximity compensation (OPC) technique or a phase shifting mask technique has been introduced, and various methods for minimizing light distortion caused by the shape of the pattern drawn on the mask have been introduced. Sought. In particular, the development of chemically amplified resists with excellent photosensitivity to light of far ultraviolet wavelengths (wavelengths of 248 nm or 194 nm) has emerged and practical techniques have been developed to further increase the resolution. The technology of forming an auxiliary pattern (a kind of dummy pattern) that controls the effect also contributes to the improvement of the resolution.

In general, the photomask is formed of light blocking patterns by a light blocking material such as chromium (Cr) on the light transmissive substrate. In the photomask, a memory cell region and a logic device region form one chip. The memory cell has a regular pattern and a relatively short length. Its shape is irregular and its length is relatively long.

1 is a plan view showing a memory cell, that is, an SRAM cell portion of a conventional semiconductor mask. As shown in FIG. 1, the SRAM cell 1 has a regular pattern of cell patterns 10, and upper and lower portions of each cell pattern 10 have NMOS cells N having a minimum line width of 0.18 μm. It consists of PMOS cells (P).

FIG. 2 is a diagram illustrating a pattern form after OPC compensation of the mask of FIG. 1. In detail, FIG. 2 illustrates OPC compensation using a model simulation program based on the minimum line width of the cell pattern 10 of FIG. 1. As a result, the OPC patterns 11 and 12 in consideration of the resolution image are obtained. Is made.

At this time, the line width uniformity of the NMOS cells N1 and N2 and the PMOS cells P1 and P2 starts to collapse according to the minimum scale grid of the model simulation program. If the minimum scale scale is designed to be 10 nm, then the minimum scale interval must be determined by an integer multiple of 10 nm to avoid errors in mask manufacturing. Because of these scale criteria, some line width errors occur during OPC compensation. Due to this line width error, the line widths of the NMOS cell N1 and the PMOS cell P1 of the left cell pattern 11 are actually about 0.18 μm in FIG. 2, whereas the NMOS cells N2 and The line width of the PMOS cell P2 is about 0.185 μm, resulting in a difference in the line widths of the cell patterns 11 and 12.

3 is a view illustrating a contour image according to light intensity obtained by simulating the cell patterns 11 and 12 of FIG. 2. In FIG. 3, the contour image in the optimal exposure state is shown by the solid line 21, the dashed line 22 is the contour image in the case of underexposure than the optimal exposure state, and the broken line 23 is underexposure (standardized). About 45% of the light intensity level) represents the cantour image respectively. As shown in FIG. 3, since the line widths of the left cell pattern 11 and the right cell pattern 12 are different in the cell patterns 11 and 12 of FIG. 2, the cell on the left side in the underexposure state 23 is different. A bridge does not occur between the pattern 11 and the cell pattern 12 on the right side, but a bridge 15 occurs between the right cell pattern 12 and the cell pattern 13 disposed thereafter. do.

Meanwhile, as described above, the SRAM cell 1 is composed of one chip together with a logic device (not shown), and a product is manufactured by the same process. However, the integration degree and the step of the SRAM cell 1 are relatively higher than that of the logic element, so that the line width bias of the SRAM cell 1 is relatively increased. This acts as a cause of the relative decrease of the cell line width of the SRAM cell 1. Therefore, in order to balance the line width of the logic device, it is necessary to perform a sizing operation to increase the cell line width of the SRAM cell 1 before OPC compensation.

4 is a diagram illustrating a pattern in which the line width of the SRAM cell is increased (ie, after sizing) and then subjected to OPC compensation in order to balance the line width of the logic device. Specifically, FIG. 4 shows the result of performing OPC compensation by increasing the bias of the 0.18 μm line width in FIG. 1 by 0.01 μm on both sides. Therefore, the reference line width of the cell pattern in FIG. 4 is 0.20 µm. However, also in this case, an arithmetic error based on the scale scale reference occurs between the cell line widths, so that the line width of the NMOS cell N1 'of the left cell pattern 11' becomes 0.205 µm, and the left cell pattern 11 ' The line widths of the NMOS cell N 'and the PMOS cell P' of the PMOS cell P2 'and the right cell pattern 12' are 0.20 mu m, respectively. As such, when a difference occurs in the line widths of the cell patterns 11 ′ and 12 ′, the line widths of the logic elements may not be balanced.

FIG. 5 is a view illustrating a cantour image obtained by simulating the cell patterns illustrated in FIG. 4. As shown in FIG. 5, in the cell pattern of FIG. 4, the margin between each cell pattern 11 ′, 12 ′, and 13 ′ during underexposure is further reduced due to an increase in line width. There is a problem that a pattern bridge is generated between the left cell pattern 11 'and the right cell pattern 12' in the underexposure state 23 having a light intensity of 45%.

The present invention was developed to solve the above problems, and an object of the present invention is to provide a method of manufacturing a photomask that can prevent a pattern bridge of a memory cell and maintain a uniform cell line width.

An object of the present invention as described above, in the mask manufacturing method for forming a plurality of cell patterns side by side in a repetitive form with a light-shielding material on the light-transmissive substrate; Each of the cell patterns has a rectangular shape extending in an up and down direction, and a contact hole forming part is formed in a central portion of the cell patterns in a direction perpendicular to the longitudinal direction thereof; Except for the area facing the contact hole forming portion of another adjacent cell pattern, a mask manufacturing method comprising performing optical proximity compensation by uniformly increasing the line width of the cell pattern by a predetermined interval along the longitudinal direction. By providing.

On the other hand, the increase in the line width of the cell pattern is determined corresponding to the distance between adjacent cell patterns, it is preferable to have a value below the limit resolution.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

6 is a plan view showing a memory cell portion of a mask manufactured according to the manufacturing method of the present invention.

As shown in FIG. 6, the memory cell of the mask according to the present invention includes a plurality of cell patterns 50, 50 ′, 60, 60 ′ formed in a repetitive form on the light transmissive substrate. Each cell pattern 50, 50 ′, 60, 60 ′ is formed in a rectangular shape extending in the vertical direction, and an upper portion of each cell pattern 50, 50 ′, 60, 60 ′ is an NMOS cell N. The lower portion is composed of a PMOS cell (P). In addition, contact hole forming portions (dog bone regions) 51, 51 ′, 61 are formed in the center portion of each cell pattern 50, 50 ′, 60, 60 ′ in a direction perpendicular to the longitudinal direction of the cell pattern. have.

6 illustrates an example in which two center cell patterns 50 and 60 are repeatedly formed. That is, the memory cell according to the present invention includes a first cell pattern 50 having a relatively long length of the contact hole forming portion 51 and a second cell pattern 60 having a relatively short length of the contact hole forming portion 61. ) Is a pair formed repeatedly. Therefore, the cell pattern 50 ′ formed behind the second cell pattern 60 has the same shape as the first cell pattern 50 and the cell pattern 60 formed in front of the first cell pattern 50. ') Has the same shape as the second cell pattern 60.

In the present invention, OPC compensation of the first and second cell patterns 50 and 60 is performed by a sizing method. That is, as shown in FIG. 6, optical proximity compensation (hereinafter, referred to as OPC compensation) by increasing line widths of the first and second cell patterns 50 and 60 uniformly to the left and right by predetermined intervals b1 and b2. Is done. As such, the line widths of the NMOS cells N and PMOS cells P of the cell patterns 50 and 60 are uniformly increased, thereby effectively performing OPC compensation.

However, the line widths of the areas 52 and 62 facing the contact hole forming portions 61 and 51 'of the cell pattern on the rear side of the cell patterns 50 and 60 are not increased. That is, uniform compensation is performed on the remaining portions except for the regions 52 and 62 facing the contact hole forming portion where the bridge is likely to be generated. This selectively compensates for the line width of the memory cell, thus avoiding unnecessary OPC compensation.

Meanwhile, the increments b1 and b2 of the line widths of the NMOS cell N and the PMOS cell P are determined according to the distances D1 and D2 between adjacent cell patterns 50, 50 ′, 60 and 60 ′. . That is, the data of the cell line width for OPC compensation corresponding to the distance between the adjacent cell patterns is calculated in advance and made into a table, and then the increase amount b1, corresponding to the distances D1 and D2, in the table. b2) is selected to perform OPC compensation.

In addition, it is preferable that the increment amounts b1 and b2 of the line widths of the NMOS cell N and the PMOS cell P have a value below the limit resolution of the exposure apparatus so as not to be developed on the actual semiconductor substrate.

In the lithographic technique, the limit resolution R of the exposure apparatus which shows the dimension of the minimum pattern is determined by the following Rayleigh's Equation.

R = k λ / N.A.

Where k is a constant according to the lithography process, λ is the wavelength of the exposure source, and N.A. (Numerical Aperture) is the numerical aperture of the lens and is related to the size of the lens.

If k is 0.5 and λ is 0.248 μm (when using a light source of KrF) and NA is 0.65, substituting these values into the Rayleigh formula (Equation 1) indicates that the limit resolution (R) is approximately 0.19 μm. have. Therefore, in this case, the increments b1 and b2 of the cell line width for OPC compensation should have a value smaller than 0.19 μm. In the present embodiment, when the line widths of the NMOS cell N and the PMOS cell P are each 0.18 μm, the increase amounts b1 and b2 of the cell line width are each formed to 0.01 μm.

FIG. 7 illustrates overlapping cantour images according to light intensities obtained by simulating the cell pattern of FIG. 6. As shown in FIG. 7, as the optimal exposure 21 progresses to the underexposure 22 and 23, the overall cell line width increases, but the line widths of the NMOS cell N and the PMOS cell P are uniform along the longitudinal direction. maintain.

Also, since the region 52 facing the contact hole forming portion 61 of the second cell pattern 60 of the first cell pattern 50 has not been subjected to OPC compensation at all, the first and second cell patterns 50 60, the gaps between the first and second cell patterns 50 and 60 may not be generated even in the underexposure state 23 having 45% light intensity.

As described above, according to the present invention, since the NPC cell width and the PMOS cell line width of the memory cell can be compensated for OPC which always increases symmetrically and uniformly, the saturated drive current and the gate speed are always stable. Gate Speed) can be secured.

In addition, by maintaining the line width of the portion facing the contact hole forming portion of the adjacent cell pattern without OPC compensation, the occurrence of pattern bridges is small even during underexposure, thereby ensuring sufficient process margin.

In addition, according to the present invention, OPC compensation is performed in a manner that uniformly increases the cell line width except for an area facing the contact hole forming unit, thereby making it possible to facilitate OPC compensation.

In the above, certain preferred embodiments of the present invention have been illustrated and described. However, the present invention is not limited to the above-described embodiments, and various modifications can be made by those skilled in the art without departing from the gist of the present invention as claimed in the claims. will be.

1 is a plan view showing a portion of a memory cell as a part of a general photomask;

FIG. 2 illustrates a state after optical proximity compensation of the pattern of the memory cell of FIG. 1; FIG.

3 is a view showing a cantour image according to the intensity of intensity obtained by simulating the cell pattern of FIG.

4 is a diagram illustrating a result of performing optical proximity compensation after prematurely increasing the line width of the memory cell pattern of FIG. 1;

5 is a view showing a cantour image obtained by simulating the cell pattern of FIG.

6 is a partial plan view of a memory cell with optical proximity compensation in accordance with the present invention;

FIG. 7 is a view illustrating a cantour image obtained by simulating the cell pattern of FIG. 6. FIG.

<Explanation of symbols for the main parts of the drawings>

50: first cell pattern 51: contact hole forming portion

60: second cell pattern 62: contact hole forming portion

N: NMOS cell P: PMOS cell

b1, b2: line width increase

Claims (2)

In the mask manufacturing method for forming a plurality of cell patterns side by side in a repetitive form with a light-shielding material on a light-transmissive substrate, Each of the cell patterns 50 and 60 has a rectangular shape extending in the vertical direction, and contact hole forming parts 51 and 61 are formed at the center of the cell patterns 50 and 60 in a direction perpendicular to the longitudinal direction thereof. Is formed extended Except for the region 52 facing the contact hole forming portion 61 of another adjacent cell pattern 60, the line width of the cell pattern 50 is left and right along the longitudinal direction by predetermined intervals b1 and b2. A mask manufacturing method characterized by uniformly increasing optical proximity compensation. The method of claim 1, The increase amount (b1, b2) of the line width of the cell pattern (50) is determined corresponding to the distance between adjacent cell patterns, and has a value of less than the limit resolution.