KR20050024668A - Photomask layout used in production of semiconductor device and photomask created from the same - Google Patents

Abstract

PURPOSE: A photomask layout used in production of a semiconductor device and a photomask created thereby are provided to improve OCV(On-Chip line width Variation) and pattern fidelity by reducing selectively a grid size. CONSTITUTION: A photomask layout includes a predetermined pattern(12) to print a predetermined shape on a semiconductor substrate. The predetermined pattern includes a plurality of segments(22,24,26). The predetermined pattern includes a first pattern region(12a) having a first OPC grid size unit and a second pattern region(12b) having a second OPC grid size unit smaller than the first OPC grid size unit. Each of the first and second pattern regions is used for forming one segment.

Description

Photomask layout used in production of semiconductor device and photomask created from the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photolithography process, and more particularly, to a photomask layout in which optical proximity correction (OPC) is applied to an integrated circuit layout in an electron beam exposure apparatus for manufacturing a semiconductor device, and a photomask obtained therefrom.

As the semiconductor devices are highly integrated, the widths of the patterns formed on the semiconductor substrates and the gaps thereof are becoming smaller, and in particular, the spurs are being made to reduce the gate length. In order to form a finer pattern as described above, it is required to resolve a pattern having a dimension equal to or less than a wavelength of light used in an exposure apparatus when transferring a mask pattern from a photomask to a wafer.

In order to faithfully resolve the pattern of the line width shorter than the wavelength of light, OPC (Optical Proximity Correction) technology is a technique for correcting the shape of the mask pattern in advance by considering the deformation of the pattern on the wafer due to the optical proximity effect. This is used.

In recent years, design rules have been continuously reduced in order to reduce costs by producing more chips based on transistor performance and net die standards, and as the gate patterns become finer, gate patterns and patterns adjacent to the patterns are reduced. The space dependency of the line width of a pattern is remarkably influenced by the dimensional increase and decrease of the space between spaces, ie, the tightness of the space between patterns, and the deterioration of the line width controllability of a gate pattern becomes a problem.

The accuracy of the photomask itself is very important to meet the strict after-development (ADI) critical target (CD) targets, and mask MTT (medium to target) and CD uniformity management are becoming more stringent. .

Improving the operating speed of transistors requires a reduction in gate length and uniformity of gate length within the chip. In particular, the uniformity of the gate length can be quantified by on-chip linewidth variation (OCV), and OCV control of 10% or less of the minimum feature size is required. To improve OCV, OPC operation, which is a photomask correction operation, is performed. At this time, the OPC minimum grid size is determined according to the GDS grid size. That is, when the GDS grid size of 5 nm is set, OPC is performed only in 5 nm units, and in the 1 nm GDS grid size, OPC is performed in 1 nm units.

In general, a method for reducing the GDS grid size (OPC grid size) and the electron beam size has been taken as a method for strict management of mask MTT and CD uniformity. Until now, only the method of setting the grid size in the entire photomask area as a method for reducing the GDS grid side has been considered. However, the method of applying the reduction of the grid size to the entire mask increases the manufacturing cost of the mask, which not only increases the manufacturing cost of the device but also requires a great amount of capital and time. In addition, since the mask data volume increases in proportion to the square of the grid size reduction amount, throughput decreases in the mask manufacturing process, and as a result, it is very disadvantageous in the long term such as mass production and feedback time.

The present invention is to solve the above problems in the prior art, to provide a photomask layout that can facilitate the MTT control and improve the CD uniformity.

Another object of the present invention is to provide a photomask that can contribute to OCV improvement and pattern fidelity improvement.

In order to achieve the above object, the photomask layout according to the present invention includes a predetermined pattern divided into a plurality of segments for transferring to a predetermined shape on the semiconductor substrate. The predetermined pattern includes a first pattern area having a first OPC grid size unit and a second pattern area having a second OPC grid size unit smaller than the first OPC grid size.

The first pattern region and the second pattern region each constitute one segment.

Preferably, the predetermined pattern is a gate pattern for forming a gate electrode on the semiconductor substrate. Also preferably, the predetermined pattern constitutes a line and space pattern.

In order to achieve the above another object, the photomask according to the present invention includes the predetermined pattern formed on the transparent substrate based on the photomask layout to transfer the predetermined pattern onto the semiconductor substrate by an exposure process. The photomask layout includes a first pattern region constituting a part of the predetermined pattern and having a first OPC grid size unit, and a second OPC grid size unit constituting another part of the predetermined pattern and smaller than the first OPC grid size. It includes a second pattern region having a.

The second pattern may be configured as a pattern corrected by an OPC technique in units of the second OPC grid size.

The exposure process is performed by a variable shape beam (VSB) electron beam exposure apparatus or a raster scan electron beam exposure apparatus.

The photomask layout according to the present invention does not reduce the grid size in the entire area of the photomask, but selectively reduces the OPC grid size in areas requiring strict mask MTT and CD uniformity control, such as in a specific pattern, for example, a gate pattern, to allow OCV. And improve pattern fidelity. According to the present invention, since the number of segments is the same as in the conventional layout, the cost of manufacturing the photomask is not increased even when using a VSB type exposure apparatus, and the pattern fidelity in the photomask is improved without additional cost increase in the mask manufacturing process. The degree of OPC can be performed in more detail.

Next, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a photomask layout according to a preferred embodiment of the present invention.

Referring to FIG. 1, the photomask layout 10 according to the present invention includes a predetermined pattern 12 divided into a plurality of segments 22, 24, and 26 in order to transfer a predetermined shape onto a semiconductor substrate. Include.

The first pattern region 12a constituting some segments 22 and 26 of the plurality of segments 22, 24, and 26 constituting the pattern 12 may be a grid of a first OPC grid size unit, for example, 5 nm. It has a size unit. In addition, the second pattern area 12b constituting the other partial segment 24 of the plurality of segments 22, 24, and 26 has a second OPC grid size unit smaller than the first OPC grid size unit. FIG. 1 illustrates a case in which the second pattern 12b is formed to have a grid size unit of 1 nm.

The first pattern region 12a and the second pattern region 12b are each composed of one segment unit, and the second pattern region 12b has a smaller OPC grid size than that of other pattern regions. The number of segments for forming 12 does not increase.

The pattern 12 may be advantageously applied to form a gate pattern for forming a gate electrode on the semiconductor substrate. A pattern region set to have a smaller grid size than other pattern regions as in the second pattern region 12b may have a great effect on OCV improvement, particularly when forming a line and space pattern.

The photomask layout according to the present invention is applicable to both a variable shape beam (VSB) electron beam exposure process and a raster scan electron beam exposure process.

In the case of fabricating a photomask based on the photomask layout as shown in FIG. 1, since the grid size is selectively set to only a pattern area requiring pattern fidelity partially among the patterns to be transferred, in the layout design process No additional design is required, and when the VSB type exposure apparatus is used, the number of segments constituting the pattern does not increase, so writing time does not increase significantly. In other words, the OPC of the line-and-space pattern can be finely executed without greatly increasing the mask writing time. Therefore, improvement of OCV and improvement of pattern fidelity can be expected.

A photomask fabricated to transfer a predetermined pattern onto a semiconductor substrate by an exposure process based on the photomask layout shown in FIG. 1 includes a predetermined pattern formed on a transparent substrate corresponding to the pattern 12 shape. do. At this time, a portion of the predetermined pattern corresponding to the second pattern 12b is corrected by an OPC technique by the second OPC grid size unit, for example, a grid size unit of 1 nm as illustrated in FIG. 1. It may consist of a true pattern.

The predetermined pattern may form a gate pattern for forming a gate electrode on the semiconductor substrate. In particular, in the case where the predetermined pattern constitutes a line-and-space pattern, when using a photomask fabricated based on the photomask layout according to the present invention, MTT control in a pattern formed on a semiconductor substrate is easy and CD uniformity is achieved. Can improve.

Currently, there are two types of exposure methods for photomask manufacturing, a raster scan method and a VSB method. Among them, the VSB method is known to have excellent characteristics in terms of pattern fidelity and throughput. The VSB method is a method of dividing a segment into an appropriate shape according to a mask layout shape and then recording according to each segment shape. Most of the time required for recording depends on the number of segments. The raster scan method is a method of recording an entire pattern with an electron beam source of a constant size regardless of the number of segments, and has a characteristic proportional to the total area.

In the construction of the photomask layout according to the present invention, OPC is performed by reducing the grid size by using the advantages of the VSB method, but the number of segments is not increased. Control effect can be obtained. Therefore, the configuration of the photomask layout according to the present invention can be advantageously applied to the OPC process in the gate pattern which requires CD accuracy in the line and space pattern, and can have a great effect on OCV improvement.

The photomask layout according to the present invention is to set the grid size smaller in the other pattern area only in some pattern areas while using the existing layout as it is, and there is no additional layout change. In addition, in the case of using the VSB type exposure apparatus, the number of segments does not increase, and thus the recording time does not increase significantly.

2 is a graph evaluating the proximity effect characteristics according to the pattern pitch for each OPC grid size.

In FIG. 2, the degree of OCV improvement obtained by only changing the grid size during photomask fabrication was measured. In FIG. 2, when there is no correction by the OPC technique, the same result as indicated by “Original” is shown in FIG. 2. On the other hand, if the correction is performed by the OPC technique, a relatively uniform CD can be obtained. However, as can be seen in Figure 2, CD uniformity varies depending on the grid size. That is, when the grid size is set to 1 nm, the CD uniformity is more excellent than when the grid size is set to 5 nm. In FIG. 2, when the grid size is set to 1 nm, the result is obtained from a layout manufactured as in the second pattern region 12a of FIG. 1, and when the grid size is set to 5 nm, all pattern regions, i. This is the case when the layout is made by setting all segments to the same grid size, that is, 5 nm grid size.

As a result of the evaluation as shown in FIG. 2, the proximity effect characteristics of the 156 nm CD (nominal CD) for the 1 nm grid size compared to the 5 nm grid size were 18.8 nm and 12.3 nm based on the 3σ. A% improvement was obtained.

The photomask layout according to the present invention does not reduce the grid size in the entire area of the photomask, but selectively reduces the OPC grid size in areas requiring strict mask MTT and CD uniformity control, such as in a specific pattern, for example, a gate pattern, to allow OCV. And improve pattern fidelity.

In manufacturing a photomask based on the photomask layout according to the present invention, since the OPC of the line-and-space pattern can be performed more precisely without a large increase in the mask writing time, the OCV can be improved. In addition, by selectively applying a small grid size to a pattern area partially requiring pattern fidelity, the mask data volume is not greatly increased. In addition, since the number of segments is the same as in the conventional layout and does not increase separately, it does not increase the cost of manufacturing the photomask even when using the VSB type exposure apparatus, and advantageously when using the raster scan type exposure apparatus. Can be applied. That is, even in the mask manufacturing process, the pattern fidelity in the photomask can be improved without additional cost increase, and the degree of OPC can be performed more precisely.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes by those skilled in the art within the scope of the technical idea of the present invention. This is possible.

1 is a photomask layout according to a preferred embodiment of the present invention.

Figure 2 is a graph showing the degree of OCV improvement compared to the case of the prior art when using a photomask manufactured based on the photomask layout according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10: photomask layout, 12: pattern, 12a: first pattern region, 12b: second pattern region, 22, 24, 26: segment.

Claims (11)

A predetermined pattern divided into a plurality of segments for transferring to a predetermined shape on the semiconductor substrate, The predetermined pattern includes a first pattern region having a first OPC grid size unit, and a second pattern region having a second OPC grid size unit smaller than the first OPC grid size. The method of claim 1, And the first pattern region and the second pattern region each constitute one segment. The method of claim 1, And the predetermined pattern is a gate pattern for forming a gate electrode on the semiconductor substrate. The method of claim 1, And the predetermined pattern constitutes a line and space pattern. Including the predetermined pattern formed on the transparent substrate based on the photomask layout to transfer the predetermined pattern onto the semiconductor substrate by an exposure process, The photomask layout is A first pattern region constituting a part of the predetermined pattern and having a first OPC grid size unit; And a second pattern region constituting another portion of the predetermined pattern and having a second OPC grid size unit smaller than the first OPC grid size. The method of claim 5, The predetermined pattern is divided into a plurality of segments, And the first pattern region and the second pattern region each constitute one segment. The method of claim 5, And the predetermined pattern is a gate pattern for forming a gate electrode on the semiconductor substrate. The method of claim 5, The predetermined pattern constitutes a line and space pattern. The method of claim 5, The second pattern is a photomask, characterized in that the pattern is corrected by the OPC technique in units of the second OPC grid size. The method of claim 5, The exposure process is a photomask, characterized in that made by a variable shape beam (VSB) electron beam exposure apparatus. The method of claim 5, The exposure process is a photomask, characterized in that made by the raster scan electron beam exposure apparatus.