KR20050069326A - Method for fabricating tungsten plug of semiconductor device - Google Patents
Method for fabricating tungsten plug of semiconductor device Download PDFInfo
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- KR20050069326A KR20050069326A KR1020030101305A KR20030101305A KR20050069326A KR 20050069326 A KR20050069326 A KR 20050069326A KR 1020030101305 A KR1020030101305 A KR 1020030101305A KR 20030101305 A KR20030101305 A KR 20030101305A KR 20050069326 A KR20050069326 A KR 20050069326A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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Abstract
본 발명은 콘택 홀에 증착되는 텅스텐의 양을 최소화하고 구리와 텅스텐을 콘택 홀에 동시에 매립하는 방법에 관한 것이다.The present invention is directed to a method of minimizing the amount of tungsten deposited in a contact hole and simultaneously embedding copper and tungsten in the contact hole.
본 발명의 반도체 소자의 콘택 홀 매립방법은 반도체 소자의 콘택 홀 매립방법에 있어서, 반도체 기판 상에 형성된 소정의 층간 절연막을 선택 식각하여 콘택홀을 형성하는 단계; 상기 형성된 콘택홀에 배리어 금속층을 증착하는 단계; 상기 배리어 금속층이 증착된 콘택홀에 텅스텐을 매립하고 평탄화 공정을 수행하는 단계; 상기 매립된 텅스텐을 에치백 공정으로 배리어 금속층과의 식각율을 제어하면서 소정의 두께로 식각하는 단계; 및 상기 식각된 텅스텐 상부에 구리를 증착하여 콘택홀을 매립하는 단계로 이루어짐에 기술적 특징이 있다.According to an aspect of an exemplary embodiment, a method of filling a contact hole in a semiconductor device may include: forming a contact hole by selectively etching a predetermined interlayer insulating layer formed on a semiconductor substrate; Depositing a barrier metal layer in the formed contact hole; Embedding tungsten in the contact hole on which the barrier metal layer is deposited and performing a planarization process; Etching the buried tungsten to a predetermined thickness while controlling the etch rate with the barrier metal layer by an etch back process; And depositing copper on the etched tungsten to fill up the contact hole.
따라서, 본 발명의 반도체 소자의 콘택 홀 매립방법은 콘택 홀에 매립되는 텅스텐의 양을 최소한으로 줄여 콘택의 저항을 줄임으로써 반도체 소자의 성능을 향상시킬 수 있다.Therefore, the contact hole filling method of the semiconductor device of the present invention can improve the performance of the semiconductor device by reducing the resistance of the contact by reducing the amount of tungsten buried in the contact hole to a minimum.
Description
본 발명은 반도체 소자의 콘택 홀 매립방법에 관한 것으로, 보다 자세하게는 금속배선 공정 중 저항값이 비교적 높은 텅스텐의 두께를 최소화하여 콘택 홀에 배선 금속과 텅스텐을 동시에 매립함으로써 콘택의 저항을 줄인 콘택 홀 형성방법에 관한 것이다. The present invention relates to a method of filling a contact hole in a semiconductor device, and more particularly, to minimizing the thickness of a tungsten having a relatively high resistance value during a metal wiring process, thereby simultaneously filling a contact metal and tungsten in the contact hole, thereby reducing contact resistance. It relates to a formation method.
종래의 반도체 소자의 금속배선 형성방법은 도 1을 참조하여 개략적으로 설명한다.A conventional method for forming metal wirings of a semiconductor device will be described with reference to FIG. 1.
먼저 반도체 소자가 형성된 실리콘웨이퍼나 하부 금속 배선층 등의 하부 도전막과 상부 금속 배선층을 전기적으로 절연하기 위해 증착된 층간 절연막(IMD : Inter-Metal Dielectric)을 선택적으로 패터닝(patterning)하여 하부 도전막의 일부가 드러나도록 콘택(contact) 홀 또는 비아(via)를 형성한 다음, 콘택 홀 또는 비아 홀이 형성된 층간 절연막 전면에 스퍼터링(sputtering) 방법에 의해 배리어(barrier) 금속막으로 티타늄/티타늄나이트라이드(Ti/TiN) 박막(101)을 증착한다. 그리고, 티타늄/티타늄나이트라이드 박막이 형성된 층간 절연막 전면에 블랑켓(blanket) 텅스텐 화학 기상 증착(chemical vapor deposition, CVD) 방법으로 텅스텐 박막(102)을 증착하여 콘택 홀 또는 비아 홀이 텅스텐 박막으로 완전히 매립되도록 한다. 이후, 배리어 금속막의 티타늄나이트라이드 박막을 식각 정지막으로 SF6 가스를 에천트(etchant)로 한 플라즈마 텅스텐 에치백(etchback) 공정을 실시하고, 이후 세정 공정을 거쳐 구리, 알루미늄을 포함하는 금속 배선(103)을 형성한다.First, a part of the lower conductive layer is selectively patterned by interposing an interlayer insulating layer (IMD: Inter-Metal Dielectric) deposited to electrically insulate the lower conductive layer such as a silicon wafer or lower metal interconnection layer on which the semiconductor device is formed and the upper metal interconnection layer. Contact holes or vias are formed to be exposed, and then titanium / titanium nitride (Ti) is formed as a barrier metal film by sputtering on the entire surface of the interlayer insulating film on which the contact holes or via holes are formed. / TiN) thin film 101 is deposited. In addition, the tungsten thin film 102 is deposited on the entire surface of the interlayer insulating film on which the titanium / titanium nitride thin film is formed by blanket tungsten chemical vapor deposition (CVD) to completely contact or via holes with the tungsten thin film. Allow to landfill. Subsequently, a plasma tungsten etchback process is performed by using the titanium nitride thin film of the barrier metal film as an etch stop layer and an SF 6 gas as an etchant, and thereafter, a metal wiring including copper and aluminum is subjected to a cleaning process. 103 is formed.
상기의 콘택 플러그를 형성하는 텅스텐은 고용점의 내열 금속으로 실리콘과의 열적 안정성이 우수하며, 접촉 저항 특성이 비교적 좋기 때문에 단차 피복성(step coverage)을 개선하기 위하여 사용되고 있다.Tungsten forming the contact plug is a heat-resistant metal of a solid solution and is used to improve step coverage because of excellent thermal stability with silicon and relatively good contact resistance characteristics.
그러나, 상기의 텅스텐은 표 1에 나타낸 바와 같이 구리나 알루미늄에 비하여 저항값이 4배 가량 높기 때문에 소자의 크기가 작아질수록 소자의 성능을 낮추는 요인으로 작용하는 문제점이 있다.However, since the tungsten is 4 times higher in resistance as compared to copper or aluminum, as shown in Table 1, there is a problem in that the smaller the size of the device, the lower the performance of the device.
따라서, 본 발명은 상기와 같은 종래 기술의 제반 단점과 문제점을 해결하기 위한 것으로, 텅스텐 콘택 플러그의 양을 최소한으로 줄이고 콘택에 금속배선과 텅스텐을 동시에 매립함으로써 콘택 저항을 줄여 향상된 반도체 소자의 성능을 향상시킨 반도체 소자의 콘택 홀 매립방법을 제공함에 본 발명의 목적이 있다. Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, and to improve the performance of the semiconductor device by reducing the contact resistance by minimizing the amount of the tungsten contact plug and at the same time buried metal wiring and tungsten in the contact. It is an object of the present invention to provide an improved contact hole filling method for a semiconductor device.
본 발명의 상기 목적은 반도체 소자의 콘택 홀 매립방법에 있어서, 반도체 기판 상에 형성된 소정의 층간 절연막을 선택 식각하여 콘택홀을 형성하는 단계; 상기 형성된 콘택홀에 배리어 금속층을 증착하는 단계; 상기 배리어 금속층이 증착된 콘택홀에 텅스텐을 매립하고 평탄화 공정을 수행하는 단계; 상기 매립된 텅스텐을 에치백 공정으로 배리어 금속층과의 식각율을 제어하면서 소정의 두께로 식각하는 단계; 및 상기 식각된 텅스텐 상부에 구리를 증착하여 콘택홀을 매립하는 단계로 이루어진 반도체 소자의 콘택 홀 매립방법에 의해 달성된다.According to an aspect of the present invention, there is provided a method of filling a contact hole in a semiconductor device, the method comprising: forming a contact hole by selectively etching a predetermined interlayer insulating layer formed on a semiconductor substrate; Depositing a barrier metal layer in the formed contact hole; Embedding tungsten in the contact hole on which the barrier metal layer is deposited and performing a planarization process; Etching the buried tungsten to a predetermined thickness while controlling the etch rate with the barrier metal layer by an etch back process; And filling a contact hole by depositing copper on the etched tungsten.
본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.
도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 콘택 홀 형성방법을 나타낸 공정도이다.2A to 2C are process diagrams illustrating a method for forming contact holes in a semiconductor device according to the present invention.
우선, 도 2a는 반도체 소자가 형성된 실리콘 웨이퍼나 하부 금속 배선층 등의 하부 도전막과 상부 금속 배선층을 전기적으로 절연하기 위해 증착된 층간절연막을 선택적으로 패터닝하여 하부 도전막의 일부가 드러나도록 콘택 홀(200)을 형성한 것을 나타낸 것이다.First, FIG. 2A illustrates a contact hole 200 to selectively expose a portion of a lower conductive layer by selectively patterning an interlayer insulating layer deposited to electrically insulate a lower conductive layer such as a silicon wafer or a lower metal interconnection layer on which a semiconductor device is formed and an upper metal interconnection layer. ) Is formed.
다음, 도 2b와 같이 콘택 홀이 형성된 층간 절연막 전면에 스퍼터링(sputtering) 방법에 의해 배리어 금속층으로 탄탈나이트라이드/탄탈 (TaN/Ta) 박막(201)을 150±10Å/150±10Å의 두께로 증착한다. 이 때 배리어 금속층을 기존의 티타늄/티타늄나이트라이드를 사용하게 되면 금속배선으로 구리를 사용할 경우 구리가 산화막 안으로 침투되어 신뢰성 문제를 발생시킬 수 있다. 그리고, 상기 배리어 금속층의 전면에 화학 기상 증착법 등으로 텅스텐 박막(202)이 콘택 홀에 완전히 매립되도록 하고 평탄화 공정을 실시한다. Next, a tantalum nitride / tantalum (TaN / Ta) thin film 201 is deposited to a thickness of 150 ± 10Å / 150 ± 10Å by a sputtering method on the entire surface of the interlayer insulating film on which the contact hole is formed as shown in FIG. 2B. do. At this time, if the barrier metal layer uses the existing titanium / titanium nitride, copper may penetrate into the oxide layer and cause reliability problems when copper is used as the metal wiring. The tungsten thin film 202 is completely buried in the contact hole by a chemical vapor deposition method and the like on the entire surface of the barrier metal layer, and a planarization process is performed.
이후, 도 2c에 나타낸 공정과 같이 배리어 금속층의 탄탈을 식각 정지막으로 한 후 SF6 가스를 에천트로 하여 플라즈마 텅스텐 에치백 공정을 실시한다.Thereafter, as shown in FIG. 2C, a plasma tungsten etchback process is performed by using tantalum of the barrier metal layer as an etch stop layer and using SF 6 gas as an etchant.
에치백 공정은 좀더 상세하게는 고밀도 플라즈마 챔버에서 압력을 200 내지 220mTorr로 유지시킨 다음, 250 내지 675W의 파워를 인가한다. 반응 가스로는 아르곤(Ar) 가스와 SF6 가스를 각각 70 내지 120sccm, 120 내지 150sccm 정도를 주입하여 배리어 금속층의 하부 탄탈막이 드러나는 시점까지 텅스텐을 에치백한다. 이때 아르곤 가스는 반응 가스인 SF6 가스를 활성화시키는 역할을 한다.The etch back process more particularly maintains the pressure at 200-220 mTorr in a high density plasma chamber and then applies a power of 250-675W. As the reaction gas, 70 to 120 sccm and 120 to 150 sccm of argon (Ar) gas and SF 6 gas are respectively injected to etch back tungsten until the lower tantalum layer of the barrier metal layer is exposed. At this time, the argon gas serves to activate the SF 6 gas which is a reaction gas.
여기에서 텅스텐이 식각되는 속도와 배리어 금속층이 식각되는 속도가 다른 점에 착안하여 탄탈이 드러나는 시점까지 텅스텐을 에치백하여 콘택 홀에 매립되는 텅스텐의 양을 조절한다.Here, the speed at which tungsten is etched differs from the speed at which the barrier metal layer is etched, and the amount of tungsten embedded in the contact hole is adjusted by etching back tungsten until the tantalum is exposed.
실시예로 식각율을 예로 들면 다음과 같다.As an example, the etching rate is as follows.
챔버의 압력이 220mTorr, RF 파워 675W가 인가된 경우 SF6 가스를 120sccm으로, 아르곤 가스를 120sccm 으로 주입하게 되면 텅스텐의 식각 속도는 4000±300Å/min이고, 탄탈나이트라이드/탄탈의 식각 속도는 40Å/min 이하이다.When the chamber pressure is 220mTorr and RF power 675W is applied, SF 6 gas is injected at 120sccm, argon gas is injected at 120sccm, and the etching speed of tungsten is 4000 ± 300Å / min, and the etching rate of tantalum nitride / tantalum is 40Å / min or less.
또 챔버의 압력이 220mTorr, RF 파워 270W가 인가된 경우 SF6 가스를 70sccm으로, 아르곤 가스를 150sccm 으로 주입하게 되면 텅스텐의 식각 속도는 1600±200Å/min이고, 탄탈나이트라이드/탄탈의 식각 속도는 16Å/min 이하가 된다.When the chamber pressure is 220mTorr and RF power 270W is applied, SF 6 gas is injected into 70sccm, argon gas is injected into 150sccm, and the etching speed of tungsten is 1600 ± 200Å / min, and the etching speed of tantalum nitride / tantalum is 16 Å / min or less.
즉, 배리어 금속층의 두께에 따라 식각되는 텅스턴의 양을 조절할 수 있다.That is, the amount of tungsten to be etched can be adjusted according to the thickness of the barrier metal layer.
마지막으로 도 2d와 같이 텅스턴 플러그 상부에 구리 또는 알루미늄 배선 금속을 증착하고 평탄화 공정을 실시하여 콘택 홀에 텅스텐과 배선 금속을 동시에 매립한다.Finally, as shown in FIG. 2D, copper or aluminum wiring metal is deposited on the tungsten plug and the planarization process is performed to simultaneously embed tungsten and the wiring metal in the contact hole.
본 발명은 이상에서 살펴본 바와 같이 바람직한 실시예를 들어 도시하고 설명하였으나, 상기한 실시 예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능할 것이다.The present invention has been shown and described with reference to the preferred embodiments as described above, but is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.
따라서, 본 발명의 반도체 소자의 콘택 홀 매립방법은 텅스텐 콘택 플러그의 양을 최소한으로 줄이고 콘택에 금속배선과 텅스텐을 동시에 매립함으로써 소자의 집적화와 저전력에서 빠른 처리속도가 요구되는 반도체 소자의 콘택 저항을 개선시킬 수 있는 효과가 있다.Therefore, the contact hole filling method of the semiconductor device of the present invention minimizes the amount of tungsten contact plugs and simultaneously embeds metal wires and tungsten in the contacts, thereby reducing the contact resistance of the semiconductor devices requiring device integration and high processing speed at low power. There is an effect that can be improved.
도 1은 종래 기술에 의한 반도체 소자 콘택 홀 구조를 나타낸 단면도.1 is a cross-sectional view showing a semiconductor device contact hole structure according to the prior art.
도 2a 내지 도 2d는 본 발명에 의한 반도체 소자의 콘택 홀 형성방법을 나타낸 공정도.2A to 2D are process charts showing a method for forming a contact hole in a semiconductor device according to the present invention.
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| KR1020030101305A KR100580793B1 (en) | 2003-12-31 | 2003-12-31 | Method for fabricating tungsten plug of semiconductor device |
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