KR20050065970A - Optic sensor, and liquid crystal display having the same - Google Patents

Abstract

Disclosed are a light sensor simplified and a liquid crystal display having the same to prevent a decrease in aperture ratio. One end of the storage capacitor is connected to the first power supply voltage. The first current electrode of the photosensitive device is connected to the other end of the storage capacitor and, as an active signal is applied through the control electrode, stores photo leakage charge in the storage capacitor corresponding to light that is activated and applied from the outside, and the control electrode As the selection signal is applied through the controller, the stored photo leakage charge is output through the second current electrode. Accordingly, by implementing the optical sensor with one thin film transistor and one storage capacitor, it is possible to prevent the aperture ratio of the liquid crystal display from being lowered.

Description

Optical sensor and liquid crystal display having the same {OPTIC SENSOR, AND LIQUID CRYSTAL DISPLAY HAVING THE SAME}

The present invention relates to an optical sensor and a liquid crystal display having the same. More particularly, the present invention relates to a simplified optical sensor and a liquid crystal display having the same in order to prevent a decrease in aperture ratio.

In general, the optical sensor detects a corresponding position in response to light input from the outside. In particular, the liquid crystal display panel employing the above-described optical sensor is a number of optical, as published in the paper published in the 2003 SID conference paper by Willem den Boer et al. As Active Matrix LCD with Integrated Optical Touch Screen. The sensors are arranged in a matrix type and used for operation of a fingerprint recognition function or a touch panel function by generating position information corresponding to the position of external light.

1 is an equivalent circuit diagram of an optical sensor employed in a general array substrate. In particular, the optical sensor formed in the unit pixel area of the liquid crystal display panel is shown.

Referring to FIG. 1, a liquid crystal display panel having a general optical sensor includes a first switching element Q1 connected between a plurality of gate lines GL, a plurality of data lines DL, a gate line GL, and a data line DL. ), A liquid crystal capacitor CLC connected to the first switching element Q1, and a first storage capacitor CST1. In addition, the first power line VL1, the second power line VL2, a second switching element TS1 for detecting the intensity of the external light and converting the charge into a charge, and storing the charge provided from the second switching element TS1. And a second switching capacitor CST2, a third switching element TS2 for outputting charges stored in the second storage capacitor CST2, and a read out line ROL. The second switching element TS1, the second storage capacitor CST2, and the third switching element TS2 operate as a kind of optical sensor.

Then, look at the operation of the optical sensor as follows.

First, when external light is incident on the second switching element TS1, a negative voltage is applied to the first power line VL1 connected to the gate electrode of the second switching element TS1, and the second switching element TS1 is applied. The second switching element TS1 is turned off by applying a positive voltage to the second power line VL2 connected to the drain electrode. Then, in the second switching element TS1 to which external light is incident, a light leakage current having a considerable magnitude is generated as compared with the third switching element TS2 to which external light is not incident.

The photo-leakage current generated as described above charges the second storage capacitor CST2 when the third switching element TS2 is not turned on, and the charge charged in the second storage capacitor CST2 is charged. 3 is maintained until the switching element TS2 is turned on.

As the high level gate signal is applied to the next gate line GQ + 1 connected to the gate electrode of the third switching element TS2, the charges charged in the second storage capacitor CST2 are transferred to the third switching element. It is output to the readout circuit unit (not shown) along the readout line ROL via TS2.

As such, the optical sensor is employed in a liquid crystal display panel, particularly an array substrate, which performs a display function to perform a light sensing function.

However, the optical sensor is limited in the design position because there is not enough space to be located in the area defining the unit pixel of the array substrate.

In particular, when the above-described optical sensor is used in a transmissive liquid crystal display or a reflection-transmissive liquid crystal display, there is a problem of reducing the aperture ratio, and since two thin film transistors and one capacitor are formed, the yield is reduced by increasing the defective rate. There is a problem that causes signal interference by a plurality of devices designed in the pixel area.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide an optical sensor with a simplified structure in order to prevent a decrease in aperture ratio and to reduce yield and signal interference due to an increase in defective rate. It is.

Another object of the present invention is to provide a liquid crystal display device having the above optical sensor.

An optical sensor according to one aspect for realizing the object of the present invention includes a storage capacitor having one end connected to a first power supply voltage; And a first current electrode connected to the other end of the storage capacitor, and as an active signal is applied through a control electrode, the light leakage charge corresponding to light that is activated and applied from the outside is stored in the storage capacitor, and the control electrode As the selection signal is applied through, the light sensing device outputs the stored photo leakage charge through the second current electrode.

In addition, a liquid crystal display device for realizing another object of the present invention described above comprises: a plurality of first scan lines for transmitting a first scan signal; A plurality of data lines carrying data signals; A pixel unit displaying an image corresponding to the data signal in response to the first scan signal; A plurality of second scan lines; Multiple lead out lines; And storing the light leakage charge corresponding to the light applied from the outside as the active signal is applied through the second scan line, and storing the stored light leakage charge as the selection signal is applied through the second scan line. It includes an optical sensor unit for outputting through the lead out line.

According to the optical sensor and the liquid crystal display having the same, by implementing the optical sensor with one thin film transistor and one storage capacitor, it is possible to prevent the aperture ratio of the liquid crystal display from being lowered.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

FIG. 2 is an equivalent circuit diagram illustrating an optical sensor according to an exemplary embodiment of the present invention. In particular, FIG. 2 illustrates an optical sensor formed in a unit pixel area of a liquid crystal display panel, and only one unit pixel is illustrated for convenience of description.

2, a liquid crystal display panel having an optical sensor according to an exemplary embodiment of the present invention includes a gate line GL, a data line DL, a switching element Q1, a liquid crystal capacitor CLC, and a first storage capacitor. CST1, a first power line VL1, a second power line VL2, a photosensitive device Q2, a second storage capacitor CST2, and a read out line ROL.

The gate line GL extends in the horizontal direction, transmits the gate signal GQ to the switching element Q1, and the data line DL extends in the vertical direction, and transmits the data signal DP to the switching element Q1. To pass on.

The switching element Q1 is formed in an area defined by the gate lines GL and the data lines DL adjacent to each other, so that the source is connected to the data line DL, and the gate is connected to the gate line GL. Connected. As the high level gate signal GQ is applied to the gate line GL, the switching element Q1 is activated, and the liquid crystal capacitor CLC and the first storage capacitor CST1 are drained through the data signal DP. Output to

One end of the liquid crystal capacitor CLC is connected to the drain of the switching element Q1, the other end thereof is connected to the common electrode voltage VCOM, and stores the data signal DP provided through the drain.

One end of the first storage capacitor CST1 is connected to the drain of the switching element Q1, and the other end thereof is connected to the storage voltage VST. The first storage capacitor CST1 stores the data signal DP provided through the drain, and the switching element Q1 is turned off to gradually discharge the charge charged in the liquid crystal capacitor CLC. As a result, the stored charge is provided to the liquid crystal capacitor CLC. The first storage capacitor CST1 defines a kind of pixel part by a combination of the switching element Q1 and the liquid crystal capacitor CLC.

The first power line VL1 extends in the horizontal direction, provides an active signal provided from the outside to the photosensitive device Q2, and then provides a selection signal to the photosensitive device Q2, and the second power line VL2. ) Extends in the horizontal direction to provide a second power supply voltage supplied from the outside to the second storage capacitor CST2.

The active signal is a signal for storing optical leakage charges corresponding to light applied from the outside in a second storage capacitor, and the selection signal is a signal for outputting the stored optical leakage charges through a read-out line ROL. . Preferably, the active signal is applied during the first frame period, and the selection signal is applied during the second frame period. If the first frame is an odd frame, the second frame is an even frame, and if the first frame is an even frame, the second frame is an odd frame. The second power supply voltage is a DC level, which shows a ground level in the drawing.

The photosensitive device Q2 is formed in a region defined by the first power line VL1 and the second power line VL2, a drain is connected to the second storage capacitor CST2, and a gate is connected to the first power line. Is connected to VL1, and a source is connected to the lead out line ROL. As the external light is incident through the channel region, the photosensitive device Q2 provides a photo current to the readout line ROL through a source. The photocurrent is a kind of light sensing signal and is information corresponding to the corresponding position.

One end of the second storage capacitor CST2 is connected to the drain of the photosensitive device Q2, and the other end thereof is connected to the second power line VL2. The second storage capacitor CST2 charges a charge corresponding to the photocurrent provided through the drain. The photosensitive device Q2 and the second storage capacitor CST2 define a kind of optical sensor, and will be described in more detail later with reference to FIGS. 3A and 3B.

The lead-out line ROL extends in the vertical direction, and outputs a photocurrent output through the source of the photosensitive element Q2 as an optical sensing signal to an external driving IC (not shown). The photo-sensing signal is an off-current present in the turn-off region of the photo-sensing element Q2. Since the signal level is weak, a separate amplifier or the end of the lead-out line ROL is used. It is preferable to further provide a noise filter.

In the above description, the first power supply line VL1, the second power supply line VL2, the photosensitive device Q2, and the lead-out line ROL are formed in the unit pixel of the liquid crystal display panel. The line VL1, the second power line VL2, the light sensing element Q2, and the lead out line ROL may be formed on a separate substrate to define a pattern recognition panel. The panel recognition panel is provided on the liquid crystal display panel and used as a predetermined touch panel, fingerprint recognition panel, or the like.

FIG. 3A is a view for explaining an optical sensor unit according to the present invention, and FIG. 3B is a waveform diagram for explaining the operation of the optical sensor unit shown in FIG. 3A. In the drawing, one end and the other end of the second storage capacitor are respectively applied to the first and second nodes NA and NB, and voltages applied to the first and second nodes NA and NB are respectively referred to. (VNA, VNB), and the gate and the source of the photosensitive device to the third and fourth nodes (NC, ND), the voltage applied to each of the third and fourth nodes (NC, ND) and the third and This is referred to as fourth node voltage VNC, VND.

3A and 3B, the voltage VDlow corresponding to the lowest value of the fourth node voltage VND is continuously applied to the first node NA.

In the reset period, when the high level third node voltage VNC is applied to the third node NC, the photosensitive device Q2 is turned on so that the charge charged in the second storage capacitor CST2 is discharged. The second node voltage VNB sensed by the second node NB and the fourth node voltage VND sensed by the fourth node ND are the same as the voltage VDlow corresponding to the lowest value of the fourth node voltage VND. .

In the charging period, when the low level third node voltage VNC is applied to the third node NC, the photosensitive device Q2 is turned off, which is external to the channel layer of the photosensitive device Q2. When light is incident from the light leakage current, the second storage capacitor CST2 is charged. At the fourth node ND, since the photosensitive device Q2 maintains the turn-off state, the photosensitive element Q2 is in a high impedance state to maintain the fourth node voltage VND at the high level.

In the read period, when the high level third node voltage VNC is applied to the third node NC, the photosensitive device Q2 is turned on and the charge charged in the second storage capacitor CST2 is charged. It is supplied to the readout IC (not shown) via Q2 and the fourth node ND.

As described above, the optical sensing element provided in the optical sensor unit according to the present invention performs an operation as a switch for a predetermined time, and performs an operation as an optical sensing element for the next predetermined time, so that one thin film transistor and one capacitor are used. It can be confirmed that the optical sensor normally operates.

4 is a plan view of the array substrate according to the example of FIG. 2 described above, and FIG. 5 is a cross-sectional view taken along the line AA ′ of FIG. 4.

4 and 5, an array substrate according to an embodiment of the present invention is connected to a plurality of gate lines 112, a plurality of drain lines 122, a gate line 112, and a drain line 122. Switching element Q1, first storage capacitor CST1, first power line 116, second power line 118, photosensitive element Q2, second storage capacitor CST2, lead-out wiring 126 ), A pixel electrode 160, and a reflection plate 170 defining a reflection area and a transmission area.

The plurality of gate wires 112 extend in the horizontal direction on the transparent substrate (not shown) and are arranged in the vertical direction, and the plurality of drain wires 122 extend in the vertical direction on the transparent substrate and in the horizontal direction. Arranged to define multiple partitioned regions.

The switching element Q1 is formed in a region partitioned from the gate wiring 112 and the drain wiring 122, and extends from the gate electrode line 210 extending from the gate wiring 112 and the drain wiring 122. A drain electrode line 123 and a source electrode line 124 spaced apart from the drain electrode line 123 are included.

The first storage capacitor CST1 is defined by the first storage electrode line 114 formed when the gate wiring 112 is formed and the source electrode line 124 formed when the drain wiring 122 is formed.

The first power supply line 116 and the second power supply line 118 extend in the horizontal direction on the transparent substrate (not shown) parallel to the gate wiring 112, and are arranged in the vertical direction.

The lead-out wiring 126 extends in the vertical direction on the transparent substrate in parallel with the drain wiring 122 and is arranged in the horizontal direction to define a plurality of divided regions.

The photosensitive device Q2 defines a predetermined region extending from the first power line 116 as a gate electrode region, defines a predetermined region extending from the lead-out wiring 126 as a source electrode region, and reads out the lead-out wiring ( A region spaced a predetermined distance from 126 is defined as a drain electrode.

The second storage capacitor CST2 is defined by the second storage electrode line formed when the second power line 118 is formed and the source electrode line formed when the source electrode region of the photosensitive device Q2 is formed.

The pixel electrode 160 includes an ITO layer or an IZO layer made of a transparent material, and is formed in each of the pixel regions partitioned by the gate lines 112 adjacent to each other and the drain lines 122 adjacent to each other. Is connected to the source electrode line 124 to receive a pixel voltage for display.

The reflector plate 170 is formed on the pixel electrode 160 to define a reflection area for reflecting natural light and a transmission area or transmission window 134 for transmitting artificial light, and do not correspond to the channel area of the light sensing element Q2. And external light is applied to the channel region.

6A to 6E are diagrams for describing the manufacturing process sequence of FIG. 4 described above.

First, referring to FIGS. 4 to 6A, tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), on a transparent substrate 105 made of an insulating material such as glass or ceramics. After depositing a metal such as copper (Cu) or tungsten (W), the deposited metal is patterned to form a gate wiring 112, a first gate electrode wiring 113, a first storage electrode wiring 114, and a first power source. The wiring 116, the second gate electrode wiring 117, and the second power supply wiring 118 are formed.

The gate wiring 112 extends in the horizontal direction and is arranged in the vertical direction, and the first gate electrode wiring 113 extends from the gate wiring 112. The first storage electrode wiring 114, the first power wiring 116, and the second power wiring 118 are formed in parallel with the extending direction of the gate wiring 112. The second gate electrode wiring 117 extends from the first power wiring 116.

Subsequently, silicon nitride is deposited on the entire surface of the substrate including the gate electrode wiring 113 by plasma chemical vapor deposition to form a gate insulating film 119, and then an amorphous silicon film and an in situ formed on the gate insulating film 119. patterning the doped n ⁺ amorphous silicon film to form a semiconductor layer 117a on a portion of the gate insulating layer 119 where the first gate electrode wiring 113 and the second gate electrode wiring 117 are positioned; The first active layer 117c and the second active layer 117d each formed of the ohmic contact layer 117b are formed.

The gate insulating layer 119 serves as a kind of dielectric layer defining the second storage capacitor CST2 in the future, and may be formed on the entire surface of the substrate, and the gate wiring 112 and the gate electrode wiring 113 may be formed. It may be patterned to cover.

6B, tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or the like on the substrate on which the resultant of FIG. 6A is formed. A metal such as tungsten (W) is deposited.

Subsequently, the deposited metal is patterned to form a drain wiring 122, a first drain electrode wiring 123, a first source electrode wiring 124, a lead-out wiring 126, a second source electrode wiring 127, and a second electrode. 2 drain electrode wiring 128 is formed. The source electrode wiring 124 formed on the upper portion and the capacitor wiring formed on the lower portion overlap each other in a plan view to perform an operation as the first storage capacitor CST1.

The drain wiring 122 extends in the vertical direction and is arranged in the horizontal direction, and the first drain electrode wiring 123 extends from the drain wiring 122, and the first source electrode wiring 124 is the first drain electrode. The pattern is spaced apart from the wiring 123 by a predetermined interval.

The first source electrode wiring 124 and the first storage electrode wiring 114 formed at the bottom thereof overlap each other in a plan view to operate as the first storage capacitor CST1, and the second drain electrode wiring 128. The second power line 118 formed at the lower portion and the lower portion overlaps a predetermined area when viewed in a plane to operate as the second storage capacitor CST2.

The lead-out wiring 126 extends in the longitudinal direction and is arranged in the horizontal direction, the second source electrode wiring 127 extends from the lead-out wiring 126, and the second drain electrode wiring 128 is the second It is patterned to be spaced apart from the source electrode wiring 127 by a predetermined interval.

Subsequently, as illustrated in FIG. 6C, a resist is laminated on the substrate on which the resultant substrate of FIG. 6B is formed by spin coating to form a thin organic insulating layer 130.

Next, a first hole exposing a portion of the source electrode wiring 124 by removing a portion of the organic insulating layer 130 from every pixel defined by the gate wiring 112 and the drain wiring 122. 132 is formed, and another part of the organic insulating layer 130 is removed to form a second hole 134 exposing the transparent substrate 105, and another part of the organic insulating layer 130 is removed. A third hole 136 that exposes a portion of the semiconductor layer 117a formed on the two gate electrode wiring 116 is formed.

Subsequently, as shown in FIG. 6D, the surface of the organic insulating layer 130 on which the first to third holes 132, 134, and 136 are formed is embossed to form valleys 142 and the floor 144 having different heights. After the concave-convex member 146 is formed, the passivation film 150 is formed. The uneven member 146 increases the reflection efficiency by the reflector to be formed in the future.

Next, as shown in FIG. 6E, an ITO layer 160 defining a pixel electrode is formed on the passivation layer 150, and the ITO layer 160 has holes previously formed with the source electrode wiring 124. 132 is connected. In this case, the ITO layer 160 may be patterned so that only the ITO layer corresponding to each pixel region is left after the entire surface is applied, or partially coated to be formed only in the pixel region. In the drawing, although the pixel electrode 160 is spaced apart from the drain wiring 122 and the gate wiring 122 at a viewer's perspective, the pixel electrode 160 may overlap with a minimum width.

Subsequently, the reflector plate 170 is formed on the resultant of FIG. 6E to complete the array substrate as illustrated in FIG. 3. The reflective plate 170 is unformed to correspond to the second hole 134 to define a transmission region, and is not formed to correspond to the third hole 136 to allow external light to be applied to the active layer of the photosensitive device. Of course, it is obvious to further form a separate alignment layer (not shown) for the rubbing of the liquid crystal on the reflective plate 170.

In the drawing, although the reflective plate 170 is formed for each pixel, the reflective plate 170 may be formed in the remaining regions except for the transmissive region defined by the organic insulating layer 130. .

In addition, the reflecting plate shown in the figure is shown to be formed in conjunction with the shape of the organic insulating layer 130 is embossed surface in order to increase the reflection efficiency, the above-described organic insulating layer is formed in a flat type, on the flat type It is also possible to form a reflecting plate.

As described above, according to the present invention, the photosensitive device provided in the optical sensor unit performs an operation as a switch for a predetermined time, and operates as an optical sensing device for the next predetermined time, so that one thin film transistor and one capacitor are used. Only the optical sensor operates normally.

As a result, the light sensing panel can be implemented through a simplified structure even if it is employed in the unit pixel region of the array substrate, thereby reducing the aperture ratio.

In addition, since the distance between the wirings can be widened by the simplified structure, the design margin of the array substrate can be sufficiently secured, and the problems caused by the signal interference between the wirings can be minimized.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

1 is an equivalent circuit diagram of an optical sensor employed in a general array substrate.

2 is an equivalent circuit diagram illustrating an optical sensor according to an exemplary embodiment of the present invention.

FIG. 3A is a view for explaining an optical sensor unit according to the present invention, and FIG. 3B is a waveform diagram for explaining the operation of the optical sensor unit shown in FIG. 3A.

4 is a plan view of the array substrate according to the example of FIG. 2 described above.

FIG. 5 is a cross-sectional view taken along the line AA ′ of FIG. 4.

6A to 6E are diagrams for describing the manufacturing process sequence of FIG. 4 described above.

<Description of the symbols for the main parts of the drawings>

GL: Gate Line DL: Data Line

Q1: switching element Q2: photosensitive element

CLC: Liquid Crystal Capacitor CST1, CST2: Storage Capacitor

VL1, VL2: power line ROL: lead out line

Claims (7)

A storage capacitor once connected to the first power supply voltage; And As a first current electrode is connected to the other end of the storage capacitor, and an active signal is applied through a control electrode, photo leakage charge corresponding to light that is activated and applied from the outside is stored in the storage capacitor, and the control electrode is stored. And a photosensitive device configured to output the stored photo leakage charge through a second current electrode as a selection signal is applied thereto. The optical sensor of claim 1, wherein the active signal is applied during a first frame period, and the selection signal is applied during a second frame period. A plurality of first scan lines carrying a first scan signal; A plurality of data lines carrying data signals; A pixel unit displaying an image corresponding to the data signal in response to the first scan signal; A plurality of second scan lines; Multiple lead out lines; And As the active signal is applied through the second scan line, the light leakage charge corresponding to the light applied from the outside is stored, and as the selection signal is applied through the second scan line, the stored light leakage charge is stored. Liquid crystal display comprising an optical sensor unit for outputting through the lead out line. The liquid crystal display of claim 3, wherein the active signal is applied during a first frame period, and the selection signal is applied during a second frame period. The display device of claim 2, wherein the pixel portion is formed in an area defined by the first scan line adjacent to each other and the data line adjacent to each other, A switching element having a control electrode connected to the gate line and a first current electrode connected to the data line; A liquid crystal capacitor having one end connected to a second current electrode of the switching element; And And a storage capacitor having one end connected to a second current electrode of the switching element. The method of claim 3, wherein the optical sensor unit is formed in a region defined by the second scan line adjacent to each other and the lead out line adjacent to each other, A storage capacitor once connected to the first power supply voltage; And As a first current electrode is connected to the other end of the storage capacitor, and an active signal is applied through a control electrode, photo leakage charge corresponding to light that is activated and applied from the outside is stored in the storage capacitor, and the control electrode is stored. And a photosensitive device configured to output the stored photo leakage charge through a second current electrode as a selection signal is applied thereto. The liquid crystal display of claim 6, wherein the first power supply voltage is smaller than a minimum voltage sensed by the lead-out line.