KR20050058042A - Fabricating method liquid crystal display device - Google Patents

Abstract

The present invention relates to a method of manufacturing a liquid crystal display device using a three-mask process, comprising the steps of preparing a transparent substrate; Depositing a first metal film on the substrate, and then forming a gate line, a gate electrode, and a gate pad through a first mask process; The first insulating layer, the amorphous silicon, the n + amorphous silicon, and the second metal film are sequentially stacked on the entire surface of the substrate including the gate electrode and the gate line, and then vertically intersect the gate line through a second mask process, and the pixel region is intersected. Forming a data line, a semiconductor layer (active layer, ohmic contact layer), a source / drain electrode, and a data pad to be defined; After forming a second insulating layer on the entire surface of the substrate including the data line and the source / drain electrodes, and then exposing the first insulating layer, the gate pad, and the data pad of the pixel region through a third mask process, a transparent layer is disposed thereon. By depositing a conductive film. A method of manufacturing a liquid crystal display device comprising the steps of forming a pixel electrode connected to a drain electrode, a gate connection terminal and a data connection terminal connected to the gate pad and the data pad.

Description

Manufacturing method of liquid crystal display device {FABRICATING METHOD LIQUID CRYSTAL DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a method for manufacturing a liquid crystal display device capable of reducing the number of mask processes and improving productivity and image quality through terminal compensation of a pixel electrode.

In display devices, particularly flat panel displays such as liquid crystal display devices, each pixel includes an active device such as a thin film transistor to drive the display device. The driving method is often called an active matrix driving method. In the active matrix method, the active elements are arranged in each pixel arranged in a matrix to drive the pixel.

In general, a liquid crystal display device is composed of a lower substrate and an upper substrate and a liquid crystal layer formed therebetween. The lower substrate is a driving element array substrate. A plurality of pixels are formed on the lower substrate, and a driving element such as a thin film transistor is formed on each pixel, and the upper substrate is a color filter. As a filter substrate, a color filter layer for realizing color is formed. In addition, a pixel electrode and a common electrode are formed on the lower substrate and the upper substrate, respectively, and an alignment layer for aligning liquid crystal molecules of the liquid crystal layer is coated.

In addition, the lower substrate and the upper substrate are bonded by a sealant formed on the outer periphery of the substrate, and maintain a constant cell gap by a spacer formed between them (upper substrate and lower substrate). The liquid crystal layer formed between the substrates drives liquid crystal molecules by a driving element formed on the lower substrate to control the amount of light passing through the liquid crystal layer to display information.

Hereinafter, the lower substrate of the liquid crystal display device will be described in more detail. In the lower substrate (ie, the driving element array substrate) of the liquid crystal display device, N × M pixels are arranged horizontally and horizontally, and each pixel is provided from an external driving circuit. And a TFT formed at the intersection of the gate line to which the scan signal is applied and the data line to which the image signal is applied. The TFT includes a gate electrode connected to the gate line, a semiconductor layer formed on the gate electrode and activated when a scan signal is applied to the gate electrode, and a source / drain electrode formed on the semiconductor layer.

In addition, a pixel electrode is formed in the display area of the pixel to operate the liquid crystal (not shown) by applying an image signal through the source / drain electrode as the semiconductor layer is connected to the source / drain electrode to activate the semiconductor layer.

In the liquid crystal display device configured as described above, the drain electrode of the TFT is electrically connected to the pixel electrode formed in the pixel, and as a signal is applied to the pixel electrode through the source / drain electrode, the liquid crystal is driven to display an image.

As described above, the lower substrate of the liquid crystal display device forms various patterns such as a driving element (TFT) or a wiring (for example, a gate / data line) on the substrate to perform an operation. One common method is photolithography.

1A to 1E are cross-sectional views illustrating a method of manufacturing a liquid crystal display device using five masks in the related art.

First, as illustrated in FIG. 1A, a transparent substrate 10 is prepared, and then a gate electrode material is deposited thereon, and then patterned through a first mask process to form the gate electrode 1a.

Subsequently, as shown in FIG. 1B, an insulating film, an amorphous silicon, and an n + amorphous silicon film are sequentially stacked on the entire surface of the substrate including the gate electrode 1a, and then patterned through the second mask process to form the gate insulating film 2. ), The active layer 5a and the n + layer 5b 'are formed.

Next, as shown in FIG. 1C, the source / drain electrode material is deposited on the entire surface of the substrate including the active layer 5a and the n + layer 5b ', and then patterned through a third mask process. An ohmic contact layer 5b made of an n + layer and a source electrode 2a and a drain electrode 2b exposing the center portion of the layer 5a is formed.

Subsequently, as shown in FIG. 2D, an insulating film is deposited on the entire surface of the substrate including the source electrode 2a and the drain electrode 2b to form a protective film 6, and then the drain electrode (through a fourth mask process) is formed. A contact hole 9 exposing a part of 2b) is formed.

Lastly, as shown in FIG. 2E, the pixel electrode material is deposited on the passivation layer 6 including the contact hole 9, and then patterned to form a drain electrode 2b and the drain electrode 2b through the contact hole 9. The pixel electrode 7 to be connected is formed.

At this time, the mask process proceeds to form each pattern is a photolithography process, the photolithography process is to coat a photoresist, a material that is photosensitive with ultraviolet rays to the substrate on which the pattern is to be formed, and to expose the pattern formed on the mask on the photoresist It is developed and etched, and a patterned photoresist is used as a mask to etch a desired layer of material, followed by a series of complex processes of removing the photoresist.

Therefore, as the number of mask processes increases, the process time and the process cost increase, and thus there is a problem in that productivity decreases. Accordingly, research is being conducted on low mask technology to minimize the number of mask processes to increase productivity and to secure process margins.

An object of the present invention to provide a method for manufacturing a liquid crystal display device through a low mask technology, in particular, to provide a method for manufacturing a liquid crystal display device through a three mask process.

In addition, another object of the present invention is to provide a liquid crystal display device capable of improving image quality and aperture ratio by compensating for a step in a pixel region, that is, an edge region.

Therefore, the present invention is made to achieve the above object, the method of manufacturing a liquid crystal display device according to the present invention comprises the steps of preparing a transparent substrate; Depositing a first metal film on the substrate, and then forming a gate line, a gate electrode, and a gate pad through a first mask process; The first insulating layer, the amorphous silicon, the n + amorphous silicon, and the second metal film are sequentially stacked on the entire surface of the substrate including the gate electrode and the gate line, and then vertically intersect the gate line through a second mask process, and the pixel region is intersected. Forming a data line, a source / drain electrode and a gate line, and a data pad to be defined; After forming a second insulating layer on the entire surface of the substrate including the data line and the source / drain electrodes, and then exposing the first insulating layer, the gate pad, and the data pad of the pixel region through a third mask process, a transparent layer is disposed thereon. By depositing a conductive film. And forming a pixel electrode connected to the drain electrode, a gate connection terminal and a data connection terminal connected to the gate pad and the data pad.

In this case, the second mask process may include applying a PR film on the second metal film; Irradiating light to the photosensitive film through a mask provided with a first transmission region for transmitting only part of the light, a second transmission region for transmitting all of the light, and a blocking region for blocking the light; The PR irradiated with light through the mask is developed to form a PR pattern on the second metal layer, wherein a first PR pattern having a first thickness is formed in the first transmission area, and a second thickness in the second transmission area. Forming a second PR pattern having a; Etching the amorphous silicon and n + amorphous silicon layers using the first and second PR patterns as masks to form data lines, active layers, n + layers, and data pads; Exposing the central region of the second metal pattern formed on the n + layer by removing the first PR pattern; And forming a source / drain electrode by removing a portion of the second metal pattern and the n + layer using the second PR pattern as a mask, wherein the thickness of the first PR pattern is smaller than the thickness of the second PR pattern.

In addition, during the formation of the source / drain electrodes, a storage electrode may be further formed to overlap the gate line to form a storage capacitor.

As described above, the formation of the PR patterns having different thicknesses through one exposure process is performed by forming the MoSi film in the first transmission region and forming the Cr film in the light blocking region. In addition, the first transmission region may be formed in a slit structure.

The third mask process may further include applying photoresist PR on the second insulating layer; Irradiating light to the photosensitive film through a mask provided with a first transmission region for transmitting only part of the light, a second transmission region for transmitting all of the light, and a blocking region for blocking the light; The PR irradiated with light through the mask is developed to form a PR pattern on the second insulating layer, to form a first PR pattern having a first thickness in the first transmission region, and to form a second thickness in the second transmission region. Forming a second PR pattern having; Etching the first and second insulating layers using the first and second PR patterns as masks to form first contact holes exposing gate pads and second contact holes exposing side surfaces of the data pads; Removing the first PR pattern and then exposing the first insulating film by removing the second insulating film of the pixel region using the second PR pattern as a mask; And depositing a transparent conductive film on the entire surface of the substrate including the second PR pattern, and then removing the second PR pattern and the transparent conductive film formed thereon, thereby connecting the gate connection terminal to the gate pad through the pixel electrode and the first contact hole. And forming a data connection terminal connected to the data pad through the contact hole. In this case, the pixel electrode may overlap the gate line, and the pixel electrode and the gate line overlap each other to form a storage capacitor.

Meanwhile, a repair pattern may be further formed below the data line, and the repair pattern may be formed together with the gate line during the first mask process. The transparent conductive film may use indium tin oxide (ITO) or indium zinc oxide (IZO).

In addition, the method of manufacturing a liquid crystal display device according to the present invention comprises the steps of preparing a transparent substrate; Forming a gate line, a gate electrode, and a gate pad on the substrate; Forming a gate insulating film on an entire surface of the substrate including the gate electrode and the gate pad; A data line, a semiconductor layer (active layer, ohmic contact layer), a source / drain electrode, and a data pad defining a pixel region are formed on the gate insulating layer to cross the gate line perpendicularly to the gate line, and the gate insulating layer is formed in each pixel region. Exposing; Forming a protective film on an entire surface of the substrate including the data line and the source / drain electrodes and applying a photoresist (PR) thereon; Forming a PR pattern using a mask, forming a contact hole exposing the gate pad and the data pad as an etch mask, and exposing a gate insulating film in the pixel region; A pixel electrode is formed on the gate insulating film of the pixel region by depositing a transparent conductive film on the entire surface of the substrate including the PR pattern, the gate insulating film of the pixel region and the contact hole, and then removing the PR pattern and the transparent conductive film formed thereon. Forming a gate connection terminal and a data connection terminal respectively connected to the gate pad and the data pad through the contact hole.

In this case, the pixel electrode may be formed to overlap the gate line, or may further form a storage electrode overlapping the gate line when forming the source / drain electrode.

Forming the data line, semiconductor layer (active layer, ohmic contact layer) source / drain electrode, and data pad may include sequentially depositing amorphous silicon, n + amorphous silicon, and a metal layer on the gate insulating layer; Applying a photoresist (PR) on the metal layer; Irradiating light to the photosensitive film through a mask provided with a first transmission region for transmitting only part of the light, a second transmission region for transmitting all of the light, and a blocking region for blocking the light; Developing PR irradiated with light through the mask to form a PR pattern on the metal layer, to form a first PR pattern having a first thickness in a first transmission region, and a second thickness in the second transmission region. Forming a second PR pattern; Etching the amorphous silicon and n + amorphous silicon layers using the first and second photosensitive patterns as masks to form a data line, an active layer, an n + layer, and a data pad; Exposing the central region of the metal pattern formed on the n + layer by removing the first PR pattern; And removing a portion of the metal pattern and the active layer using the second PR pattern as a mask to form an active layer and a source / drain electrode. At this time, the thickness of the first PR pattern is formed thinner than the thickness of the second PR pattern.

Forming a PR pattern on the passivation layer may include applying a photoresist (PR) on the passivation layer; Irradiating light onto the PR film through a mask provided with a first transmission region for transmitting only part of the light, a second transmission region for transmitting all of the light, and a blocking region for blocking the light; And developing a PR pattern irradiated with light through the mask to form a PR pattern on the passivation layer, wherein the first PR pattern is formed in the first transmission area, and the second PR pattern is relatively thicker than the first PR pattern in the second transmission area. Forming a step. In addition, by etching a portion of the gate insulating layer and the passivation layer using the first and second PR patterns as masks to form a contact hole exposing the gate pad and the data pad, the first PR pattern is removed, and then the second PR pattern is removed. By removing the protective film of the pixel region as a mask, the gate insulating film of the pixel region is exposed, and the first PR pattern is removed through an ashing process.

As described above, the present invention manufactures a liquid crystal display device through three mask processes. That is, the semiconductor layer composed of the active layer and the ohmic contact layer and the source / drain electrode, which are formed through the conventional two mask processes, are reduced to one mask process, and the protective film and the pixel electrode are reduced to one mask process. The mask process can be reduced.

In addition, according to the present invention, by using a halftone or a diffraction mask in the third mask process, the first insulating layer formed in the pixel region is left without being removed, thereby reducing the step difference between the drain electrode and the storage electrode connected to the pixel electrode. It can remove light leakage and improve aperture ratio.

That is, in the third mask process, when the half mask or the diffraction mask is not used and a general mask composed of only 100% transmission region and blocking region is used, the pixel electrode is formed on the transparent substrate, and the pixel electrode is formed of the drain electrode and the storage electrode. The step difference between the regions connected to each other is formed by the first insulating layer and the semiconductor layer (amorphous silicon and ohmic contact layer). On the other hand, when the pixel electrode is formed on the first insulating layer using the halftone mask, the step difference between the region where the pixel electrode is connected to the drain electrode and the storage electrode is due to a semiconductor layer (amorphous silicon, ohmic contact layer). Compared with the case where a general mask is used, the step caused by the first insulating film can be eliminated.

Therefore, the light leakage area can be reduced and the opening area can be increased by the step by the first insulating film.

Hereinafter, a method of manufacturing a liquid crystal display device according to the present invention will be described in more detail with reference to the accompanying drawings.

2 is a schematic plan view of a liquid crystal display device according to the present invention.

As shown in the figure, the intersection of the gate line 101 to which a scan signal is applied from an external driving circuit and the data line 103 to which an image signal is applied to each pixel of a liquid crystal display device in which N x M pixels are arranged. And a thin film transistor (TFT) formed in the region. The TFT includes a gate electrode 101a connected to the gate line 101, an active layer 105a formed on the gate electrode 101a and activated when a scan signal is applied to the gate electrode 101a, and the active layer. And source / drain electrodes 102a and 102b formed over 105a. As the active layer 105a is activated by being connected to the source / drain electrodes 102a and 102b in the display area of the pixel, an image signal is applied through the source / drain electrodes 102a and 102b so that the liquid crystal (not shown) Is formed, and the pixel electrode 107 is connected to the storage electrode 109 overlapping the gate line 101.

The storage electrode 109 together with the gate line 101 forms a storage capacitor Cst.

In addition, the storage capacitor Cst may be formed by overlapping the gate line 101 with the pixel electrode 107 without forming the storage electrode 109.

Although not illustrated in detail, a repair pattern may be formed under the data line 103, and the repair pattern may be formed in a gate line forming process.

In the liquid crystal display device configured as described above, the drain electrode 102b of the TFT is electrically connected to the pixel electrode 107 formed in the pixel, and a signal is applied to the pixel electrode 7 through the source / drain electrodes 102a and 102b. As a result, the liquid crystal is driven to display an image.

Although not shown in the drawings, a gate pad and a data pad configured to receive a signal from an external driving circuit are formed at one side of the gate line 101 and the data line 103.

The liquid crystal display device constructed as described above is manufactured through a three mask process, and a manufacturing method of the liquid crystal display device according to the present invention will be described through a process sectional view of I-I '.

3A to 3C illustrate a method of manufacturing a liquid crystal display device according to the present invention, wherein a thin film transistor region T and a storage capacitor region S, a gate line and a data line along the cut line of the line II ′ of FIG. 1 are illustrated. Process cross-sectional views of the gate pad GP and the data pad region DP formed on one side of the substrate are shown.

First, as shown in FIG. 3A, a transparent substrate 110 is prepared, and then Al, Mo, Cu, MoW, MoTa, MoNb, Cr, W or aluminum (Al) and molybdenum (Mo) are formed on the substrate 110. A first metal film (not shown) such as a double layer of is deposited by a sputtering method. The first metal layer is patterned through the first mask process to form the gate electrode 101a, the gate line 101, and the gate pad 101b, respectively.

Subsequently, as illustrated in FIG. 3B, an inorganic material such as SiNx or SiOx is deposited on the entire surface of the substrate including the gate electrode 101a, the gate line 101, and the gate pad 101b to form the first insulating layer 102, that is, the first insulating layer 102. A gate insulating film, an n + amorphous silicon film doped with impurities such as an amorphous silicon film and phosphorus (P) thereon, and Al. After depositing a second metal film such as AlNd, Cr, Mo, Cu, etc. sequentially, the semiconductor layer 105 and the semiconductor layer 105 composed of the active layer 105a and the ohmic contact layer 105b through a second mask process Source / drain electrodes 102a and 102b exposing a center portion of the active layer 105a and a storage electrode 109 and a data pad 103a disposed on the gate line 101, respectively. do.

In this case, in the second mask process, since the semiconductor layer 105 and the source / drain electrodes 102a and 102b must be formed at the same time through a single mask process, a diffraction mask or a half-tone mask is used. Use That is, since the diffraction mask has a slit structure in the light transmission region, and the amount of exposure irradiated through the slit region is smaller than the perfect transmission region through which all the light is transmitted, after applying the PR film, the slit region and the part of the diffraction mask are partially applied. When exposure is performed using a mask provided with a complete transmission region, the thickness of the PR remaining in the slit region and the thickness of the PR remaining in the complete transmission region are formed differently. That is, in the case of positive PR, the thickness of the PR irradiated with light through the slit region is formed thicker than that of the fully transmissive region, whereas in the case of negative PR, the thickness of the photosensitive remaining in the fully transmissive region is thick.

Accordingly, the present invention simultaneously forms the semiconductor layer 105 and the source / drain electrodes 102a and 102b using the characteristics of the diffraction mask. In addition, a halftone mask may be used. In the case of the halftone mask, chromium is formed in the light blocking region, and molybdenum silicide (MoSi) is formed in the halftone region. At this time, the amount of permeation can be controlled by adjusting the thickness of molybdenum silicide.

4A to 4D, the second mask process using the diffraction mask (that is, the process of forming the semiconductor layer 105 and the source / drain electrodes 102a and 102b) will be described in more detail. As described above, the first insulating film 102, the amorphous silicon film 105a ', and the n + amorphous silicon film 105b' are disposed on the entire surface of the substrate including the gate electrode 101a, the gate line 101, and the gate pad 101b. And sequentially stacking the second metal film 103 ', and then applying the PR film 130 thereon. Then, the diffraction mask 140 is applied to irradiate light such as UV (indicated by an image table on the drawing). At this time, the diffraction mask 140 is provided with a first transmission region A1 for transmitting only part of the light, a second transmission region A2 for transmitting all of the light, and a blocking region A3 for blocking all the irradiated light. Light transmitted through the mask 140 is irradiated to the PR film 130.

Subsequently, as shown in FIG. 4B, the PR film 130 exposed through the diffraction mask 140 is developed to irradiate light through the first transmission area A1 and the second transmission area A2. Only the PR film is left and the remaining area is removed. In this case, the first PR pattern 130a formed through the first transmission area A1 is thinner than the second PR pattern 130b formed in the second transmission area A2. This is because negative PR is used, and negative PR is used more than positive PR because it has a higher resolution than positive PR. On the other hand, it can also be formed using positive PR, in which case it is necessary to reverse the pattern of the diffraction mask. That is, the light should be blocked in the area where the PR is to be left.

Subsequently, the second metal film 103 ', the n + amorphous silicon film 105b' and the amorphous silicon film 105a 'formed under the first and second PR patterns 130a and 130b are formed as masks. ), The active layer 105a, the n + pattern 105b ', the second metal pattern 103', the storage electrode 109, and the data pad 103a are formed. In this case, a part of the side surface of the data pad 103a is exposed by the contact hole 103a '.

Subsequently, as illustrated in FIG. 4C, the first PR pattern 130a is removed through an ashing process. At this time, a part of the second PR pattern 130b is also removed, so that its thickness becomes thin. Subsequently, as the first photosensitive pattern 130a is removed using the second photosensitive pattern 130b as a mask, the exposed second metal pattern 103 'and the n + layer 105b' are etched to form an active layer 105a. The source / drain electrodes 102a and 102b and the ohmic contact layer 105b are formed on the upper portion and spaced apart from each other. At this time, the ohmic contact layer 105b is formed to reduce the resistance between the active layer 105a and the source / drain electrodes 102a and 102b to facilitate signal transmission. Thereafter, a stripper may be applied to remove the second PR patterns 130b formed on the source / drain electrodes 102a and 102b and the storage electrode 109.

As described above, when the semiconductor layer 105, the source / drain electrodes 102a and 102b and the storage electrode 109 and the data pad 103a are formed through the second mask process, as shown in FIG. 3C. A second insulating film 106, that is, a protective film is formed on the top. In addition, a PR film is coated on the second insulating layer 106 and then patterned through a third mask process to expose a part of the drain electrode 102b and the storage electrode 109, and the gate pad 101b and the data. First and second contact holes 101b 'and 103a' exposing the pad 103a are formed. After depositing a transparent conductive film on the upper portion, a pixel electrode 107 is formed to be connected to the drain electrode 102b and the storage electrode 109 through a lift-off process. The gate connection terminal 101c and the data connection terminal 103b which are connected to the gate pad 101c and the data pad 103a through the two contact holes 101b 'and 103a' are formed.

As described above, in the third mask process, the passivation layer and the pixel electrode may be formed in one mask process using the lift-off process, and the third mask process using the lift-off process may be further described with reference to FIGS. 5A to 5C. This will be explained in detail.

First, as shown in FIG. 5A, an inorganic film, such as SiOx or SiNx, or an organic film, such as BCB or acrylic, is coated on the entire surface of the substrate including the source / drain electrodes 102a and 102b and the storage electrode 109. After the two insulating films 106 are formed, a PR film is applied over them. Then, the PR film is patterned through the third mask process to form the PR pattern 150a that remains selectively on the second insulating film 106.

Subsequently, as shown in FIG. 5B, the first and second insulating layers 102 and 106 are removed using the PR pattern 150a as a mask, thereby exposing one side of the drain electrode 102b and the storage electrode 109. The substrate 110 in the pixel region is exposed. In this case, a first contact hole 101b 'exposing a part of the gate pad 101b and a second contact hole 103a' exposing a part of the data pad 103a are also formed. The insulating films 102 and 106 can be effectively removed by dry etching. In this manner, after all the desired patterns are formed, when the etching process is continued, the second insulating layer 106 is overetched to protrude the edge region of the PR pattern 150a.

Subsequently, as illustrated in FIG. 5C, a transparent conductive film 107 ′, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the entire surface of the substrate including the PR pattern 150a having the edge region protruding therefrom. do. At this time, since the conductive film 107 'is not deposited under the edge region of the PR pattern 150a, the region is exposed to the outside.

Subsequently, as shown in FIG. 5D, the PR pattern 150a having a portion of the edge region exposed is applied to a stripper to remove the PR pattern 150a and the conductive film 107 ′ deposited thereon. By removing them together, the pixel electrode 107, the gate connection terminal 101c and the data connection terminal 103b are formed, respectively. In this case, the pixel electrode 107 is connected to the drain electrode 102b and the storage electrode 109, and the gate connection terminal 101c is connected to the gate pad 101b through the first contact hole 101b 'and is connected to the data. The connection terminal 103b is connected to the data pad 103a through the second contact hole 103a '.

As described above, in the third mask process, after the PR pattern is formed on the protective film, the protective film is overetched to form a protruding region of the PR pattern, and a portion of the PR pattern is exposed to the outside by depositing a transparent electrode film thereon. Let's do it. By applying the PR pattern exposed to the outside to the stripper, the protective film and the pixel electrode can be formed in one mask process through a lift-off process of removing the PR pattern and the transparent electrode film deposited thereon.

As described above, through the three mask process, the present invention reduces the semiconductor layer (active layer and ohmic contact layer) and the source / drain electrode, which are conventionally formed through two mask processes, into one mask process, and the protective film and the pixel electrode are reduced. By reducing to one mask process, there is an advantage that the total of two mask processes can be reduced.

However, in the liquid crystal display device manufactured through the three mask process as described above, light leakage occurs in this region because the step difference between the drain electrode and the storage electrode connected to the pixel electrode is large.

That is, as shown in FIG. 5D, the step difference between the drain electrode 102b and the pixel electrode 107 connected to the storage electrode 109 is the gate insulating film 102, the active layer 105a, and the ohmic contact layer 105b. And the drain electrode 102b. Since the liquid crystal does not drive normally in this region D, defects such as light leakage appear on the screen. Therefore, the black matrix can be extended to this area to cover the light leakage area, but in this case, the aperture ratio is reduced, resulting in a problem that the brightness of the screen is lowered.

Accordingly, the present invention has been made in particular to solve this problem, and in another embodiment of the present invention, a diffraction mask or a halftone mask is used in the third mask process, thereby generating a region connected to the drain electrode and the storage electrode. By reducing the pixel electrode step, the light leakage area is minimized and the aperture ratio is improved. That is, by applying diffraction exposure to the pixel region and leaving the gate insulating film without removing the step, the step difference caused by the gate insulating film can be removed.

6A to 6E illustrate a method of manufacturing a liquid crystal display device according to another embodiment of the present invention. In particular, FIG. 6A to 6E illustrate a third mask process that is different from the previous embodiment. In addition, in the description of this embodiment, the description of the same configuration as in the previous embodiment will be omitted.

First, as shown in FIG. 6A, an inorganic film such as SiOx or SiNx is formed on the entire surface of the substrate including the source / drain electrodes 202a and 202b and the storage electrode 209 formed through the first and second mask processes. An organic film, such as BCB or acrylic, is applied to form a second insulating film 206, and then a PR film 250 is coated on the second insulating film 206. Then, a diffraction mask or halftone mask 240 is applied to irradiate light such as UV (indicated by an image table on the drawing). In this case, the diffraction mask 240 is provided with a first transmission region A1 for transmitting only part of the light, a second transmission region A2 for transmitting all of the light, and a blocking region A3 for blocking all the irradiated light. Light transmitted through the mask 240 is irradiated to the PR film 250.

Subsequently, as illustrated in FIG. 6B, the PR film 250 exposed through the diffraction mask 240 is developed to irradiate light through the first transmission area A1 and the second transmission area A2. Only the PR film is left and the remaining area is removed. In this case, the first PR pattern 250a formed through the first transmission area A1 is thinner than the second PR pattern 250b formed in the second transmission area A2. Subsequently, the first contact hole exposing the gate pad 101b by etching the exposed second insulating layer 206 and the first insulating layer 202 using the first and second PR patterns 250a and 250b as a mask. A second contact hole 203a 'exposing the 201b' and the data pad 203b is formed. In this case, the first and second insulating layers 202 and 206 may be effectively removed by dry etching.

When the first and second contact holes 117a and 117b are formed, as illustrated in FIG. 6C, the first PR pattern 250a is removed through an ashing process. At this time, a part of the second PR pattern 250b is also removed and the thickness thereof becomes thin. Subsequently, a portion of the drain electrode 202b and the storage electrode 209 is etched by etching the second insulating layer 206 of the exposed pixel region as the first PR pattern 250a is removed using the second PR pattern 250b as a mask. And expose the first insulating film 202 in the pixel region. In this case, the second insulating layers 102 and 106 may be effectively removed by dry etching, and after forming all the desired patterns, the second insulating layer 206 may continue to be etched after the desired pattern is formed. over etching) to protrude the edge region of the second PR pattern 250b.

As shown in FIG. 6D, a transparent conductive film 207 ′, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is disposed on the entire surface of the substrate including the second PR pattern 250b having the edge region protruding therefrom. Deposit. At this time, since the conductive film 207 'is not deposited under the edge region of the PR pattern 250a, the region is exposed to the outside.

Subsequently, the second PR pattern 250a exposing a part of the edge region is applied to a stripper to remove the second PR pattern 250b and simultaneously remove the conductive film 207 'deposited thereon. As shown in Fig. 6E, a pixel electrode 207 is formed on the first insulating film 202, i.e., the gate insulation, to connect the drain electrode 202b and the storage electrode 209. In this case, the gate connection terminal 201c is connected to the gate pad 201b through the first contact hole 201b ', and the data connection terminal is connected to the data pad 203a through the second contact hole 203a'. 203b) is also formed.

In addition, the step formed in the region where the pixel electrode 207 is connected to the drain electrode 202b and the storage electrode 209 is formed by the active layer 205a, the ohmic contact layer 205b, and the drain electrode 202b. It can be seen that the step formation area is reduced compared to the previous embodiment (FIG. 5D). That is, in the previous embodiment (FIG. 5D), the stepped region D of the pixel electrode 107 is formed by the gate insulating film 102, the active layer 105a, the ohmic contact layer 105b, and the drain electrode 102b. On the other hand, in the present embodiment (Fig. 6E), since the pixel electrode 207 is formed on the gate insulating film 202, the step difference caused by the gate insulating film 202 can be eliminated.

Therefore, in this embodiment, the light leakage area can be minimized by reducing the step area of the pixel electrode. In addition, since the area where light leakage is generated is smaller than in the previous embodiment, the area for forming the black matrix can be reduced, so that the aperture ratio can be improved.

In addition, the storage electrode 209 may be formed in the capacitor capacitor region S, and the pixel electrode 207 and the gate line 201 may overlap each other.

That is, as illustrated in FIG. 7, the storage electrode is omitted, and the pixel electrode 207 is formed by overlapping the gate insulating film 202 over the gate line 201. As such, when the pixel electrode 207 is directly overlapped with the gate line 201, the step difference of the pixel electrode 201 generated in this region can be more effectively removed. That is, in the previous embodiment (see FIG. 6E), due to the semiconductor pattern (active pattern and n + pattern) remaining in the lower portion of the storage electrode 209, there is a limit in reducing the step of the pixel electrode 209 in this region. . However, in this embodiment, since the storage electrode 209 which causes the step difference is removed, it is more advantageous in terms of opening secured.

As described above, the present invention provides a method of manufacturing a liquid crystal display device using a three mask process. In particular, in the process of forming the protective film and the pixel electrode, by using a diffraction mask or a halftone mask, it is possible to reduce the step difference generated in the region connecting to the drain electrode and the storage electrode of the pixel electrode, thereby reducing the light leakage region. It can minimize and improve aperture ratio.

As described above, according to the present invention, by manufacturing a liquid crystal display device through a low mask technology (three mask process), it is possible to reduce the process time, reduce the production cost and improve productivity.

In addition, the present invention can improve the image quality and the aperture ratio by compensating for the step difference generated in the edge region of the pixel electrode through a diffraction mask or a halftone mask process.

1A to 1E are cross-sectional views illustrating a method of manufacturing a liquid crystal display device by a conventional five mask process.

2 is a plan view schematically showing a liquid crystal display device according to the present invention.

3A to 3C are cross-sectional views illustrating a method for manufacturing a liquid crystal display device according to the present invention.

4A to 4C are cross-sectional views showing details of a second mask process according to the present invention.

5A to 5D are cross-sectional views showing details of a third mask process according to the present invention.

6A to 6E are cross-sectional views showing details of a third mask process according to another embodiment of the present invention.

7 is a cross-sectional view of a liquid crystal display according to another embodiment of the present invention.

*** Explanation of symbols for main parts of drawing ***

101a, 201a: gate electrodes 101b, 201b: gate pads

101c and 201c: gate connection terminals 102 and 202: first insulating film

103a, 203a: data pad 103b, 203b: data connection terminal

103a 'and 203a': second contact holes 105a and 205a: active layer

105b and 205b: ohmic contact hole 106 and 206: second insulating film

107,207: pixel electrode 109,209: storage electrode

Claims (20)

Preparing a transparent substrate; Depositing a first metal film on the substrate, and then forming a gate line, a gate electrode, and a gate pad through a first mask process; The first insulating layer, the amorphous silicon, the n + amorphous silicon, and the second metal film are sequentially stacked on the entire surface of the substrate including the gate electrode and the gate line, and then vertically intersect the gate line through a second mask process, and the pixel region is intersected. Forming a data line, a semiconductor layer (active layer, ohmic contact layer), a source / drain electrode, and a data pad to be defined; After forming a second insulating layer on the entire surface of the substrate including the data line and the source / drain electrodes, and then exposing the first insulating layer, the gate pad, and the data pad of the pixel region through a third mask process, a transparent layer is disposed thereon. By depositing a conductive film. And forming a pixel electrode connected to the drain electrode, a gate connection terminal and a data connection terminal connected to the gate pad and the data pad. The method of claim 1, wherein the second mask process, Applying a photoresist layer on the second metal film; Irradiating light to the photosensitive film through a mask provided with a first transmission region for transmitting only part of the light, a second transmission region for transmitting all of the light, and a blocking region for blocking the light; The PR irradiated with light through the mask is developed to form a PR pattern on the second metal layer, wherein a first PR pattern having a first thickness is formed in the first transmission area, and a second thickness in the second transmission area. Forming a second PR pattern having a; Etching the amorphous silicon and n + amorphous silicon layers using the first and second PR patterns as masks to form data lines, active layers, n + layers, and data pads; Exposing the central region of the second metal pattern formed on the n + layer by removing the first PR pattern; And Forming a ohmic contact layer and a source / drain electrode by removing a portion of the second metal pattern and the n + layer by using the second PR pattern as a mask. The method of claim 2, wherein the thickness of the first PR pattern is smaller than the thickness of the second PR pattern. The method of claim 2, wherein a MoSi film is formed in the first transmission region of the mask, and a Cr film is formed in the light blocking region. The method of claim 2, wherein the first transmission region of the mask has a slit structure. The method of claim 1, wherein the third mask process, Applying a PR film on the second insulating film; Irradiating light onto the PR film through a mask provided with a first transmission region for transmitting only part of the light, a second transmission region for transmitting all of the light, and a blocking region for blocking the light; The PR irradiated with light through the mask is developed to form a PR pattern on the second insulating layer, to form a first PR pattern having a first thickness in the first transmission region, and to form a second thickness in the second transmission region. Forming a second PR pattern having; Etching the first and second insulating layers using the first and second PR patterns as masks to form first contact holes exposing gate pads and second contact holes exposing side surfaces of the data pads; Removing the first PR pattern and then exposing the first insulating film by removing the second insulating film of the pixel region using the second PR pattern as a mask; And After depositing a transparent conductive film on the entire surface of the substrate including the second PR pattern, and removing the second PR pattern and the transparent conductive film formed on the upper portion, the gate connection terminal and the gate connection terminal for connecting to the gate pad through the pixel electrode and the first contact hole 2. A method of manufacturing a liquid crystal display device, comprising forming a data connection terminal connected to a data pad through a contact hole. The method of claim 1, wherein a repair pattern is further formed below the data line. The method of claim 7, wherein the repair pattern is formed together with the gate line during the first mask process. The method of claim 1, wherein the transparent conductive film is formed using indium tin oxide (ITO) or indium zinc oxide (IZO). The method of claim 1, further comprising forming a storage electrode overlapping the gate line to form a storage capacitor when the source / drain electrodes are formed.  The method of claim 1, wherein the pixel electrode is formed to overlap the gate line. Preparing a transparent substrate; Forming a gate line, a gate electrode, and a gate pad on the substrate; Forming a gate insulating film on an entire surface of the substrate including the gate electrode and the gate pad; A data line, a semiconductor layer (active layer, ohmic contact layer), a source / drain electrode, and a data pad defining a pixel region are formed on the gate insulating layer to cross the gate line perpendicularly to the gate line, and the gate insulating layer is formed in each pixel region. Exposing; Forming a protective film on an entire surface of the substrate including the data line and the source / drain electrodes and applying a photoresist (PR) thereon; Forming a PR pattern using a mask, forming a contact hole exposing the gate pad and the data pad as an etch mask, and exposing a gate insulating film in the pixel region; A pixel electrode is formed on the gate insulating film of the pixel region by depositing a transparent conductive film on the entire surface of the substrate including the PR pattern, the gate insulating film of the pixel region and the contact hole, and then removing the PR pattern and the transparent conductive film formed thereon. Forming a gate connection terminal and a data connection terminal respectively connected to the gate pad and the data pad through the contact hole. The method of claim 12, wherein the pixel electrode is formed to overlap the gate line. The method of claim 12, further comprising forming a storage electrode overlapping the gate line when the source / drain electrode is formed. The method of claim 12, wherein the forming of the data line, semiconductor layer (active layer, ohmic contact layer) source / drain electrode, and data pad comprises: Sequentially depositing an amorphous silicon, an n + amorphous silicon and a metal layer on the gate insulating film; Applying a photoresist (PR) on the metal layer; Irradiating light onto the PR film through a mask provided with a first transmission region for transmitting only part of the light, a second transmission region for transmitting all of the light, and a blocking region for blocking the light; Developing PR irradiated with light through the mask to form a PR pattern on the metal layer, to form a first PR pattern having a first thickness in a first transmission region, and a second thickness in the second transmission region. Forming a second PR pattern; Etching the amorphous silicon and n + amorphous silicon layers using the first and second PR patterns as masks to form data lines, active layers, n + layers, and data pads; Exposing the central region of the metal pattern formed on the n + layer by removing the first PR pattern; And And removing a portion of the metal pattern and the active layer by using the second PR pattern as a mask to form an active layer and a source / drain electrode. The method of claim 15, wherein a thickness of the first PR pattern is smaller than a thickness of the second PR pattern. The method of claim 12, wherein the forming of the PR pattern on the passivation layer comprises: Applying a photoresist (PR) on the protective film; Irradiating light onto the PR film through a mask provided with a first transmission region for transmitting only part of the light, a second transmission region for transmitting all of the light, and a blocking region for blocking the light; And The PR irradiated with light is developed to form a PR pattern on the passivation layer, wherein a first PR pattern is formed in the first transmission area, and a second PR pattern that is relatively thicker than the first PR pattern is formed in the second transmission area. A method of manufacturing a liquid crystal display device, characterized in that it comprises the step of forming. 18. The method of claim 17, wherein a portion of the gate insulating film and the protective film is etched using the first and second PR patterns as masks to form contact holes exposing the gate pads and the data pads, and then the first PR patterns are removed. And removing the protective film of the pixel region by using the second PR pattern as a mask to expose the gate insulating film of the pixel region. 19. The method of claim 18, wherein the first PR pattern is removed through an ashing process. 18. The method of claim 17, wherein the remaining PR pattern is a second PR pattern.