KR20050056392A - Method of forming metal line in a semiconductor - Google Patents
Method of forming metal line in a semiconductor Download PDFInfo
- Publication number
- KR20050056392A KR20050056392A KR1020030089341A KR20030089341A KR20050056392A KR 20050056392 A KR20050056392 A KR 20050056392A KR 1020030089341 A KR1020030089341 A KR 1020030089341A KR 20030089341 A KR20030089341 A KR 20030089341A KR 20050056392 A KR20050056392 A KR 20050056392A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- metal wiring
- wafer
- via hole
- metal
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 59
- 239000002184 metal Substances 0.000 title claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000007769 metal material Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 29
- 239000011229 interlayer Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 229910001080 W alloy Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 125000001183 hydrocarbyl group Chemical group 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 238000001465 metallisation Methods 0.000 description 12
- 238000005530 etching Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 본 발명의 사상은 웨이퍼에 구비된 다수 개의 반도체 기판 각각에 비아홀 및 금속배선 트렌치를 형성하는 단계, 상기 웨이퍼의 에지영역에 희생막을 형성하는 단계, 상기 결과물 전면에 상기 비아홀 및 금속배선 트렌치를 매립할 금속물질을 형성하는 단계 및 상기 결과물의 비아홀 및 금속배선 트렌치 내에만 금속물질이 증착되도록 평탄화 공정을 수행하여, 비아 및 금속배선을 형성하는 단계를 포함한다. The present invention relates to a method for forming a metal wiring of a semiconductor device, the idea of the present invention is to form a via hole and a metal wiring trench in each of a plurality of semiconductor substrates provided in the wafer, forming a sacrificial film in the edge region of the wafer And forming a metal material to fill the via hole and the metal wiring trench on the entire surface of the resultant, and performing a planarization process so that the metal material is deposited only in the via hole and the metal wiring trench to form the via and the metal wiring. It includes.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 더욱 상세하게는 반도체 소자의 금속배선 형성방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device.
일반적으로, 반도체 소자의 고집적화 및 고밀도화됨에 따라 신뢰성을 가진 반도체소자의 금속배선 형성방법에 대한 기술개발이 요구되고 있다. In general, as the integration and density of semiconductor devices are increased, there is a demand for technology development of a method for forming metal wirings of semiconductor devices with reliability.
이 요구에 부응하기 위해 다마신(Damascene) 공정을 통해 금속배선을 형성하고 있는 데, 이 다마신 공정을 이용할 경우 금속배선의 전기적 절연 및 배선 형성을 위해 CMP 공정과 같은 평탄화 공정을 수행한다. In order to meet this demand, metallization is formed through a damascene process, which uses a planarization process such as a CMP process for electrical insulation and formation of metallization.
그러나 상기 금속배선 형성 공정시 수행되는 CMP 공정시 웨이퍼 에지영역에서는 금속배선 물질의 일부가 제거되지 못하고 남게 되는 문제가 발생한다. 이 금속성 잔류물(residue)이 남게 되는 경우는, 후속 절연막 증착 후 콘택 형성 및 패드 형성 등을 위한 산화막 식각공정 진행시 아킹(arching)현상 등의 문제점을 발생시킨다. However, in the CMP process performed during the metallization process, a portion of the metallization material cannot be removed from the wafer edge region. When the metallic residue remains, problems such as arching may occur during the oxide film etching process for contact formation, pad formation, and the like after the subsequent insulating film deposition.
따라서 반도체 소자의 금속배선 형성 공정시 웨이퍼 에지부분에 잔류하게 되는 금속성 잔류물을 제거하는 방법에 대한 기술 개발이 요구되고 있다. Therefore, there is a need for a technology development for a method of removing metallic residues remaining on the wafer edge portion during the metallization forming process of semiconductor devices.
상술한 문제점을 해결하기 위한 본 발명의 사상은 금속배선 형성 공정시 웨이퍼 에지부분에 잔류하는 금속성 잔류물을 제거할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 있다. An object of the present invention for solving the above problems is to provide a method for forming a metal wiring of a semiconductor device that can remove the metallic residue remaining on the wafer edge portion during the metal wiring forming process.
상술한 목적을 달성하기 위한 본 발명의 사상은 웨이퍼에 구비된 다수 개의 반도체 기판 각각에 비아홀 및 금속배선 트렌치를 형성하는 단계, 상기 웨이퍼의 에지영역에 희생막을 형성하는 단계, 상기 결과물 전면에 상기 비아홀 및 금속배선 트렌치를 매립할 금속물질을 형성하는 단계 및 상기 결과물의 비아홀 및 금속배선 트렌치 내에만 금속물질이 증착되도록 평탄화 공정을 수행하여, 비아 및 금속배선을 형성하는 단계를 포함한다. The idea of the present invention for achieving the above object is to form a via hole and a metal wiring trench in each of a plurality of semiconductor substrates provided in the wafer, forming a sacrificial film in the edge region of the wafer, the via hole on the entire surface of the resultant And forming a metal material to fill the metal wiring trench, and performing a planarization process so that the metal material is deposited only in the resulting via hole and the metal wiring trench, thereby forming the via and the metal wiring.
본 발명의 또 다른 사상은 웨이퍼에 구비된 다수 개의 반도체 기판에 제1 식각 정지막, 제1 층간 절연막, 제2 식각 정지막 및 제2 층간 절연막을 순차적으로 형성하는 단계, 상기 제2 층간 절연막, 제2 식각 정지막, 제1 층간 절연막 및 제1 식각 정지막을 패터닝하여 비아홀 및 금속배선 트렌치를 형성하는 단계, 상기 웨이퍼의 에지영역에 희생막을 형성하는 단계, 상기 결과물 전면에 상기 비아홀 및 금속배선 트렌치를 매립할 금속물질을 형성하는 단계 및 상기 결과물의 비아홀 및 금속배선 트렌치 내에만 금속물질이 증착되도록 평탄화 공정을 수행하여, 비아 및 금속배선을 형성하는 단계를 포함한다. Another idea of the present invention is to sequentially form a first etch stop film, a first interlayer insulating film, a second etch stop film and a second interlayer insulating film on a plurality of semiconductor substrates provided in the wafer, the second interlayer insulating film, Patterning a second etch stop layer, a first interlayer insulating layer, and a first etch stop layer to form a via hole and a metal wiring trench, forming a sacrificial film in an edge region of the wafer, and forming the via hole and the metal wiring trench in the entire surface of the resultant Forming a metal material to bury the metal material; and performing a planarization process so that the metal material is deposited only in the via hole and the metal wiring trench of the resultant, thereby forming the via and metal wiring.
상기 희생막은 HSQ(Hydo-Siles-Quioxane) 및 탄화수소기 중 어느 하나를 함유한 SOG막인 것이 바람직하다. The sacrificial film is preferably an SOG film containing any one of HSQ (Hydo-Siles-Quioxane) and a hydrocarbon group.
상기 SOG막 형성하는 공정을 수행한 후, 상기 SOG막의 물질 내의 카본 및 수분 등을 제거하는 공정을 더 수행하는 것이 바람직하다. After performing the process of forming the SOG film, it is preferable to further perform a process for removing carbon, water, and the like in the material of the SOG film.
상기 SOG막의 물질 내의 카본 및 수분 등을 제거하는 공정은 100~ 200℃ 정도의 온도, 2~ 20분 정도의 시간에서 수행되는 베이크 공정 및 400~ 500℃ 정도의 온도, 20분 ~ 2시간 정도의 시간에서 수행되는 어닐링 공정 중 어느 하나인 것이 바람직하다. The process of removing carbon and moisture in the material of the SOG film is a baking process performed at a temperature of about 100 to 200 ° C., about 2 to 20 minutes, and a temperature of about 400 to 500 ° C., about 20 minutes to 2 hours. It is preferably one of the annealing processes carried out in time.
상기 금속물질은 티타늄(Ti), 티타늄 질화막(TiN), W합금 및 구리 중 어느 하나인 것이 바람직하다. The metal material is preferably any one of titanium (Ti), titanium nitride (TiN), W alloy, and copper.
상기 평탄화 공정은 500~ 1000Å 정도 오버 CMP되도록 수행되는 CMP 공정인 것이 바람직하다. The planarization process is preferably a CMP process that is performed to be over CMP about 500 ~ 1000Å.
상기 웨이퍼의 에지 부분은 상기 웨이퍼의 끝지점에서 상기 웨이퍼의 중심으로 2~ 10mm 정도까지의 영역을 일컫는 것이 바람직하다. The edge portion of the wafer preferably refers to an area of about 2 to 10 mm from the end point of the wafer to the center of the wafer.
이하, 첨부 도면을 참조하여 본 발명의 실시 예를 상세히 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있지만 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안 된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해 제공되어지는 것이다. 또한 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다 또는 접촉하고 있다 라고 기재되는 경우에, 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제 3의 막이 개재되어질 수도 있다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, but the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. In addition, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.
도 1 내지 도 4는 본 발명에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도들이다. 1 to 4 are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.
도 1을 참조하면, 매몰 콘택(C)과 같은 하부 구조가 형성된 반도체 기판(30: A) 상에 제1 식각 정지막(32), 제1 층간 절연막(34), 제2 식각 정지막(36) 및 제2 층간 절연막(38)을 순차적으로 형성한다. Referring to FIG. 1, a first etch stop layer 32, a first interlayer insulating layer 34, and a second etch stop layer 36 are formed on a semiconductor substrate 30 A having a lower structure such as a buried contact C. FIG. ) And the second interlayer insulating film 38 are sequentially formed.
상기 제1 식각 정지막(32)은 이후 콘택홀을 형성하기 위해 진행되는 식각공정에 대한 식각 정지막이고, 제2 식각 정지막(36)은 이후 금속배선 트렌치를 형성하기 위해 진행되는 식각공정에 대한 식각 정지막이다. The first etch stop layer 32 is an etch stop layer for an etching process that is subsequently performed to form a contact hole, and the second etch stop layer 36 is then used for an etching process that is performed to form a metal wiring trench. For etch stop.
상기 제1 및 제2 식각 정지막(32, 36)은 300~ 700Å 정도의 두께로 형성할 수 있고, 제1 층간 절연막(34)은 5000~ 10000Å 정도의 두께로 형성할 수 있고, 제2 층간 절연막(38)은 3000~ 5000Å 정도의 두께로 형성할 수 있다. The first and second etch stop layers 32 and 36 may be formed to have a thickness of about 300 to 700 GPa, and the first interlayer insulating layer 34 may be formed to have a thickness of about 5000 to 10000 GPa, and the second interlayer may be formed. The insulating film 38 can be formed to a thickness of about 3000 to 5000 GPa.
도 2를 참조하면, 상기 제2 층간 절연막(38) 상의 소정 영역에 비아홀을 정의할 제1 포토레지스트 패턴(미도시)을 형성하고, 이를 식각 마스크로 제2 층간 절연막(38), 제2 식각 정지막(36), 제1 층간 절연막(34) 및 제1 식각 정지막(32)을 식각하여 상기 매몰 콘택과 같은 하부구조를 노출하는 비아홀(VH)을 형성한다. Referring to FIG. 2, a first photoresist pattern (not shown) defining a via hole is formed in a predetermined region on the second interlayer insulating layer 38, and the second interlayer insulating layer 38 and the second etching are formed using an etching mask. The stop layer 36, the first interlayer insulating layer 34, and the first etch stop layer 32 are etched to form a via hole VH exposing a substructure such as the buried contact.
상기 제1 포토레지스트 패턴(미도시)을 제거하고, 상기 제2 층간 절연막(38)의 다른 소정 영역에 금속배선 트렌치를 정의하는 제2 포토레지스트 패턴(미도시)을 형성하고, 이를 식각 마스크로 제2 층간 절연막(38) 및 제2 식각 정지막(36)을 식각하여 금속배선 트렌치(MT)를 형성하고, 상기 제2 포토레지스트 패턴(미도시)을 제거한다. The first photoresist pattern (not shown) is removed, and a second photoresist pattern (not shown) defining a metal wiring trench is formed in another predetermined region of the second interlayer insulating layer 38, and the second photoresist pattern (not shown) is used as an etching mask. The second interlayer insulating layer 38 and the second etch stop layer 36 are etched to form a metal wiring trench MT, and the second photoresist pattern (not shown) is removed.
상기 금속배선 트렌치(MT) 및 비아홀(VH)이 형성된 반도체 기판(A)이 구비된 웨이퍼의 에지 부분(B)에만 SOG(spin on glass)공정을 통해 SOG막(40)을 형성한다. The SOG film 40 is formed through a spin on glass (SOG) process only on the edge portion B of the wafer having the semiconductor substrate A on which the metallization trench MT and the via hole VH are formed.
상기 웨이퍼의 에지 부분은 웨이퍼의 끝지점에서 웨이퍼의 중심으로 2~ 10mm 정도까지의 영역을 일컫는다. The edge portion of the wafer refers to an area of about 2 to 10 mm from the end point of the wafer to the center of the wafer.
이 SOG막(40)은 1000~ 5000Å 정도의 두께, HSQ(Hydo-Siles-Quioxane) 또는 탄화수소기 중 어느하나를 함유한 물질로 형성할 수 있다. The SOG film 40 may be formed of a material containing any one of a thickness of about 1000 to 5000 GPa, a Hyd-Siles-Quioxane (HSQ), or a hydrocarbon group.
또한, 상기 SOG막(40)은 플로우(flow) 특성을 갖는 물질을 사용하기 때문에, SOG막 물질 내의 카본 및 수분 등의 제거를 목적으로 이에 대한 증착 완료 후 100~ 200℃ 정도의 온도, 2~ 20분 정도의 시간에서 수행되는 베이크 공정 또는 400~ 500℃ 정도의 온도, 20분 ~ 2시간 정도의 시간에서 수행되는 어닐링 공정을 수행할 수 있다. In addition, since the SOG film 40 uses a material having a flow characteristic, for the purpose of removing carbon and moisture in the SOG film material, a temperature of about 100 to 200 ° C. after the completion of deposition thereof, and The baking process may be performed at a time of about 20 minutes or the annealing process may be performed at a temperature of about 400 to 500 ° C. and a time of about 20 minutes to 2 hours.
또한, 상기 어닐링 공정 또는 베이킹 공정은 N2, Ar등과 같은 불활성가스를 사용하여 수행할 수 있다. In addition, the annealing process or baking process may be performed using an inert gas, such as N2, Ar.
본 발명의 실시 예에서는 상기 SOG막(40)을 금속배선 트렌치(MT) 및 비아홀(VH)이 형성된 반도체 기판이 구비된 웨이퍼 에지부분에 형성하는 바에 대해서만 제시하고 있지만, 상기 SOG막(40)은 금속배선 트렌치(MT) 및 비아홀(VH)이 형성되기 전 반도체 기판이 구비된 웨이퍼 에지부분에 대해서도 형성될 수 있다. In the exemplary embodiment of the present invention, the SOG film 40 is provided only on the edge portion of the wafer having the semiconductor substrate on which the metallization trench MT and the via hole VH are formed. It may also be formed on the wafer edge portion provided with the semiconductor substrate before the metallization trench MT and the via hole VH are formed.
도 3을 참조하면, 상기 결과물 전면에 금속물질(42)을 형성한다. 이 금속물질(42)은 상기 비아홀(VH) 및 금속배선 트렌치(MT)에 형성되고, 상기 웨이퍼 에지부분(B)의 SOG막(40)상부에도 형성된다. 이 SOG막의 형성으로 인해 웨이퍼 에지부분(B)에는 금속물질은 단차를 갖게 된다. Referring to FIG. 3, a metal material 42 is formed on the entire surface of the resultant product. The metal material 42 is formed in the via hole VH and the metal wiring trench MT, and is also formed on the SOG film 40 of the wafer edge portion B. Due to the formation of the SOG film, the wafer edge portion B has a stepped metal material.
상기 금속물질은 티타늄(Ti), 티타늄 질화막(TiN), W합금 및 구리 중 어느 하나 일 수 있다. The metal material may be any one of titanium (Ti), titanium nitride (TiN), W alloy, and copper.
도 4를 참조하면, 상기 제2 층간 절연막(38)이 노출될 때까지 CMP 공정과 같은 평탄화 공정을 수행하여 금속배선(M) 및 비아(V)의 형성을 완료한다. Referring to FIG. 4, a planarization process such as a CMP process is performed until the second interlayer insulating layer 38 is exposed to complete formation of the metal interconnection M and the via V. FIG.
상기 CMP 공정은 500~ 1000Å 정도 오버 CMP되도록 수행될 수 있다. The CMP process may be performed to over CMP about 500 ~ 1000Å.
이 CMP 공정과 같은 평탄화 공정으로 인해, 웨이퍼 에지부분(B)에 형성된 단차를 가진 금속물질 및 SOG막(40)이 제거되므로, 이들의 제거와 동시에 웨이퍼 에지부분(B)에 잔존할 수 있는 금속성 잔류물은 제거된다. Due to the planarization process such as this CMP process, since the metal material and the SOG film 40 having the step formed in the wafer edge portion B are removed, the metal that can remain in the wafer edge portion B at the same time as their removal is removed. The residue is removed.
또한, 상기 평탄화 공정으로 인해, 웨이퍼 에지부분(B)에 형성된 단차를 가진 금속물질 및 SOG막(40)의 제거는, 금속성 잔류물뿐만 아니라 웨이퍼 에지부분(B)에 잔존할 수 있는 잔류물 또한 제거된다. In addition, due to the planarization process, the removal of the metal material and the SOG film 40 having the step formed in the wafer edge portion B may include not only metallic residues but also residues that may remain in the wafer edge portion B. Removed.
본 발명에 의하면, 웨이퍼 에지영역에 SOG막을 형성한 후 금속배선 형성 CMP 공정을 수행함으로써, 금속배선 형성 공정시 웨이퍼 에지부분에 잔류하는 금속성 잔류물을 제거할 수 있다. According to the present invention, by forming the SOG film in the wafer edge region and then performing the metallization forming CMP process, it is possible to remove metallic residues remaining on the wafer edge portion during the metallization forming process.
이상에서 살펴본 바와 같이 본 발명에 의하면, 웨이퍼 에지영역에 SOG막을 형성한 후 금속배선 형성 CMP 공정을 수행함으로써, 금속배선 형성 공정시 웨이퍼 에지부분에 잔류하는 금속성 잔류물을 제거할 수 있는 효과가 있다.As described above, according to the present invention, by forming the SOG film in the wafer edge region and then performing the metallization forming CMP process, there is an effect of removing the metallic residue remaining on the wafer edge portion during the metallization forming process. .
본 발명은 구체적인 실시 예에 대해서만 상세히 설명하였지만 본 발명의 기술적 사상의 범위 내에서 변형이나 변경할 수 있음은 본 발명이 속하는 분야의 당업자에게는 명백한 것이며, 그러한 변형이나 변경은 본 발명의 특허청구범위에 속한다 할 것이다.Although the present invention has been described in detail only with respect to specific embodiments, it is apparent to those skilled in the art that modifications or changes can be made within the scope of the technical idea of the present invention, and such modifications or changes belong to the claims of the present invention. something to do.
도 1 내지 도 4는 본 발명에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도들이다. 1 to 4 are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
30: 반도체 기판 32: 제1 식각정지막30: semiconductor substrate 32: first etch stop film
34: 제1 층간 절연막 36: 제2 식각정지막34: first interlayer insulating film 36: second etch stop film
38: 제2 층간 절연막 40: SOG막38: second interlayer insulating film 40: SOG film
42: 금속물질 M: 금속배선42: metal material M: metal wiring
V: 비아 A: 반도체 기판V: Via A: Semiconductor Substrate
B: 웨이퍼의 에지부분 B: edge of wafer
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030089341A KR20050056392A (en) | 2003-12-10 | 2003-12-10 | Method of forming metal line in a semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030089341A KR20050056392A (en) | 2003-12-10 | 2003-12-10 | Method of forming metal line in a semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20050056392A true KR20050056392A (en) | 2005-06-16 |
Family
ID=37251000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020030089341A KR20050056392A (en) | 2003-12-10 | 2003-12-10 | Method of forming metal line in a semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20050056392A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100632658B1 (en) * | 2004-12-29 | 2006-10-12 | 주식회사 하이닉스반도체 | Method of forming metal line in semiconductor device |
-
2003
- 2003-12-10 KR KR1020030089341A patent/KR20050056392A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100632658B1 (en) * | 2004-12-29 | 2006-10-12 | 주식회사 하이닉스반도체 | Method of forming metal line in semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100482180B1 (en) | Fabricating method of semiconductor device | |
| JP2007074004A (en) | Inter-layer insulating structure and its forming method | |
| US6297158B1 (en) | Stress management of barrier metal for resolving CU line corrosion | |
| KR100791697B1 (en) | Metal line structure and method for forming metal line of semiconductor device | |
| KR100333712B1 (en) | A method for forming damascene type metal wire in semiconductor device | |
| KR20050056392A (en) | Method of forming metal line in a semiconductor | |
| KR20050067823A (en) | Method of forming metal line in a semiconductor | |
| KR20090024854A (en) | Metal line and method for fabricating metal line of semiconductor device | |
| US6143644A (en) | Method to prevent passivation from keyhole damage and resist extrusion | |
| JPH08181146A (en) | Manufacture of semiconductor device | |
| KR100307827B1 (en) | Metal wiring contact formation method of semiconductor device | |
| KR100571696B1 (en) | Method For Manufacturing Semiconductor Devices | |
| KR20100036008A (en) | Method for forming metal wiring of semiconductor device | |
| KR20000056852A (en) | Method of fabricating a metal-interconnect structure in integrated circuit | |
| KR100509434B1 (en) | Method for improving photo resist adhesion | |
| KR100652303B1 (en) | Method for forming metal line of semiconductor device | |
| KR100575359B1 (en) | Semiconductor Device And Method For Manufacturing The Same | |
| KR100349346B1 (en) | Method of defining a wire pattern in a semiconductor device | |
| KR100800667B1 (en) | Method for fabricating semiconductor device | |
| KR20040050118A (en) | Method of forming a metal line in a semiconductor device | |
| KR100358569B1 (en) | A method for forming a metal line of semiconductor device | |
| KR100274346B1 (en) | Method of forming a metal wiring in a semiconductor device | |
| KR100372817B1 (en) | method of contacting metal lines of semiconductor device | |
| KR20050009575A (en) | Method of forming metal line in semiconductor device | |
| KR20060030200A (en) | Method of forming a metal wiring layer in a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |