KR20050055348A - Driving apparatus of display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive device for a display device, and more particularly to a drive device for a display device that can reduce the number of connection wirings to the outside.

A plurality of pixels, a switching control signal generator for generating a switching control signal based on an input signal from the outside, a data driver for outputting a data voltage, a plurality of data lines for transmitting the data voltage to the pixel, and the switching control And a plurality of transfer gates configured to transfer the data voltage to the data line according to a signal.

In this way, by reducing the number of signals input from the outside it is possible to reduce the number of wiring for transmitting the signal to reduce the process cost or cost.

Description

Drive device for display device {DRIVING APPARATUS OF DISPLAY DEVICE}

The present invention relates to a driving device of a display device.

A liquid crystal display, an EL (electro luminescence) display, or the like includes a plurality of pixels arranged in a matrix form. Each pixel includes a switching element that selectively receives an image signal, and a three-terminal element such as a MOS transistor is mainly used as the switching element. The display device also includes a plurality of gate lines and a plurality of data lines connected to the switching elements, each gate line delivering a gate-on voltage for turning on the switching elements, respectively, and each data line through each turned-on switching element for each pixel. Pass the image signal on.

The display device also includes a gate driver for applying a gate-on voltage to the gate line, a data driver for applying an image signal to the data line, and a signal controller for controlling the gate driver.

The data driver consists of a plurality of data driver ICs, and several data lines are connected to one data driver IC.

In this case, in order to reduce the number of data lines to be connected, a 1: n demultiplexing scheme in which one output and a plurality of data lines of the data driving IC are connected is used. In this connection, a transmission element is usually used as a switching element. And a signal for controlling the transfer gate is applied by an external timing generator to adjust the on / off timing of each transfer gate.

On the other hand, as the number of data lines increases, the number of switching elements connected to the data driving IC also increases. In this case, the number of control signals input from the outside gradually increases, thereby increasing the wiring area for connecting to the outside. As a result, there may be an increase in cost and difficulty in implementing a chip on glass (COG).

Accordingly, an object of the present invention is to provide a driving device for a display device that can reduce connection wiring to the outside.

According to an aspect of the present invention, a driving device of a display device includes a plurality of pixels, and includes a switching control signal generator and a data voltage generating a switching control signal based on an input signal from an external source. And a plurality of data lines for transmitting the data voltages to the pixels, and a plurality of transfer gates for transmitting the data voltages to the data lines according to the switching control signal.

The input signal may include first to fourth control signals, and the switching control signal generator may include a plurality of logic gates to which the first to fourth control signals are applied, and an inverter to invert the fourth control signal. It may include.

In addition, the first to third control signals may be generated twice each during one horizontal period H, and the fourth control signal may be inverted at a period of 1 / 2H.

Here, the logic gate includes first to sixth logic gates, and the first to third logic gates receive one of the first to third control signals and the fourth control signal, respectively, and the fourth The sixth to sixth logic gates preferably receive one of the first to third control signals and an inverted signal of the fourth control signal.

Meanwhile, the first to third logic gates generate first to third switching control signals during the first half H, and the fourth to sixth logic gates switch to fourth through sixth h during the second half H. A switching control signal can be generated.

In this case, the transfer gate may include first to sixth transfer gates, and the first to sixth transfer gates may be sequentially applied with the first to sixth switching control signals.

Meanwhile, the logic gate may be an AND gate.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

A liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. It includes the line (D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel must display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n .

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal. It consists of a circuit.

The signal controller 600 generates control signals for controlling operations of the gate driver 400 and the data driver 500, and provides the corresponding control signals to the gate driver 400 and the data driver 500.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal, and adjusts the image signals R, G, and B to match the operating conditions of the liquid crystal panel assembly 300. After appropriately processing, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signals R ', G', and B 'are sent to the data driver 500.

In addition, the switching control signal generator 650 of the signal controller 600 may turn on / off the transmission gates TG1-TG6 based on an input control signal CONTSW from an external timing generator (not shown). It generates and sends a switching control signal CONT3 for controlling, which will be described in detail later.

The gate control signal CONT1 includes a vertical synchronization start signal STV indicating the start of output of the gate on pulse (gate on voltage section), a gate clock signal CPV for controlling the output timing of the gate on pulse, and a gate on pulse. An output enable signal OE or the like that defines a width.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The data driver 500 sequentially receives and shifts image data R ', G', and B 'corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and generates a gray voltage. The image data R ', G', B 'is converted into the corresponding data voltage by selecting the gray voltage corresponding to each of the image data R', G ', and B' among the gray voltages from the unit 800. Then, it is applied to the corresponding data line D ₁ -D _m .

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. When the switching element Q connected to the () is turned on, the data voltage applied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned on switching element Q.

The difference between the data voltage applied to the pixel and the common voltage V _com is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage. As a result, the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

After one horizontal period (or “1H”) (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 are next. The same operation is repeated for the pixels in the row. In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarity of the data voltage flowing through one data line may be changed (“column inversion”) or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS within one frame ( "Dot reversal")

Next, the driving device of the display device will be described in detail with reference to FIGS. 3 to 6.

3 is a diagram illustrating a connection between a data driver and a transmission gate according to an exemplary embodiment of the present invention, and FIG. 4 is a circuit diagram of a switching control signal generator according to an exemplary embodiment of the present invention. 5 is a timing diagram of the input signal shown in FIG. 4, and FIG. 6 is a waveform diagram of the output signal shown in FIG.

As shown in FIG. 3, a plurality of data lines D1-D12 are connected to the data driving IC through the transfer gates TG1-TG6.

The transfer gates TG1-TG6 are turned on / off according to the switching control signals SW1-SW6 generated by the switching control signal generator 650, and the data voltages of the corresponding pixels are turned on through the turned on transfer gates TG1-TG6. Is applied to.

Then, after the structure and operation of the switching control signal generator 650 will be described, the overall operation will be described.

As shown in FIG. 4, the switching control signal generator 650 according to an exemplary embodiment of the present invention includes a plurality of AND gates AND1 -AND6 and an inverter INV.

The AND gates AND1-AND3 receive input signals S1-S3 and CON generated by an external timing generator (not shown), and the AND gates AND4-AND6 are connected to the input signals S1-S3. The inverted input signal CONB is applied.

The high period of the gate clock signal CPV has a length of 1H, and the input signals S1-S3 are generated twice each within 1H. The input signal CON has a period of 1H, and the high and low are repeated by 1 / 2H.

First, when the input signals S1 and CON are applied, the AND gate AND1 outputs a section in which both signals are high to output the switching control signal SW1 shown in FIG. 6. The AND gates AND2 and AND3 also perform the same operation when the input signals SW2, SW3, and CON are sequentially input, and output the switching control signals SW2 and SW3. At this time, the rest of the AND gates SW4-SW6 are inputted with the inverted input signal CONB, that is, a signal corresponding to a row, so the output is kept low.

Next, when 1 / 2H passes, the input signal CON is inverted, and the input signal CON and the input signals S1-S3 that are low are applied to the AND gates AND1 -AND3 to output a low signal. The inverted high signal and the input signals S1-S3 are input to the AND4-AND6 and the switching control signal SW4-SW6 is generated as shown in FIG. 6.

The switching control signals SW1-SW6 generated in this way are sequentially applied to the transfer gates TG1-TG6 shown in FIG. 3 and sequentially turned on, and a data voltage is applied to the corresponding pixel.

Although the driving device of the display device illustrated in FIG. 4 is located in the signal controller 600 in the exemplary embodiment of the present invention, it may be implemented as a separate chip.

In this way, even if the number of transmission gates TG1-TG6 increases, the number of signals input from the outside can be greatly reduced. In other words, in the conventional method, as many as the number of switching elements externally, for example, in the case of FIG. 6, six switching control signals should be applied. Therefore, since the switching control signal must be applied as the switching element increases, the connection wiring with the outside increases.

However, according to the embodiment of the present invention, it is possible to reduce the number of connection wirings from six to four. This will not increase the number of connection wirings to the outside even if the number of transfer gates increases in the future, thereby reducing the process cost or cost.

As described above, when the switching control signal generation unit is separately provided in the signal controller or as a separate chip to generate the switching control signal, connection wiring with the outside can be reduced.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a connection between a data driver and a transmission gate according to an exemplary embodiment of the present invention.

4 is a circuit diagram of a switching control signal generator according to an exemplary embodiment of the present invention.

FIG. 5 is a timing diagram of the input signal shown in FIG. 4.

6 is a waveform diagram of an output signal shown in FIG. 4.

Claims (7)

A driving device of a display device including a plurality of pixels, A switching control signal generator for generating a switching control signal based on an input signal from an external device, A data driver for outputting a data voltage, A plurality of data lines transferring the data voltage to the pixel, and A plurality of transfer gates transferring the data voltage to the data line according to the switching control signal Driving device for a display device comprising a. In claim 1, The input signal includes first to fourth control signals, The switching control signal generator is A plurality of logic gates receiving the first to fourth control signals, and An inverter for inverting the fourth control signal Driving device for a display device comprising a. In claim 2, The first to third control signals are generated twice each during one horizontal period (H), and the fourth control signal is inverted in a period of 1 / 2H. In claim 3, The logic gate includes first to sixth logic gates, The first to third logic gates receive one of the first to third control signals and the fourth control signal, respectively, The fourth to sixth logic gates receive one of the first to third control signals and an inverted signal of the fourth control signal, respectively. Drive device for display device. In claim 4, The first to third logic gates generate first to third switching control signals during the first half H, The fourth to sixth logic gates generate switching fourth to sixth switching control signals during the second half of H. Drive device for display device. In claim 5, The transfer gate includes first to sixth transfer gates, The first to sixth transmission gates sequentially receive the first to sixth switching control signals. Drive device for display device. In claim 6, And the logic gate is an AND gate.