KR20050054117A - A manufacturing method for copper metal layer of semiconductor device - Google Patents
A manufacturing method for copper metal layer of semiconductor device Download PDFInfo
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- KR20050054117A KR20050054117A KR1020030087441A KR20030087441A KR20050054117A KR 20050054117 A KR20050054117 A KR 20050054117A KR 1020030087441 A KR1020030087441 A KR 1020030087441A KR 20030087441 A KR20030087441 A KR 20030087441A KR 20050054117 A KR20050054117 A KR 20050054117A
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- tantalum nitride
- interlayer insulating
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- 239000010949 copper Substances 0.000 title claims abstract description 38
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 33
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 title description 6
- 239000002184 metal Substances 0.000 title description 6
- 238000000034 method Methods 0.000 claims abstract description 41
- 230000004888 barrier function Effects 0.000 claims abstract description 29
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000011229 interlayer Substances 0.000 claims abstract description 22
- 230000008569 process Effects 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000005498 polishing Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 33
- 239000002243 precursor Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 22
- 238000000231 atomic layer deposition Methods 0.000 description 12
- 239000007789 gas Substances 0.000 description 12
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- -1 ethylmethylamino Chemical group 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- MTHYQSRWPDMAQO-UHFFFAOYSA-N diethylazanide;tantalum(5+) Chemical compound CCN(CC)[Ta](N(CC)CC)(N(CC)CC)(N(CC)CC)N(CC)CC MTHYQSRWPDMAQO-UHFFFAOYSA-N 0.000 description 1
- VSLPMIMVDUOYFW-UHFFFAOYSA-N dimethylazanide;tantalum(5+) Chemical compound [Ta+5].C[N-]C.C[N-]C.C[N-]C.C[N-]C.C[N-]C VSLPMIMVDUOYFW-UHFFFAOYSA-N 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명의 실시예에 따른 반도체 소자의 구리 배선 제조 방법은 반도체 기판 위에 층간 절연막을 형성하는 단계, 층간 절연막에 접촉홀을 형성하는 단계, 접촉홀을 포함하는 층간 절연막 위에 ALD 방법으로 탄탈륨 나이트라이드막을 형성하는 단계, 탄탈륨 나이트라이드막에 실리콘 계열의 가스를 주입하여 탄탈륨 나이트라이드막을 탄탈륨 실리콘 나이트라이드막으로 변화시켜 베리어막을 형성하는 단계, 베리어막 위에 도전막을 증착하여 접촉홀을 매립하는 단계, 도전막에 어닐링 공정을 진행하는 단계, 도전막 및 베리어막을 층간 절연막의 상부 표면이 드러나는 시점까지 화학 기계적 연마하여 평탄화하는 단계를 포함한다.In the method for manufacturing a copper wiring of a semiconductor device according to an embodiment of the present invention, forming a layered insulating film on the semiconductor substrate, forming a contact hole in the interlayer insulating film, a tantalum nitride film on the interlayer insulating film including the contact hole by the ALD Forming a barrier film by injecting a silicon-based gas into the tantalum nitride film to form a barrier film by depositing a conductive film on the barrier film; Performing an annealing process, and chemically polishing and polishing the conductive film and the barrier film to the point where the upper surface of the interlayer insulating film is exposed.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는 구리를 이용하여 반도체 소자의 금속 배선층을 형성하는 반도체 소자의 구리 배선 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a copper wiring of a semiconductor device in which a metal wiring layer of a semiconductor device is formed using copper.
최근 반도체 소자가 집적화되고 공정 기술력이 향상되면서 소자의 동작 속도나 저항, 금속 간의 기생 용량 등의 특성을 개선시키기 위한 일환으로 기존의 알루미늄 배선 대신에 구리 배선 공정이 제안되었다. 또한, 층간 절연막으로 기존의 산화막 대신 저유전상수(Low-K) 물질이 차세대 소자의 배선 공정으로 각광을 받고 있다. Recently, as semiconductor devices have been integrated and process technology has been improved, a copper wiring process has been proposed in place of existing aluminum wiring as part of improving characteristics of device operation speed, resistance, and parasitic capacitance between metals. In addition, a low dielectric constant (Low-K) material is being spotlighted as a wiring process of next-generation devices as an interlayer insulating film instead of a conventional oxide film.
또한, 이러한 구리와 저유전상수 물질을 이용한 배선 공정의 경우 구리의 식각 특성이 매우 열악하므로 기존의 식각 공정 대신 다마신(damascene) 공정이 구리 배선에 적합한 공정으로 이용되고 있다. In addition, in the wiring process using the copper and the low dielectric constant material, since the etching property of copper is very poor, the damascene process is used as a process suitable for copper wiring instead of the conventional etching process.
종래 기술에 따른 반도체 소자의 구리 배선 제조 방법에 따르면, 층간 절연막 내에 비아홀과 배선 형성을 위한 트렌치를 포함하는 접촉홀을 형성한 다음 접촉홀이 충분히 매립되도록 구리막을 두껍게 증착한다. 그리고 구리막에 어닐링(annealing) 공정을 진행하여 구리막 증착 시 유입된 불순물을 제거한 다음 층간 절연막의 상부 표면이 드러나는 시점까지 화학 기계적 연마하여 접촉홀 내에 매립되는 구리 배선을 형성한다.According to the method of manufacturing a copper wiring of a semiconductor device according to the prior art, a contact hole including a via hole and a trench for forming a wiring is formed in an interlayer insulating film, and then a copper film is thickly deposited so that the contact hole is sufficiently filled. In addition, an annealing process is performed on the copper film to remove impurities introduced during the deposition of the copper film, followed by chemical mechanical polishing until the upper surface of the interlayer insulating film is exposed to form a copper wiring embedded in the contact hole.
또한, 구리가 층간 절연막으로 확산하는 것을 방지하기 위해 구리막을 증착하기 전에 접촉홀 내면에 탄탈륨 실리콘 나이트라이드(TaSiN)를 증착하여 확산 방지막을 형성한다. 이때, 확산 방지막을 형성하는 방법으로 PVD(physical Vapor Deposition) 방법 또는 CVD(Chemical Vapor Deposition) 방법을 주로 이용한다.In addition, in order to prevent the diffusion of copper into the interlayer insulating film, a tantalum silicon nitride (TaSiN) is deposited on the inner surface of the contact hole before the copper film is deposited to form a diffusion barrier. In this case, as a method of forming the diffusion barrier, a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method is mainly used.
먼저, PVD 방법에 의한 확산 방지막은 TaSi를 물리적으로 기상화하는 동시에 질소(N)와 반응시켜 탄탈륨 실리콘 나이트라이드(TaSiN)를 증착하여 형성한다. 이와 같이, PVD 방법은 제조 공정은 용이하나 Si(실리콘)이 확산 방지막 내에 다결정 상태로 존재하여 구리(Cu) 따위의 도전층과 접할 때, 구리가 쉽게 확산되어 확산 방지막과 도전층의 계면에 Cu3Si와 같은 화학 반응층을 형성한다. 이때, Cu3Si와 같은 화학 반응층은 누설 전류를 증가시켜 소자의 특성을 떨어뜨린다. 또한, PVD 방법은 높은 애스펙트 비(aspect ratio)를 요구하는 소자에서는 스텝 커버리지(step coverage)를 확보할 수 없게 되어 확산 방지막이 불량하게 형성되는 문제가 있다.First, the diffusion barrier layer by the PVD method is formed by depositing tantalum silicon nitride (TaSiN) by physically vaporizing TaSi and reacting with nitrogen (N). As described above, the PVD method is easy to manufacture, but when Si (silicon) is present in a polycrystalline state in the diffusion barrier and is in contact with a conductive layer such as copper (Cu), copper is easily diffused to form Cu at the interface between the diffusion barrier and the conductive layer. A chemical reaction layer such as 3 Si is formed. At this time, a chemical reaction layer such as Cu 3 Si increases the leakage current and degrades the device characteristics. In addition, the PVD method has a problem in that a step coverage cannot be secured in devices requiring high aspect ratios, so that a diffusion barrier is poorly formed.
이어 CVD 방법에 의한 확산 방지막은 TaSiN을 형성하기 위한 전구체(precursor)들을 반응 용기 속에 연속적으로 투입하여 TaSiN을 형성하기 위한 전구체가 기판 위에 증착하여 형성된다. 그러나, 전구체는 각종 유기 잔재물을 포함하고 있기 때문에 이를 이용하여 확산 방지막을 형성하게 되면 비저항이 높아진다. 그 결과, CVD 방법에 의한 확산 방지막 또한 소자의 특성 및 신뢰성이 떨어뜨리는 문제가 있다.Subsequently, the diffusion barrier film by the CVD method is formed by continuously depositing precursors for forming TaSiN into a reaction vessel and depositing a precursor for forming TaSiN on a substrate. However, since the precursor contains various organic residues, the specific resistance becomes high when the diffusion barrier is formed by using the precursor. As a result, there is a problem that the diffusion barrier film by the CVD method also degrades the characteristics and reliability of the device.
본 발명이 이루고자 하는 기술적 과제는 반도체 소자가 고집적화됨에 따라 발생하는 확산 방지막의 결함을 제거하여 소자의 특성 및 동작을 안정화시킬 수 있는 반도체 소자의 구리 배선 제조 방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for manufacturing a copper wiring of a semiconductor device capable of stabilizing characteristics and operation of the device by eliminating defects of a diffusion barrier film generated as the semiconductor device is highly integrated.
이러한 과제를 이루기 위하여 본 발명에서는 다음과 같은 반도체 소자의 구리 배선 제조 방법을 마련한다.In order to achieve such a problem, the present invention provides a method for manufacturing a copper wiring of a semiconductor device as follows.
보다 상세하게는 반도체 기판 위에 층간 절연막을 형성하는 단계, 층간 절연막에 접촉홀을 형성하는 단계, 접촉홀을 포함하는 층간 절연막 위에 ALD 방법으로 탄탈륨 나이트라이드막을 형성하는 단계, 탄탈륨 나이트라이드막에 실리콘 계열의 가스를 주입하여 탄탈륨 나이트라이드막을 탄탈륨 실리콘 나이트라이드막으로 변화시켜 베리어막을 형성하는 단계, 베리어막 위에 도전막을 증착하여 접촉홀을 매립하는 단계, 도전막에 어닐링 공정을 진행하는 단계, 도전막 및 베리어막을 층간 절연막의 상부 표면이 드러나는 시점까지 화학 기계적 연마하여 평탄화하는 단계를 포함하여 이루어지는 반도체 소자의 구리 배선 제조 방법을 마련한다.More specifically, forming an interlayer insulating film on a semiconductor substrate, forming a contact hole in the interlayer insulating film, forming a tantalum nitride film on the interlayer insulating film including the contact hole by the ALD method, silicon based on the tantalum nitride film Transforming the tantalum nitride film into a tantalum silicon nitride film by injecting a gas to form a barrier film, depositing a conductive film on the barrier film, filling a contact hole, performing an annealing process on the conductive film, a conductive film and A method of manufacturing a copper wiring for a semiconductor device, the method comprising: planarizing the barrier film by chemical mechanical polishing until the upper surface of the interlayer insulating film is exposed.
또한 ALD 방법에 의한 탄탄륨 나이트라이드막의 형성은 ALD 방법에 의해 수십Å 이하의 두께를 가지는 탄탈륨 나이트라이드를 반복 증착하여 원하는 두께의 탄탈륨 나이트라이드막을 형성하는 것이 바람직하다.In addition, the formation of the tantalum nitride film by the ALD method is preferably repeated deposition of tantalum nitride having a thickness of several tens of micrometers or less by the ALD method to form a tantalum nitride film having a desired thickness.
또한 ALD 방법에 의한 탄탈륨 나이트라이드막의 형성은 TBTDET, PDEAT, PDMAT 또는 PEMAT의 프리커셔를 이용하는 것이 바람직하다.In addition, it is preferable to use the precursor of TBTDET, PDEAT, PDMAT, or PEMAT for formation of a tantalum nitride film by the ALD method.
또한 프리커셔에 의한 탄탈륨 나이트라이드막의 형성은 170~500℃의 온도 조건에서 수행하는 것이 바람직하다.In addition, the formation of the tantalum nitride film by the precursor is preferably carried out at a temperature of 170 ~ 500 ℃.
또한 실리콘 계열의 가스는 SiH4 가스를 사용하는 것이 바람직하다.In addition, it is preferable to use SiH 4 gas as the silicon-based gas.
또한 실리콘 계열의 가스는 30~700Torr의 압력 조건 하에서 10초~120초 주입하는 것이 바람직하다.In addition, the silicon-based gas is preferably injected for 10 seconds to 120 seconds under a pressure condition of 30 ~ 700 Torr.
이하, 첨부한 도면을 참고로 하여 본 발명의 실시예에 대하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세히 설명한다. 그러나 본 발명은 여러 가지 상이한 형태로 구현될 수 있으며 여기에서 설명하는 실시예에 한정되지 않는다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.
도면에서 여러 층 및 영역을 명확하게 표현하기 위하여 두께를 확대하여 나타내었다. 명세서 전체를 통하여 유사한 부분에 대해서는 동일한 도면 부호를 붙였다. 층, 막, 영역, 판 등의 부분이 다른 부분 "위에" 있다고 할 때, 이는 다른 부분 "바로 위에" 있는 경우뿐 아니라 그 중간에 또 다른 부분이 있는 경우도 포함한다. 반대로 어떤 부분이 다른 부분 "바로 위에" 있다고 할 때에는 중간에 다른 부분이 없는 것을 뜻한다.In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.
먼저, 본 발명의 실시예에 따른 반도체 소자를 첨부된 도면을 참고로 하여 상세하게 설명한다.First, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명의 한 실시예에 따른 반도체 소자의 구리 배선을 개략적으로 도시한 단면도이다.1 is a cross-sectional view schematically illustrating a copper wiring of a semiconductor device according to an exemplary embodiment of the present invention.
도 1에 도시한 바와 같이, 금속 배선(110) 따위의 하부 구조가 형성되어 있는 반도체 기판(100) 위에 층간 절연막(120)이 형성되어 있다. 층간 절연막(120)은 저유전상수의 절연 물질로 이루어지며, 금속 배선(110)의 일부분을 드러내는 접촉홀(130)을 가진다. 이때, 접촉홀(130)은 상하부 배선층을 연결하기 위한 비아홀과 상부 배선층이 형성되는 트렌치로 이루어진 다마신 패턴 또는 상부 배선층이 형성되는 트렌치만으로 이루어진 다마신 패턴으로 형성할 수 있다.As shown in FIG. 1, an interlayer insulating layer 120 is formed on a semiconductor substrate 100 on which a lower structure such as the metal wiring 110 is formed. The interlayer insulating layer 120 is made of an insulating material having a low dielectric constant and has a contact hole 130 exposing a portion of the metal wire 110. In this case, the contact hole 130 may be formed as a damascene pattern consisting of a via hole for connecting the upper and lower wiring layers and a trench in which the upper wiring layer is formed, or a damascene pattern consisting of only a trench in which the upper wiring layer is formed.
층간 절연막(120)의 접촉홀(130)의 내면에는 확산 방지막(150)이 형성되어 있다. 확산 방지막(150)은 ALD(Atomic Layer Deposion) 방법에 의해 형성된 탄탈륨 실리콘 나이트라이드(TaSiN)막으로 형성되어 있다.The diffusion barrier 150 is formed on an inner surface of the contact hole 130 of the interlayer insulating layer 120. The diffusion barrier 150 is formed of a tantalum silicon nitride (TaSiN) film formed by an atomic layer deposition (ALD) method.
그리고, 확산 방지막(150) 위에는 구리(Cu) 등의 도전막으로 이루어져 있으며 접촉홀(130)을 매립하는 상부 배선(165)이 형성되어 있다.The upper wiring 165 is formed of a conductive film such as copper (Cu) and fills the contact hole 130 on the diffusion barrier 150.
이상 설명한 본 발명의 실시예에 따른 반도체 소자의 구리 배선 제조하는 방법에 대하여 첨부한 도면을 참조하여 상세히 설명한다.A method of manufacturing a copper wiring of a semiconductor device according to an embodiment of the present invention described above will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명의 일 실시예에 따른 반도체 소자의 구리 배선 제조 방법을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a copper wiring of a semiconductor device according to an embodiment of the present invention.
먼저, 도 2a에 도시한 바와 같이, 하부 배선층(110)이 형성되어 있는 반도체 기판(100) 위에 저유전상수의 절연체를 이용하여 층간 절연막(120)을 형성한다. 그리고, 사진 및 식각 공정을 진행하여 하부 배선층(110)의 일부분을 드러내는 접촉홀(130)을 형성한다. 이때, 접촉홀(130)은 상하부 배선층을 연결하기 위한 비아홀과 상부 배선층이 형성되는 트렌치로 이루어진 듀얼 다마신 패턴 또는 상부 배선층이 형성되는 트렌치만으로 이루어진 싱글 다마신 패턴으로 형성할 수 있다.First, as shown in FIG. 2A, the interlayer insulating layer 120 is formed on the semiconductor substrate 100 on which the lower wiring layer 110 is formed by using an insulator of low dielectric constant. In addition, the contact hole 130 exposing a part of the lower wiring layer 110 is formed by performing a photo and etching process. In this case, the contact hole 130 may be formed as a dual damascene pattern formed of a via hole for connecting the upper and lower interconnection layers and a trench in which the upper interconnection layer is formed, or a single damascene pattern composed of only a trench in which the upper interconnection layer is formed.
이어 도 2b에 도시한 바와 같이, 접촉홀(130) 내부를 포함하여 층간 절연막(120) 위에 종래 PVD 또는 CVD 방법과는 달리 ALD 방법으로 탄탈륨 나이트라이드(TaN)막(141)을 형성한다.2B, a tantalum nitride (TaN) film 141 is formed on the interlayer insulating film 120 including the inside of the contact hole 130 by the ALD method, unlike the conventional PVD or CVD method.
이때 ALD 방법에 의한 탄탈륨 나이트라이드막(141)의 형성은, TBTDET(tertbutylimido (trisdiethylamide) tantalum), PDEAT(pentakis (diethylamide) tantalum), PDMAT(pentakis (dimethylamide) tantalum), 또는 PEMAT(pentakis (ethylmethylamino) tantalum) 등의 프리커셔(precusor)(141)를 170℃ 내지 500℃의 온도에서 수 내지 수십Å의 두께로 증착하며, 이러한 ALD 방법에 의한 프리커셔(141, 142, 143)의 증착 공정을 반복 진행하여 도 2c에서와 같이 원하는 두께의 탄탈륨 나이트라이드막(140)을 형성한다.At this time, the formation of the tantalum nitride film 141 by the ALD method is TBTDET (tertbutylimido (trisdiethylamide) tantalum), PDEAT (pentakis (diethylamide) tantalum), PDMAT (pentakis (dimethylamide) tantalum), or PEMAT (pentakis (ethylmethylamino) a precursor (141) such as tantalum) is deposited to a thickness of several to several tens of microseconds at a temperature of 170 ° C to 500 ° C, and the deposition process of the precursors 141, 142, and 143 by the ALD method is repeated. Proceeding to form a tantalum nitride film 140 of a desired thickness as shown in Figure 2c.
이어 도 2d에 도시한 바와 같이, ALD 방법에 의해 형성된 탄탈륨 나이트라이드(TaN)막(140)에 실리콘(Si) 계열 가스를 주입하여 탄탈륨 나이트라이드막(140)을 탄탈륨 실리콘 나이트라이드(TaSiN)막(150)으로 변화시킨다. 이때, 실리콘 계열의 가스는 90~300Torr의 압력에서 10초~120초 가량 주입한다. 또한, 실리콘(Si) 계열 가스는 SiH4 가스를 사용하는 것이 바람직하다.Subsequently, as shown in FIG. 2D, a silicon (Si) -based gas is injected into the tantalum nitride (TaN) film 140 formed by the ALD method to convert the tantalum nitride film 140 into a tantalum silicon nitride (TaSiN) film. Change to 150. At this time, the silicon-based gas is injected for about 10 seconds to 120 seconds at a pressure of 90 ~ 300 Torr. In addition, it is preferable to use SiH 4 gas as the silicon (Si) -based gas.
SiH4 가스는 탄탈륨 나이트라이드와 반응하여 탄탈륨 실리콘 나이트라이드막을 형성하는 동시에 SiH4 가스의 수소 화합물이 탄탈륨 나이트라이드막 형성 시, 유입된 카본(C) 등의 불순물과 반응하여 불순물을 제거하는 역할을 한다.SiH 4 gas reacts with tantalum nitride to form a tantalum silicon nitride film, and the hydrogen compound of SiH 4 gas reacts with impurities such as carbon (C) introduced to remove impurities when forming a tantalum nitride film. do.
그 후 도 2e에 도시한 바와 같이, 탄탈륨 실리콘 나이트라이드막의 베리어(150)을 포함하는 층간 절연막(120) 위에 접촉홀(130)이 충분히 매립되도록 구리(Cu) 등의 도전막(160)을 두껍게 증착한다.After that, as shown in FIG. 2E, the conductive film 160 such as copper (Cu) is thickened so that the contact holes 130 are sufficiently buried on the interlayer insulating film 120 including the barrier 150 of the tantalum silicon nitride film. Deposit.
다음, 도전막(160)에 어닐링 공정을 진행하여 도전막(160) 증착 시, 유입된 불순물을 제거한다. Next, an annealing process is performed on the conductive layer 160 to remove impurities introduced during the deposition of the conductive layer 160.
이어 도 1에 도시한 바와 같이, 층간 절연막(120)의 상부 표면이 드러나는 시점까지 화학 기계적 연마하여 결과물의 표면을 평탄화한다. 그러면, 도전막이 접촉홀(130) 내에만 존재하게 되어 도전막으로 이루어진 반도체 소자의 구리 배선(165)이 완성된다.Subsequently, as shown in FIG. 1, the surface of the resultant is planarized by chemical mechanical polishing until the upper surface of the interlayer insulating layer 120 is exposed. Then, the conductive film is present only in the contact hole 130, thereby completing the copper wiring 165 of the semiconductor device made of the conductive film.
앞서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 구리 배선의 확산 방지막은 최근 반도체 소자의 집적도가 높아짐에 따라 접촉홀의 애스펙트 비(aspect ratio) 또한 커지는 것을 고려하여 애스펙트 비가 높은 영역에서 스텝 커버리지가 좋은 ALD 방법을 이용하여 형성한다. 또한, 더 좋은 스텝 커버리지를 얻기 위해 수십Å 이하의 낮은 두께로 여러번 반복하여 다층으로 형성한다.As described above, the diffusion preventing film of the copper wiring of the semiconductor device according to the present invention has good step coverage in a region having a high aspect ratio in consideration of the fact that the aspect ratio of the contact hole increases as the degree of integration of the semiconductor device increases. It is formed using the method. Further, in order to obtain better step coverage, the film is repeatedly formed several times with a low thickness of several tens of micrometers or less.
또한, 본 발명에 따른 확산 방지막은 TaSiN막으로 형성하되, TaSiN을 직접 증착하여 형성하지 않고, ALD 방법에 의해 다층으로 형성되어 있는 탄탈륨 나이트라이드막에 실리콘 계열의 가스 즉, SiH4 가스를 주입하여 형성한다. 따라서, 탄탈륨 실리콘 나이트라이드막을 비정질 상태로 형성할 수 있어 금속 배선 및 도전막의 도전 입자가 확산되는 현상을 최소화한다.In addition, the diffusion barrier film according to the present invention is formed of a TaSiN film, but not directly formed by depositing TaSiN, by injecting a silicon-based gas, that is, SiH 4 gas into the tantalum nitride film formed in a multilayer by the ALD method Form. Accordingly, the tantalum silicon nitride film can be formed in an amorphous state, thereby minimizing the diffusion of conductive particles in the metal wiring and the conductive film.
이상에서 본 발명의 바람직한 실시예에 대하여 상세하게 설명하였지만 본 발명의 권리범위는 이에 한정되는 것은 아니고 다음의 청구범위에서 정의하고 있는 본 발명의 기본 개념을 이용한 당업자의 여러 변형 및 개량 형태 또한 본 발명의 권리범위에 속하는 것이다.Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.
이상에서 설명한 바와 같이 본 발명에 따르면 확산 방지막을 ALD 방법으로 형성하여 접촉홀의 애스펙트 비가 커지더라도 확산 방지막의 스텝 커버리지를 좋게 할 수 있어 확산 방지막의 불량을 방지할 수 있다. As described above, according to the present invention, even if the aspect ratio of the contact hole increases by forming the diffusion barrier layer by the ALD method, the step coverage of the diffusion barrier layer can be improved, thereby preventing the defect of the diffusion barrier layer.
또한, 확산 방지막을 비정질 상태로 형성할 수 있어 도전막의 도전 입자가 주변 영역으로 확산하는 현상을 최소화하여 누설 전류를 감소시킬 수 있다. 따라서, 소자의 특성 및 동작을 안정화시킬 수 있다. In addition, the diffusion barrier may be formed in an amorphous state, thereby minimizing the diffusion of the conductive particles into the peripheral region, thereby reducing the leakage current. Therefore, the characteristics and operation of the device can be stabilized.
도 1은 본 발명의 일 실시예에 따른 반도체 소자의 구리 배선을 개략적으로 도시한 단면도이고,1 is a cross-sectional view schematically showing a copper wiring of a semiconductor device according to an embodiment of the present invention.
도 2a 내지 도 2e는 본 발명의 한 실시예에 따른 반도체 소자의 구리 배선 제조 방법을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a copper wiring of a semiconductor device according to an exemplary embodiment of the present invention.
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