KR20020056293A - Method for forming metal line in semiconductor device - Google Patents

Method for forming metal line in semiconductor device Download PDF

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KR20020056293A
KR20020056293A KR1020000085616A KR20000085616A KR20020056293A KR 20020056293 A KR20020056293 A KR 20020056293A KR 1020000085616 A KR1020000085616 A KR 1020000085616A KR 20000085616 A KR20000085616 A KR 20000085616A KR 20020056293 A KR20020056293 A KR 20020056293A
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film
layer
barrier metal
forming
metal
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KR1020000085616A
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Korean (ko)
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이인행
김장식
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박종섭
주식회사 하이닉스반도체
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Publication of KR20020056293A publication Critical patent/KR20020056293A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for fabricating a metal interconnection of a semiconductor device is provided to prevent encroachment generated in a hybrid organic siloxane polymer(HOSP) layer and caused by the contact of WF6 and HOSP when a tungsten layer is deposited, by forming a TiN layer as a barrier layer for stably filling the tungsten layer in a via hole while using an atomic layer deposition(ALD) method. CONSTITUTION: A semiconductor substrate(10) is prepared in which the first metal interconnection(11) is formed. An insulation thin film(13) is deposited on the first metal interconnection. An interlayer dielectric is deposited on the insulation thin film. A via hole exposing a predetermined portion of the first metal interconnection is formed in the interlayer dielectric. A barrier metal layer is deposited on the resultant structure having the via hole through an ALD method. A plug contact layer(16) is formed on the barrier metal layer. The second metal interconnection(17) in contact with the plug contact layer is formed.

Description

반도체 소자의 금속배선 형성방법{METHOD FOR FORMING METAL LINE IN SEMICONDUCTOR DEVICE}METHOD FOR FORMING METAL LINE IN SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 보다 구체적으로는, 배리어 금속막 증착을 안정화할 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device capable of stabilizing deposition of a barrier metal film.

최근, 반도체 소자의 고집적화에 따라 금속배선을 통한 신호전달에 있어 RC지연에 의해 소자의 동작속도가 느려지는 문제점을 해결하는 방법으로 새로운 저유전율 절연물을 층간절연막으로 사용하는 시도가 활발히 진행중이다. 이중 Hybrid Organic Siloxane Polymer (이하 HOSP)막은 유전률이 약 2.5 이며 열안정성이 뛰어나고 갭 필링(gap filling) 능력이 좋으며 낮는 스트레스를 가지는 등 많은 장점을 가지고 있어 차세대 반도체 소자의 층간절연막으로 사용될 가능성이 매우 높다. 이렇게 HOSP막으로 절연된 금속선을 비아홀을 통해 연결할 때 비아홀은 보통 화학증착법에 의한 텅스텐막으로 매립된다.In recent years, attempts have been actively made to use a new low dielectric insulator as an interlayer insulating film in order to solve the problem of slowing the operation speed of the device due to RC delay in signal transmission through metal wiring due to high integration of semiconductor devices. Hybrid Organic Siloxane Polymer (HOSP) film has many advantages such as dielectric constant of about 2.5, excellent thermal stability, good gap filling capability and low stress. . When the metal wire insulated with the HOSP film is connected through the via hole, the via hole is usually filled with a tungsten film by chemical vapor deposition.

그러나, 상기 저유전 물질중에 하나인 HOSP막을 층간절연막으로 사용하여 비아홀을 형성하는 경우, 상기 비아홀의 매립을 화학증착법에 의한 텅스텐막을 이용하는 경우에 있어 다음과 문제점이 발생한다.However, when the via hole is formed using the HOSP film, which is one of the low dielectric materials, as the interlayer insulating film, the following problem occurs when the tungsten film is deposited by chemical vapor deposition.

먼저, 상기 텅스텐막에 사용되는 WF6 가스와 HOSP막이 서로 접촉하는 경우 반응에 의해 HOSP막에 침식(encroachment)아 발생한다는 점이다.First, when the WF6 gas and the HOSP film used in the tungsten film are in contact with each other, an encroachment occurs in the HOSP film by a reaction.

즉, 상기 텅스텐막 증착전 진행되는 배리어 금속막 증착공정에서 형성된 티타늄 질화막(TiN)이 비아홀의 측벽에 완벽하게 도포되지 않은 경우, 상기 WF6 가스가 측벽으로 침투하여 HOSP막내로 심한 침식이 발생되어 안정적인 저항을 확보하기가 불가능한 문제가 있다.That is, when the titanium nitride film (TiN) formed in the barrier metal film deposition process performed before the tungsten film deposition is not completely applied to the sidewall of the via hole, the WF6 gas penetrates into the sidewall, causing severe erosion into the HOSP film. There is a problem that it is impossible to secure resistance.

이런 문제를 해결하기 위해서는 상기 배리어 금속막인 TiN막이 측벽에 충분한 두께를 가지고 치밀하게 도포되어야 한다. 이 때, PVD공정으로 TiN막을 증착하는 경우에는 측벽도포성에 문제가 있으므로 TiN막은 측벽도포성이 뛰어난 CVD공정을 사용하여야 한다. 상기 CVD공정을 이용한 TiN막 증착은 TiCl4-NH3-H2를 이용한 것과 TDMAT(Tetra Di Methyl Titanium) 금속유기체를 이용한 것으로 나눌 수 있다.In order to solve this problem, the TiN film, which is the barrier metal film, needs to be applied to the sidewalls with sufficient thickness. In this case, when the TiN film is deposited by the PVD process, there is a problem in the sidewall coating property. Therefore, the TiN film should use a CVD process having excellent sidewall coating property. TiN film deposition using the CVD process can be divided into TiCl4-NH3-H2 and TDMAT (Tetra Di Methyl Titanium) metal organic.

상기 TiCl4-NH3-H2의 경우에는 증착온도가 550℃ 이상이 되어야 안정적인 막질을 얻을 수 있으며, TDMAT 금속유기체를 사용하는 경우에는 증착온도는 350~400℃로 비교적 저온이나 TiN막내 C, O 등 불순물이 함유되어 있어 저항이 높으며 플라즈마 처리를 통해 막질을 개선한다고 하더라도 측벽에 증착된 층은 거의 개선이 되어 있지 않으므로 깨끗한 TiN막을 얻기가 매우 어려운 문제점을 가지고 있다.In the case of TiCl4-NH3-H2, a stable film quality can be obtained when the deposition temperature is 550 ° C. or higher. In the case of using a TDMAT metal organic material, the deposition temperature is 350 to 400 ° C., which is relatively low, but impurities such as C and O in the TiN film are relatively low. Since the resistivity is high and the film quality is improved through plasma treatment, the layer deposited on the sidewall is hardly improved, and thus it is very difficult to obtain a clean TiN film.

따라서, 상기와 같은 문제점을 해결하기 위한 본 발명의 목적은, ALD(Atomic Layer Deposition)방식을 이용하여 배리어 금속막을 형성할 수 있는 반도체 소자의 금속배선 형성방법을 제공하는 것이다.Accordingly, an object of the present invention for solving the above problems is to provide a method for forming a metal wiring of a semiconductor device capable of forming a barrier metal film using an ALD (Atomic Layer Deposition) method.

도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 제조공정도.1A to 1C are manufacturing process diagrams for explaining a method for forming metal wirings of a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호설명 ** Explanation of Signs of Major Parts of Drawings *

10 : 반도체 기판 11 : 제1 금속배선10 semiconductor substrate 11 first metal wiring

12 : 제1 층간절연막 13 : 박막의 절연막12: first interlayer insulating film 13: thin film insulating film

14 : 제2 층간절연막 15 : 비아홀14: second interlayer insulating film 15: via hole

16 : 플러그 콘택막 17 : 제2 금속배선막16 plug contact film 17 second metal wiring film

100 : 배리어 금속막100: barrier metal film

상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속배선 형성방법은, 제1 금속배선이 형성된 반도체 기판을 제공하는 단계; 상기 제1 금속배선 상부에 박막의 절연막을 증착하는 단계; 상기 박막의 절연막 상부에 층간절연막을 증착하는 단계; 상기 층간절연막에 상기 제1 금속배선의 소정부분을 노출시키는 비아홀을 형성하는 단계; 상기 비아홀이 형성된 전체구조 상면에 ALD(Atomic Layer Deposition)방식을 통한 배리어 금속막을 증착하는 단계; 상기 배리어 금속막 상부에 플러그 콘택막을 형성하는 단계; 및 상기 플러그 콘택막과 콘택하는 제2 금속배선을 형성하는 단계를 포함하여 구성하는 것을 특징으로 한다.Method of forming a metal wiring of the semiconductor device according to the present invention for achieving the above object comprises the steps of providing a semiconductor substrate formed with a first metal wiring; Depositing an insulating film of a thin film on the first metal wire; Depositing an interlayer insulating film over the insulating film of the thin film; Forming a via hole exposing a predetermined portion of the first metal wire in the interlayer insulating film; Depositing a barrier metal film using an atomic layer deposition (ALD) method on an upper surface of the entire structure in which the via holes are formed; Forming a plug contact layer on the barrier metal layer; And forming a second metal wire in contact with the plug contact layer.

이하, 본 발명의 바람직한 실시예를 첨부한 도면에 의거하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 금속배선 형성방법에 관한 것이다.1A to 1C are directed to a method for forming metal wirings of a semiconductor device according to the present invention.

먼저, 도 1a에 도시된 바와같이, 제1 금속배선(11)이 형성된 반도체 기판(10)을 제공한다. 도면에는 도시하지 않았지만, 상기 반도체 기판(10) 상에는 트랜지스터가 형성되어 있고, 그 상부에 콘택홀이 형성된 제1 층간절연막(12)이 증착되어 있다.First, as shown in FIG. 1A, a semiconductor substrate 10 on which a first metal wiring 11 is formed is provided. Although not shown in the figure, a transistor is formed on the semiconductor substrate 10, and a first interlayer insulating film 12 having a contact hole formed thereon is deposited.

상기 제1 층간절연막(12) 상부에 제1 금속배선(11)이 형성된 전체구조 상면에 박막의 절연막(13)을 증착한다. 상기 박막의 절연막(13)은 IMD(inter metal dilectric)의 역할을 수행한다.The thin film insulating layer 13 is deposited on the upper surface of the entire structure in which the first metal wiring 11 is formed on the first interlayer insulating layer 12. The insulating film 13 of the thin film serves as an inter metal dilectric (IMD).

그 다음, 상기 절연막(13) 상부에 제2 층간절연막(14)을 증착한다. 이 때, 상기 제2 층간절연막(14)은 바람직하게 저유전 물질막인 하이브리드 유기 실란 폴리머(이하, HOSP)막으로 형성된다. 그 다음, 상기 제2 층간절연막(14)에 상기 제1 금속배선(11)의 소정부분을 노출시키는 비아홀(15)을 형성한다.Next, a second interlayer insulating film 14 is deposited on the insulating film 13. At this time, the second interlayer insulating film 14 is preferably formed of a hybrid organic silane polymer (hereinafter referred to as HOSP) film which is a low dielectric material film. Next, a via hole 15 exposing a predetermined portion of the first metal wiring 11 is formed in the second interlayer insulating film 14.

그 다음, 도 1b에 도시된 바와같이, 상기 비아홀(15)이 형성된 전체구조 상면에 ALD(Atomic Layer Deposition) 방식을 통하여 배리어 금속막(100)을 증착한다. 상기 배리아 금속막(100)은 바람직하게 티타늄 질화막(TiN)으로 형성되며, 상기 ALD 방식을 통한 배리어 금속막 증착은 반응기체인 TiCl4와 NH3를 이용하여 실시한다.Next, as shown in FIG. 1B, the barrier metal film 100 is deposited on the upper surface of the entire structure in which the via hole 15 is formed through an ALD (Atomic Layer Deposition) method. The barrier metal film 100 is preferably formed of a titanium nitride film (TiN), and the deposition of the barrier metal film through the ALD method is performed using TiCl 4 and NH 3, which are reactive bodies.

이 때, 상기 ALD 방식을 통한 배리어 금속막 증착에 있어서, 먼저, 챔버내에TiCl4 가스를 유입하여 상기 비아홀이 형성된 후의 결과물 표면상에 물리 흡착을 시킨다. 그 다음, 아르곤과 같은 불활성 기체로 챔버내를 퍼지(purge)한 다음, 상기 퍼지된 동일 챔버내에서 상기 물리 흡착된 TiCl4 가스와 NH3 가스와 반응시킴으로써, 티타늄 질화막을 형성한다. 이 때, 상기 배리어 금속막은 챔버내 온도 300 ~ 450를 유지하여 형성된다.At this time, in the deposition of the barrier metal film through the ALD method, first, TiCl 4 gas is introduced into the chamber to physically adsorb onto the resulting surface after the via hole is formed. A titanium nitride film is then formed by purging the chamber with an inert gas such as argon and then reacting with the physically adsorbed TiCl 4 gas and NH 3 gas in the same purged chamber. At this time, the barrier metal film is formed by maintaining a temperature of 300 to 450 in the chamber.

여기서, 상기와 같은 ALD 공정을 반복함으로써 원하는 두께를 형성할 수 있다. 이 때, 증착되는 두께는 후속 형성되는 텅스텐막 증착시 WF6의 측벽으로의 침식을 방지할 수 있는 두께로 조절한다.Here, the desired thickness can be formed by repeating the ALD process as described above. At this time, the thickness to be deposited is adjusted to a thickness that can prevent erosion to the side wall of the WF6 during the subsequent deposition of tungsten film.

그 다음, 도 1c에 도시된 바와같이, 상기 배리어 금속막(100)이 증착된 전체구조 상면에 상기 비아홀(15)을 매립시키는 플러그 콘택막(16)을 형성한다. 이 때, 상기 플러그 콘택막(16)은 바람직하게 화학증착법을 이용한 텅스텐막으로 형성된다. 이어서, 상기 플러그 콘택막(16)이 형성된 전체구조 상면에 제2 금속배선막(17)을 형성하여 반도체 소자의 금속배선을 형성한다.Next, as shown in FIG. 1C, a plug contact layer 16 may be formed on the upper surface of the entire structure on which the barrier metal layer 100 is deposited. At this time, the plug contact film 16 is preferably formed of a tungsten film using a chemical vapor deposition method. Subsequently, the second metal wiring layer 17 is formed on the upper surface of the entire structure in which the plug contact layer 16 is formed to form metal wiring of the semiconductor device.

상기한 바와같은 반도체 소자의 금속배선 형성방법은 다음과 같은 효과가 있다.The metal wiring forming method of the semiconductor device as described above has the following effects.

층간절연막으로 저유전 물질인 HOSP막을 금속 층간절연막으로 사용하는 경우, 상기 비아홀에 텅스텐막을 안정적으로 매립하기 위한 배리어 금속막으로 ALD 공정을 적용시킨 TiN막을 형성한다. 이에, 상기 텅스텐막 증착시 WF6와 HOSP의 접촉에 의해 HOSP막에 발생되는 침식(encroachment)을 방지하여 안정적인 소자 동작에 기여할 수 있다.When the low dielectric material HOSP film is used as the metal interlayer insulating film as the interlayer insulating film, a TiN film to which the ALD process is applied is formed as a barrier metal film for stably embedding the tungsten film in the via hole. As a result, the deposition of the tungsten film prevents erosion generated in the HOSP film due to the contact of the WF6 and the HOSP, thereby contributing to stable device operation.

기타, 본 발명의 요지를 벗어나지 않는 범위내에서 다양하게 변경하여 실시할 수 있다.In addition, it can implement in various changes within the range which does not deviate from the summary of this invention.

Claims (8)

제1 금속배선이 형성된 반도체 기판을 제공하는 단계;Providing a semiconductor substrate having a first metal wiring formed thereon; 상기 제1 금속배선 상부에 박막의 절연막을 증착하는 단계;Depositing an insulating film of a thin film on the first metal wire; 상기 박막의 절연막 상부에 층간절연막을 증착하는 단계;Depositing an interlayer insulating film over the insulating film of the thin film; 상기 층간절연막에 상기 제1 금속배선의 소정부분을 노출시키는 비아홀을 형성하는 단계;Forming a via hole exposing a predetermined portion of the first metal wire in the interlayer insulating film; 상기 비아홀이 형성된 전체구조 상면에 ALD(Atomic Layer Deposition)방식을 통한 배리어 금속막을 증착하는 단계;Depositing a barrier metal film using an atomic layer deposition (ALD) method on an upper surface of the entire structure in which the via holes are formed; 상기 배리어 금속막 상부에 플러그 콘택막을 형성하는 단계; 및Forming a plug contact layer on the barrier metal layer; And 상기 플러그 콘택막과 콘택하는 제2 금속배선을 형성하는 단계를 포함하여 구성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And forming a second metal wire in contact with the plug contact layer. 제 1항에 있어서,The method of claim 1, 상기 층간절연막은 저유전 물질막인 하이브리드 유기 실란 폴리머막(HOSP)인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The interlayer dielectric layer is a hybrid organic silane polymer layer (HOSP) which is a low dielectric material layer. 제 1항에 있어서,The method of claim 1, 상기 배리어 금속막은 티타늄 질화막인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And the barrier metal film is a titanium nitride film. 제 1항 또는 제 3항에 있어서,The method according to claim 1 or 3, 상기 ALD 방식을 통한 배리어 금속막 증착은 반응기체 TiCl4와 NH3를 이용하여 실시하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.Barrier metal film deposition through the ALD method is performed using the reactant TiCl4 and NH3 metallization method of the semiconductor device. 제 4항에 있어서,The method of claim 4, wherein 상기 배리어 금속막 증착은 챔버내에 TiCl4 가스를 유입하여 상기 비아홀이 형성된 후의 결과물 표면상에 흡착시키는 단계;The deposition of the barrier metal film may include adsorbing TiCl 4 gas into a chamber and adsorbing the resultant surface after the via hole is formed; 상기 불활성 기체로 챔버내를 퍼지(purge)하는 단계; 및Purging the chamber with the inert gas; And 상기 퍼지된 동일 챔버내에서 상기 흡착된 TiCl4 가스와 NH3 가스와 반응시켜 티타늄 질화막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And forming a titanium nitride film by reacting with the adsorbed TiCl 4 gas and NH 3 gas in the same purged chamber. 제 5항에 있어서,The method of claim 5, 상기 불활성 기체는 아르곤 가스인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And said inert gas is an argon gas. 제 4항에 있어서,The method of claim 4, wherein 상기 배리어 금속막은 챔버내 온도 300 ~ 450를 유지하여 형성되는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The barrier metal film is a metal wiring forming method of the semiconductor element, characterized in that formed by maintaining the temperature in the chamber 300 ~ 450. 제 1항에 있어서,The method of claim 1, 상기 플러그 콘택막을 텅스텐막인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And a tungsten film for said plug contact film.
KR1020000085616A 2000-12-29 2000-12-29 Method for forming metal line in semiconductor device KR20020056293A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100613346B1 (en) * 2004-12-15 2006-08-21 동부일렉트로닉스 주식회사 Semiconductor device and manufacturing method thereof
KR100873017B1 (en) * 2002-07-19 2008-12-09 주식회사 하이닉스반도체 Method for fabricating multi-layer metallization
KR200452087Y1 (en) * 2009-12-16 2011-02-01 김상택 Waste plastic and waste vinyl total liquefaction apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100873017B1 (en) * 2002-07-19 2008-12-09 주식회사 하이닉스반도체 Method for fabricating multi-layer metallization
KR100613346B1 (en) * 2004-12-15 2006-08-21 동부일렉트로닉스 주식회사 Semiconductor device and manufacturing method thereof
KR200452087Y1 (en) * 2009-12-16 2011-02-01 김상택 Waste plastic and waste vinyl total liquefaction apparatus

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