KR20050053283A - Thin film transistor array substrate and fabricating method thereof - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate capable of reducing light loss in a pixel region and a method of manufacturing the same.

The thin film transistor array substrate according to the present invention includes a gate line formed on the substrate; A common line formed in parallel with the gate line; A data line interposed to be insulated from the gate line and the common line, and formed between the pixel regions; A thin film transistor formed at an intersection of the gate line and the data line; A common electrode formed in the pixel region and connected to the common line; A pixel electrode connected to the thin film transistor and forming a horizontal electric field with the common electrode in the pixel region; And an organic passivation layer formed in the remaining region except for the pixel region.

Description

Thin Film Transistor Array Substrate and its Manufacturing Method {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel using a horizontal electric field, and more particularly, to a thin film transistor array substrate capable of reducing light loss in a pixel region and a method of manufacturing the same.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. Such liquid crystal display devices are classified into vertical electric field types and horizontal electric field types according to the direction of the electric field for driving the liquid crystal.

In the vertical field type liquid crystal display, the common electrode formed on the upper substrate and the pixel electrode formed on the lower substrate are disposed to face each other to drive the liquid crystal of TN (Twisted Nemastic) mode by a vertical electric field formed therebetween. Such a vertical field type liquid crystal display device has a large aperture ratio, but has a narrow viewing angle of about 90 degrees.

In a horizontal field type liquid crystal display, a liquid crystal in an in-plane switch (hereinafter referred to as IPS) mode is driven by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on a lower substrate. The horizontal field type liquid crystal display device has an advantage that a viewing angle is about 160 degrees. Hereinafter, the horizontal field type liquid crystal display device will be described in detail.

As shown in FIG. 1, the horizontal field type liquid crystal display includes a thin film transistor array substrate 50 and a color filter array substrate 60 bonded to each other as shown in FIG. 1, and a liquid crystal 40 filled in a liquid crystal space provided by two substrates and a spacer. It is provided.

3, the color filter array substrate 60 includes a color filter 34 for implementing a color formed on the upper substrate 11, a black matrix 32 for preventing light leakage, a color filter 34, and a color filter array substrate 60. A planarization layer 36 for planarizing the upper substrate 11 having the black matrix 32 formed thereon, and a spacer 70 for maintaining a constant cell gap on the planarization layer 36.

As shown in FIGS. 2 and 3, the thin film transistor array substrate 50 includes a gate line 2 and a data line 4 intersected on the lower substrate 1, and a thin film transistor 30 formed at each intersection thereof. ), A pixel electrode 22 and a common electrode 24 formed to form a horizontal electric field in the pixel region provided in the intersection structure, and a common line 26 connected to the common electrode 24.

The gate line 2 supplies a gate signal to the gate electrode 6 of the thin film transistor 30. The data line 4 supplies the pixel signal to the pixel electrode 22 through the drain electrode 10 of the thin film transistor 30. The gate line 2 and the data line 4 are formed in an intersecting structure to define the pixel area. The common line 26 is formed in parallel with the gate line 2 with the pixel region therebetween, and supplies a reference voltage for driving the liquid crystal to the common electrode 24.

The thin film transistor 30 keeps the pixel signal of the data line 4 charged and held in the pixel electrode 22 in response to the gate signal of the gate line 2. To this end, the thin film transistor 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode connected to the pixel electrode 22. 10). In addition, the thin film transistor 30 includes a semiconductor layer (not shown) that overlaps with the gate electrode 6 and the gate insulating layer 12 therebetween to form a channel between the source electrode 8 and the drain electrode 10. More is formed.

The pixel electrode 22 is connected to the drain electrode 10 of the thin film transistor 30 through the contact hole 20 penetrating the passivation layer 18 and is formed in the pixel area. In particular, the pixel electrode 22 is formed in parallel with the common electrode 24 between the common electrodes 24.

The common electrode 24 is connected to the common line 26 to be formed in the pixel region. In particular, the common electrode 24 is formed parallel to the pixel electrode 22 in the pixel region.

Accordingly, a horizontal electric field is formed between the pixel electrode 22 supplied with the pixel signal through the thin film transistor 30 and the common electrode 24 supplied with the reference voltage through the common line 26. The horizontal electric field causes liquid crystal molecules arranged in the horizontal direction between the thin film transistor array substrate 50 and the color filter array substrate 60 to rotate by dielectric anisotropy. According to the degree of rotation of the liquid crystal molecules, the light transmittance passing through the pixel region is changed, thereby realizing an image.

Meanwhile, the passivation layer 18 of the thin film transistor array substrate 50 illustrated in FIGS. 2 and 3 is formed of an inorganic insulating material. The inorganic insulating material has a high dielectric constant and a signal line including the gate line 2 and the data line 4 and a driving electrode including the pixel electrode 22 and the common electrode 24 are formed at predetermined intervals. . This is because when the signal line and the driving electrode are overlapped with the passivation layer 18 therebetween to increase the aperture ratio, the capacitance value of the parasitic capacitor between the signal line and the driving electrode becomes large, resulting in signal distortion.

As described above, when the protective film is formed of an inorganic insulating material, the signal line and the driving electrode have to be spaced apart at a predetermined interval, and thus there is a problem in that the aperture ratio decreases by that interval.

In order to solve this problem, the structure of the thin film transistor array substrate shown in FIGS. 4 and 5 has been proposed.

The protective film 18 of the thin film transistor array substrate shown in FIGS. 4 and 5 is formed of an organic insulating material including BCB and acrylic resin. In this case, since the passivation layer 18 is formed of an organic insulating material having a low dielectric constant, the data line (gate line) and the common electrode (common line) are overlapped. As a result, the light transmission region between the common electrode and the pixel electrode is widened to improve the aperture ratio. In addition, since the common electrode (common line) and the data line (gate line) overlap completely, the gate signal and the data signal affecting the electric field between the common electrode 24 and the pixel electrode 22 are shielded.

Meanwhile, the passivation layer 18 formed of the organic insulating material is formed on the entire lower substrate 1 including the pixel region. Since the organic protective film 18 loses about 5 to 9% of light from the backlight, there is a problem that the light transmittance is lowered. In addition, the organic passivation layer 18 has a poor adhesion with the adjacent layer, so that the floating phenomenon occurs, and the organic passivation layer 18 includes carbon (C), so that the organic passivation layer 18 directly contacts the channel portion of the thin film transistor 30. There is a problem that the characteristics of.

Accordingly, an object of the present invention is to provide a thin film transistor array substrate and a method of manufacturing the same which can reduce light loss in the pixel region.

In order to achieve the above object, the thin film transistor array substrate according to the present invention includes a gate line formed on the substrate; A common line formed in parallel with the gate line; A data line interposed to be insulated from the gate line and the common line, and formed between the pixel regions; A thin film transistor formed at an intersection of the gate line and the data line; A common electrode formed in the pixel region and connected to the common line; A pixel electrode connected to the thin film transistor and forming a horizontal electric field with the common electrode in the pixel region; And an organic passivation layer formed in the remaining region except for the pixel region.

The thin film transistor array substrate may further include an inorganic protective film formed between the organic protective film and the thin film transistor.

The pixel electrode is formed on the inorganic protective film.

The pixel electrode is formed on the gate insulating film.

The common electrode may be formed on the organic passivation layer and overlap the data line with the organic passivation layer therebetween.

The common electrode may be formed on a plane and a side surface of the organic passivation layer.

The thin film transistor array substrate may further include a spacer formed on the organic passivation layer and integrated with the organic passivation layer.

The organic protective film is formed of an organic insulating material including acrylic resin, BCB, and the like.

The inorganic protective film is formed of an inorganic insulating material containing any one of silicon nitride and silicon oxide.

In order to achieve the above object, a method of manufacturing a thin film transistor array substrate according to the present invention is a gate line, the data line for crossing the gate line and the gate insulating film interposed to determine the pixel region, the intersection of the gate line and the data line Forming a thin film transistor in the portion; Forming an organic passivation layer on a region other than the pixel region; And forming a pixel electrode connected to the thin film transistor in the pixel area and forming a common electrode forming a horizontal electric field with the pixel electrode.

The forming of the organic passivation layer in the remaining regions other than the pixel area may include forming the spacer and overlapping any one of the gate line, data line, and thin film transistor with the same material as the organic passivation layer. Characterized in that it comprises a.

The forming of the pixel electrode and the common electrode may include forming a pixel electrode on the gate insulating layer exposed by the organic passivation layer and forming a common electrode on the organic passivation layer.

The method of manufacturing the thin film transistor array substrate may further include forming an inorganic passivation layer protecting the thin film transistor between the thin film transistor and the organic passivation layer.

The forming of the pixel electrode and the common electrode may include forming a pixel electrode on the inorganic passivation layer exposed by the organic passivation layer and forming a common electrode on the organic passivation layer.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 6 to 13.

FIG. 6 is a plan view illustrating a thin film transistor array substrate according to a first exemplary embodiment of the present invention, and FIG. 7 is a cross-sectional view illustrating a thin film transistor array substrate taken along a line “Ⅶ-Ⅶ” in FIG. 6.

The thin film transistor array substrate 150 shown in FIGS. 6 and 7 includes a gate line 102 and a data line 104 formed to intersect the lower substrate 101, and a thin film transistor 130 formed at each intersection thereof. And a pixel electrode 122 and a common electrode 124 formed to form a horizontal electric field in the pixel region provided in a cross structure thereof, and a common line 126 connected to the common electrode 124. In addition, the thin film transistor array substrate 150 may further include an organic passivation layer 128 that protects the thin film transistor 130, and a spacer 170 that is formed integrally with the organic passivation layer 128 and maintains a constant cell gap. Equipped.

The gate line 102 supplies a gate signal to the gate electrode 106 of the thin film transistor 130. The data line 104 supplies the pixel signal to the pixel electrode 122 through the drain electrode 110 of the thin film transistor 130. The data line 104 is formed to overlap the common electrode 124 with the inorganic passivation layer 118 and the organic passivation layer 128 interposed therebetween. The common line 126 is formed in parallel with the gate line 102 with the pixel region 105 interposed therebetween, and supplies a reference voltage for driving the liquid crystal to the common electrode 124. The common line 126 is formed to overlap the gate line 102 with the gate insulating layer 112, the inorganic protective layer 118, and the organic protective layer 128 interposed therebetween.

The thin film transistor 130 keeps the pixel signal of the data line 104 charged and maintained in the pixel electrode 122 in response to the gate signal of the gate line 102. To this end, the thin film transistor 130 may include a gate electrode 106 connected to the gate line 102, a source electrode 108 connected to the data line 104, and a drain electrode connected to the pixel electrode 122. 110). In addition, the thin film transistor 130 includes an active layer 114 that forms a channel between the source electrode 108 and the drain electrode 110 while overlapping the gate electrode 106 and the gate insulating layer 112 therebetween, and the source electrode. An ohmic contact layer 116 for ohmic contact with the 108 and the drain electrode 110 is further formed.

As shown in FIG. 7, the inorganic protective layer 118 and the organic protective layer 128 are sequentially stacked on the thin film transistor 130, or as shown in FIG. 8, the inorganic protective layer 118 is stacked in a single layer. Formed into a structure. In this case, the inorganic protective film 118 formed to cover the thin film transistor 130 prevents damage to the channel portion of the thin film transistor 130 by carbon (C) included in the organic protective film 128.

The organic passivation layer 128 is formed on the inorganic passivation layer 118 except for the pixel region 105 provided at the intersection of the gate line 102, the data line 104, and the common line 126. In other words, the organic passivation layer 128 is removed from the pixel region 105 through the through hole 184. The organic passivation layer 128 has a low dielectric constant, such that the data line (gate line) and the common electrode (common line) overlap each other, thereby improving the aperture ratio.

In addition, the common electrode 124 is formed to overlap the data line 104 by the organic passivation layer 128, and the gate line 102 and the common line 126 are formed to overlap each other. Accordingly, the electric field distortion can be prevented by shielding the data signal from the data line 104 and the gate signal from the gate line 102 that affect the electric field between the pixel electrode 122 and the common electrode 122. .

The spacer 170 is simultaneously formed of the same material as the organic passivation layer 128. The spacer 170 protrudes from a region corresponding to at least one of the gate line 102, the data line 104, the common line 126, and the thin film transistor 130 so that the color filter array substrate and the thin film transistor array substrate ( Maintain the cell gap between 150).

As illustrated in FIG. 7, the pixel electrode 122 penetrates the first contact hole 180 penetrating the inorganic passivation layer 118 and the second contact hole 180 penetrating the organic passivation layer 128 and overlaps the first contact hole 180. It is connected to the drain electrode 110 of the thin film transistor 130 through the contact hole 182 is formed on the inorganic protective film 118 in the pixel region. Alternatively, as illustrated in FIG. 8, the contact hole 120 penetrates the inorganic passivation layer 118 and is connected to the drain electrode 110 of the thin film transistor 130 to be formed on the inorganic passivation layer 118 of the pixel region.

The pixel electrode 122 is formed in parallel with the common electrode 124 between the common electrodes 124.

The common electrode 124 is connected to the common line 126 to be formed in the pixel area. In particular, the common electrode 124 is formed to be parallel to the pixel electrode 122 in the pixel area.

Accordingly, a horizontal electric field is formed between the pixel electrode 122 supplied with the pixel signal through the thin film transistor 130 and the common electrode 124 supplied with the reference voltage through the common line 126. The horizontal electric field causes liquid crystal molecules arranged in the horizontal direction between the thin film transistor array substrate 150 and the color filter array substrate to rotate by dielectric anisotropy. According to the degree of rotation of the liquid crystal molecules, the light transmittance passing through the pixel region is changed, thereby realizing an image.

As described above, in the thin film transistor array substrate according to the first embodiment of the present invention, the organic protective layer positioned on the pixel area is removed to reduce the loss generated while the light generated in the backlight passes through the organic protective layer.

In addition, in the thin film transistor array substrate according to the first embodiment of the present invention, the signal line and the driving electrode are formed to overlap each other with the organic passivation layer interposed therebetween, thereby increasing the aperture ratio and preventing electric field distortion between the driving electrodes.

In addition, the thin film transistor array substrate according to the first embodiment of the present invention can reduce the total number of mask processes of the liquid crystal display panel by forming an organic passivation layer simultaneously with the spacer.

9A to 9C are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention. Here, the thin film transistor array substrate illustrated in FIG. 7 among the thin film transistor array substrate illustrated in FIGS. 7 and 8 will be described as an example.

Referring to FIG. 9A, an inorganic passivation layer 118 having a first contact hole 180 is formed on a lower substrate 101 on which a gate line 102, a data line 104, and a thin film transistor 130 are formed.

To this end, the inorganic protective layer 118 is formed by depositing an inorganic insulating material on the lower substrate 101 on which the gate line 102, the data line 104, and the thin film transistor 130 are formed. The inorganic protective film 118 is formed of an inorganic insulating material including silicon nitride (SiNx) or silicon oxide (SiOx). The inorganic protective film 118 is patterned by a photolithography process and an etching process using a mask to form a first contact hole 180. The first contact hole 180 penetrates through the inorganic protective layer 118 to expose the drain electrode 110.

Referring to FIG. 9B, an organic passivation layer 128 having a second contact hole 182 and a through hole 184 is formed on the lower substrate 101 on which the inorganic passivation layer 118 is formed, and on the organic passivation layer 128. Spacer 170 is formed. Detailed description thereof will be described in detail with reference to FIGS. 10A to 10D.

First, as illustrated in FIG. 10A, an organic insulating material 129 and a photoresist 216 are sequentially coated on the inorganic protective film 118. Here, the organic insulating material 129 may be an organic insulating material such as a positive photoresist, an acryl-based organic compound having a low dielectric constant, BCB, or PFCB.

Then, the partial exposure mask 200 is aligned above the lower substrate 101. The partial exposure mask 200 includes a mask substrate 210 made of a transparent material, a blocking portion 212 formed in the blocking region S2 of the mask substrate 210, and a partial exposure region S3 of the mask substrate 210. The formed diffraction exposure part 214 (or semi-transmissive part) is provided. Here, the region where the mask substrate 210 is exposed becomes the exposure region S1.

The photoresist film 216 is exposed and developed using the partial exposure mask 200 to correspond to the blocking portion 212 and the diffraction exposure portion 214 of the partial exposure mask 200 as shown in FIG. 10B. As a result, a photoresist pattern 208 having a step difference between the blocking region S2 and the partial exposure region S3 is formed. That is, the photoresist pattern 208 formed in the partial exposure region S3 has a second height lower than that of the photoresist pattern 208 having the first height formed in the blocking region S2.

The organic insulating material is patterned by an etching process using the photoresist pattern 208 as a mask, so that the through hole 184 exposing the inorganic protective film 118 of the pixel region 105, the first contact hole 180 region, and the like. An organic passivation layer 128 having an overlapping second contact hole 182 is formed.

Subsequently, in the ashing process using an oxygen (O ₂ ) plasma, the photoresist pattern 208 having the second height in the partial exposure region S3 is removed as shown in FIG. 10C, and the blocking region S2 is removed. The photoresist pattern 208 having the first height is in a state where the height is lowered. The organic passivation layer 128 of the partial exposure region S3 is partially removed by the etching process using the photoresist pattern 208. Accordingly, the spacer 170 protruding from the region corresponding to at least one of the gate line, the data line, the common line, and the thin film transistor is formed. The photoresist pattern 208 remaining on the spacer 170 is removed by a strip process as shown in FIG. 10D.

Referring to FIG. 9C, the pixel electrode 122, the common line 126, and the common electrode 124 are formed on the lower substrate 101 on which the organic passivation layer 128 and the spacer 170 are formed.

To this end, a transparent conductive film is formed on the lower substrate 101 on which the organic protective film 128 is formed through a deposition method such as sputtering. Herein, the transparent conductive film may include indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (ITZO), indium zinc oxide (IZO), or the like. Transparent conductive materials are used. Subsequently, the transparent conductive film is patterned by a photolithography process and an etching process using a mask to form a common electrode 124, a common line 126, and a pixel electrode 122.

Meanwhile, the organic passivation layer 128 and the spacer 170 of the thin film transistor array substrate according to the first embodiment of the present invention may be formed of an organic insulating material including a photo-initiator. In this case, the organic insulating material including the photoinitiator is patterned by an exposure and development process, thereby eliminating the photoresist patterning process and the etching process, thereby reducing the material cost and simplifying the process.

11 is a cross-sectional view illustrating a thin film transistor array substrate according to a second embodiment of the present invention.

Referring to FIG. 11, a thin film transistor array substrate according to a second embodiment of the present invention has the same components except that an inorganic protective film is not formed as compared to the thin film transistor array substrate illustrated in FIG. 7.

The organic passivation layer 128 is formed on the gate insulating layer 112 in the remaining region except for the pixel region 105 provided at the intersection of the gate line 102, the data line 104, and the common line 126. That is, the organic passivation layer 128 is removed from the pixel region 105 through the through hole 192. The organic passivation layer 128 has a low dielectric constant, such that the data line (gate line) and the common electrode (common line) overlap each other, thereby improving the aperture ratio. In addition, the common electrode 124 is formed to overlap the data line 104 by the organic passivation layer 128, and the gate line 102 and the common line 126 are formed to overlap each other. Accordingly, the electric field distortion can be prevented by shielding the data signal from the data line 104 and the gate signal from the gate line 102 that affect the electric field between the pixel electrode 122 and the common electrode 122. .

The spacer 170 is simultaneously formed of the same material as the organic passivation layer 128. The spacer 170 protrudes from a region corresponding to at least one of the gate line 102, the data line 104, the common line 126, and the thin film transistor 130 to form a color filter array substrate and a thin film transistor array substrate. Cell gap is maintained.

The pixel electrode 122 penetrates through the organic passivation layer 128 and is connected to the drain electrode 110 of the thin film transistor 130 through the first contact hole 190 and formed on the gate insulating layer 112 of the pixel region. In particular, the pixel electrode 122 is formed in parallel with the common electrode 124 between the common electrodes 124.

As described above, the thin film transistor array substrate according to the second embodiment of the present invention can reduce the loss generated while the light generated in the backlight passes through the organic passivation layer by removing the organic passivation layer on the pixel region.

In addition, in the thin film transistor array substrate according to the second embodiment of the present invention, the signal line and the driving electrode are formed to overlap each other with the organic passivation layer interposed therebetween, thereby increasing the aperture ratio and preventing electric field distortion of the driving electrode.

In addition, the thin film transistor array substrate according to the second exemplary embodiment of the present invention can reduce the number of mask processes of the color filter array substrate by simultaneously forming an organic passivation layer with a spacer.

Meanwhile, any one of the common electrode 124 and the pixel electrode 122 of the thin film transistor array substrate according to the first to second embodiments of the present invention may be formed in various forms. For example, as illustrated in FIG. 12, the common electrode 124 may be formed to surround the organic passivation layer 128 in an area overlapping the data line 104. That is, the common electrode 124 is formed not only on the plane of the organic passivation layer 128 but also on the side surface extending from the plane of the organic passivation layer 128.

FIG. 13 is a cross-sectional view illustrating a liquid crystal display panel including a thin film transistor array substrate according to first to second embodiments of the present invention.

Referring to FIG. 13, the liquid crystal display panel includes a thin film transistor array substrate 270 and a color filter array substrate 260 bonded to each other with the liquid crystal interposed therebetween.

The color filter array substrate 260 includes a color filter 252 for color implementation and a black matrix 250 for preventing light leakage, and a color filter 252 and a black matrix 250 formed on the upper substrate 201. The planarization layer 254 is provided to planarize the upper substrate 201.

As illustrated in FIGS. 6 and 11, the thin film transistor array substrate 270 includes a gate line 102 and a data line 104 formed to intersect on the lower substrate 101, and a thin film transistor 130 formed at each intersection thereof. ), A pixel electrode 122 and a common electrode 124 formed to form a horizontal electric field in the pixel region provided in the intersection structure, and a common line 126 connected to the common electrode 124. In addition, the thin film transistor array substrate 150 includes an organic passivation layer 128 formed in the remaining regions other than the pixel region. Accordingly, it is possible to prevent the loss generated by the organic passivation layer 128 while the light generated in the backlight passes through the pixel region.

As described above, in the thin film transistor array substrate and the method of manufacturing the same, an organic passivation layer is formed in the remaining region except the pixel region. As a result, light loss caused by the organic protective film can be prevented. In addition, since the data line (gate line) and the common electrode (common line) overlap each other with the organic passivation layer interposed therebetween, the influence of the driving signal field from the signal line can be shielded. In addition, since the organic protective film and the spacer are formed at the same time, the manufacturing cost can be reduced and the manufacturing yield can be improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view illustrating a conventional horizontal field application liquid crystal display panel.

FIG. 2 is a plan view illustrating the thin film transistor array substrate shown in FIG. 1 in detail.

3 is a cross-sectional view illustrating the liquid crystal display panel illustrated in FIG. 1.

4 is a plan view of a high-aperture liquid crystal display panel employing an organic protective film.

5 is a cross-sectional view illustrating the liquid crystal display panel illustrated in FIG. 4.

6 is a plan view illustrating a thin film transistor array substrate according to a first embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating the thin film transistor array substrate taken along the lines "1-1" and "2-2" in FIG. 6.

FIG. 8 is a cross-sectional view illustrating another embodiment of the thin film transistor array substrate illustrated in FIG. 6.

9A to 9C are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 7.

10A to 10D are cross-sectional views illustrating in detail a manufacturing method for forming the organic protective film and the spacer illustrated in FIG. 9B.

11 is a cross-sectional view illustrating a thin film transistor array substrate according to a second exemplary embodiment of the present invention.

12 is a cross-sectional view illustrating another form of the common electrode illustrated in FIGS. 7 and 11.

13 is a cross-sectional view illustrating a liquid crystal display panel including a thin film transistor array substrate according to first and second embodiments of the present invention.

<Description of Symbols for Main Parts of Drawings>

2,102: Gate line 4,104: Data line

6,106: gate electrode 8,108: source electrode

10,110 drain electrode 14,114 active layer

16,116: ohmic contact layer 18,28,118,128: protective film

22,122: pixel electrode 24,124: common electrode

26,126 Common line 30,130 Thin film transistor

Claims (14)

A gate line formed on the substrate; A common line formed in parallel with the gate line; A data line interposed to be insulated from the gate line and the common line, and formed between the pixel regions; A thin film transistor formed at an intersection of the gate line and the data line; A common electrode formed in the pixel region and connected to the common line; A pixel electrode connected to the thin film transistor and forming a horizontal electric field with the common electrode in the pixel region; A thin film transistor array substrate comprising: an organic passivation layer formed in the remaining regions other than the pixel region. The method of claim 1, The thin film transistor array substrate further comprises an inorganic protective film formed between the organic protective film and the thin film transistor. The method of claim 2, The pixel electrode is formed on the inorganic protective film. The method of claim 1, The pixel electrode is formed on the gate insulating film. The method of claim 1, The common electrode may be formed on the organic passivation layer and overlap the data line with the organic passivation layer therebetween. The method of claim 1, The common electrode is a thin film transistor array substrate, characterized in that formed on the plane and side of the organic protective film. The method of claim 1, And a spacer formed on the organic passivation layer and integrated with the organic passivation layer. The method of claim 1, The organic protective film is a thin film transistor array substrate, characterized in that formed of an organic insulating material containing acrylic resin, BCB and the like. The method of claim 2, The inorganic protective film is a thin film transistor array substrate, characterized in that formed of an inorganic insulating material containing any one of silicon nitride and silicon oxide. Forming a thin film transistor at an intersection of the gate line, the data line intersecting the gate line and the gate insulating layer, and determining a pixel area; Forming an organic passivation layer on a region other than the pixel region; And forming a pixel electrode connected to the thin film transistor in the pixel region, and forming a common electrode forming a horizontal electric field with the pixel electrode. The method of claim 10, Forming an organic passivation layer in the remaining regions other than the pixel region may include And forming a spacer overlapping any one of the gate line, the data line, and the thin film transistor with the same material as the organic protective film while forming the organic passivation layer. The method of claim 10, Forming the pixel electrode and the common electrode And forming a pixel electrode on the gate insulating film exposed by the organic passivation layer and forming a common electrode on the organic passivation layer. The method of claim 10, And forming an inorganic passivation layer protecting the thin film transistor between the thin film transistor and the organic passivation layer. The method of claim 13, Forming the pixel electrode and the common electrode Forming a pixel electrode on the inorganic passivation layer exposed by the organic passivation layer and forming a common electrode on the organic passivation layer.