KR20050045097A - Driving apparatus of liquid crystal display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device of a liquid crystal display device, and more particularly to a driving device of a liquid crystal display device capable of normally generating a vertical synchronization start signal (STV). A driving device of a liquid crystal display device including a plurality of pixels according to an exemplary embodiment of the present invention includes a signal controller for processing an image signal and a plurality of control signals from an external device, and a control signal from the signal controller based on a control signal from the signal controller. A gate driver configured to output a gate signal to a switching element, wherein the signal controller comprises: a delay unit for delaying and outputting a data enable signal among the control signals; and a generator for generating a gate clock signal based on an output from the delay unit. And a processor configured to send the gate clock signal to the gate driver based on the data enable signal and the data clock signal. The processing unit includes a clock counter to prevent the gate clock signal from going low for a predetermined clock from the rising edge of the data enable signal.

In this manner, by preventing the gate clock signal from going low for a predetermined time, the vertical synchronization start signal STV is prevented from being abnormally generated, thereby displaying a normal screen with no shaking or afterimage of the screen.

Description

Driving device of liquid crystal display {DRIVING APPARATUS OF LIQUID CRYSTAL DISPLAY}

The present invention relates to a drive device for a liquid crystal display device.

A general liquid crystal display device includes two display panels and a liquid crystal layer having dielectric anisotropy interposed therebetween. An electric field is applied to the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. Such liquid crystal displays are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

The liquid crystal display includes a liquid crystal panel assembly in which a signal controller, a gate driver, a data driver, and a pixel are disposed.

The signal controller receives an image signal, a control signal and a clock signal from the outside, processes the image signal and the control signal according to the operating conditions of the liquid crystal panel assembly, and sends them out. The control signal includes a data enable signal DE, a gate clock signal CPV, a vertical synchronization start signal STV, and the like.

Since the data enable signal DE is delayed while processing the image signal and the clock signal, the data enable signal is also output from the signal controller in a slightly delayed form in order to meet this requirement.

The gate clock signal CPV is generated based on this delayed data enable signal, for example, counting a predetermined clock at the rising edge of the data enable signal and then pulling the gate clock signal low. And a predetermined clock counting at the falling edge of the data enable signal and then making the gate clock signal high.

The vertical synchronization start signal STV is generated based on the data enable signal input to the signal controller and the generated gate clock signal. That is, while the input data enable signal is high, the vertical sync start signal STV becomes high on the falling edge of the current gate clock signal and becomes low on the falling edge of the next gate clock signal.

In the case of a liquid crystal display device for a monitor, a screen processing is generally performed in a digital manner. However, since the signal output from the computer itself is an analog signal, an analog to digital converter (ADC) is required. These ADCs can be attached by the end product manufacturer and adjusted to various specifications as needed.

At this time, the clock number of the blank interval of the data enable signal can be adjusted. In general, the clock number has a tolerance range of about 30 to 40 clocks, but any clock number may generate an abnormal gate clock signal.

For example, the falling edge of the current gate clock signal and the rising edge of the next gate clock signal are simultaneously located between the rising edge of the input data enable signal input to the signal controller and the rising edge of the data enable signal delayed by the signal controller. In this case, the vertical synchronization start signal STV is abnormally generated. In this case, an afterimage of the screen may be seen, or the screen may be shaken to deteriorate the image quality.

Accordingly, an object of the present invention is to provide a driving device of a liquid crystal display device capable of generating a normal vertical synchronization start signal regardless of whether an abnormal gate clock signal is generated.

According to an aspect of the present invention, there is provided a driving apparatus of a liquid crystal display device including a plurality of pixels, a signal controller for processing an image signal and a plurality of control signals from the outside, and a signal controller. And a gate driver for outputting a gate signal to the switching element of the pixel based on a control signal of. The signal control unit may include a delay unit for delaying and outputting a first control signal among the control signals, a generation unit for generating a second control signal based on an output from the delay unit, and the first control signal and the second control signal. And a processing unit which sends a third control signal to the gate driver based on the data clock signal. At this time, the processing unit includes a clock counter, and preferably prevents the second control signal from going low for a predetermined clock from the rising edge of the first control signal. The predetermined clock may be 10 clocks.

The first control signal may be a data enable signal indicating whether data exists or not, and the signal controller may provide a vertical synchronization start signal STV for instructing the output of the gate signal to be output based on the third control signal. The second and third control signals may be gate clock signals for controlling the output timing of the gate signals.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a driving device of a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel must display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n .

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal. It consists of a circuit.

The signal controller 600 generates control signals for controlling operations of the gate driver 400 and the data driver 500, and provides the corresponding control signals to the gate driver 400 and the data driver 500.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal, and adjusts the image signals R, G, and B to match the operating conditions of the liquid crystal panel assembly 300. After appropriately processing, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signals R ', G', and B 'are sent to the data driver 500.

The gate control signal CONT1 includes a vertical synchronization start signal STV indicating the start of output of the gate on pulse (gate on voltage section), a gate clock signal CPV for controlling the output timing of the gate on pulse, and a gate on pulse. An output enable signal OE or the like that defines a width.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The data driver 500 sequentially receives and shifts image data R ', G', and B 'corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and generates a gray voltage. The image data R ', G', B 'is converted into the corresponding data voltage by selecting the gray voltage corresponding to each of the image data R', G ', and B' among the gray voltages from the unit 800. Then, it is applied to the corresponding data line D ₁ -D _m .

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. When the switching element Q connected to the () is turned on, the data voltage applied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned on switching element Q.

The difference between the data voltage applied to the pixel and the common voltage V _com is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage. As a result, the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

After one horizontal period (or “1H”) (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 are next. The same operation is repeated for the pixels in the row. In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarity of the data voltage flowing through one data line may be changed (“column inversion”) or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS within one frame ( "Dot reversal")

Meanwhile, as described above, the signal controller 600 generates the data control signal CONT2 and the gate control signal CONT1 and sends them to the data driver 500 and the gate driver 400, respectively. At this time, a method of processing when the gate clock signal CPV and the vertical synchronization start signal STV abnormally occurs among the gate control signals CONT1 will be described with reference to FIGS. 3 to 6.

3 is a block diagram of a signal controller 600 according to an embodiment of the present invention. 4 and 5 illustrate waveforms that occur abnormally when the gate clock signal CPV and the vertical synchronization start signal STV occur normally, and FIG. 6 illustrates vertical synchronization even when the gate clock signal CPV occurs abnormally. It is a diagram showing a waveform in which the start signal STV normally occurs.

As shown in FIG. 3, the signal controller 600 according to an exemplary embodiment of the present invention includes a delay unit 601, a gate clock signal generator 603, and a processor 605.

The delay unit 601 delays and outputs the data enable signal DE by a predetermined clock signal. As described above, the delay unit 601 delays the clock signal by about 3 clocks for synchronizing with a delay time for processing the video signal.

The gate clock signal generator 603 generates a gate clock signal CPV based on the data enable signal DE ′ from the delay unit 601. As described above, the gate clock signal CPV is made low after counting a predetermined clock on the rising edge of the data enable signal DE 'and the gate clock signal CPV is made high after counting the predetermined clock on the falling edge. By creating a full gate clock signal (CPV).

The processor 605 receives the data enable signal DE, the data clock signal HCLK, and the gate clock signal CPV from the outside.

The processor 605 includes a clock counter (not shown) to count the data clock HCLK, which counts by a predetermined clock from the rising edge of the data enable signal DE. For example, about 10 clocks are counted. At this time, the processing unit 605 prevents the gate clock signal CPV from going low until 10 clocks have passed, and only after 10 clocks have elapsed.

4 to 6, the operation of the processor 605 will be described in detail.

4 through 6 illustrate waveforms of the data enable signal DE, the delayed data enable signal DE ′, the gate clock signals CPV and CPV ′ and the vertical synchronization start signal STV.

4 and 5 show generation of normal and abnormal gate clock signals CPV and vertical synchronization start signal STV, respectively.

In the case of FIG. 4, when the gate clock signal CPV is generated in synchronization with the delayed data enable signal DE ′ as described above, the vertical synchronization start signal STV is generated at the falling edge of the current gate clock signal CPV. It goes high and goes low on the falling edge of the next gate clock signal CPV.

In contrast, in the case of FIG. 5, the gate clock signal CPV falls and rises between the rising edge of the data enable signal DE and the delayed data enable signal DE ′. In this case, the vertical synchronization start signal STV becomes high on the falling edge of the current gate clock signal CPV and becomes low on the falling edge of the next gate clock signal CPV to the vertical synchronization start signal STV of FIG. 4. The width becomes narrower.

On the other hand, in the case of FIG. 6, even if the gate clock signal CPV abnormally occurs, the processing unit 605 prevents the gate clock signal CPV from going low for a predetermined clock. As a result, the gate clock signal CPV ′ generated by the processing unit 605 continues to be high as shown in the drawing, so that the vertical synchronization start signal STV is normally generated.

In this manner, the vertical synchronization start signal STV is normally generated by preventing the gate clock signal CPV from going low for a predetermined clock on the rising edge of the data enable signal DE, thereby preventing image blur or afterimages. You can prevent it from being seen.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a signal controller of a liquid crystal display according to an exemplary embodiment of the present invention.

4 and 5 are diagrams illustrating normal and abnormal occurrence waveforms of a gate clock signal and a vertical synchronization start signal.

6 is a waveform diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

Claims (6)

A driving device of a liquid crystal display device including a plurality of pixels, A signal controller which processes an image signal and a plurality of control signals from the outside, A gate driver for outputting a gate signal to a switching element of the pixel based on a control signal from the signal controller; Including, The signal controller A delay unit for delaying and outputting a first control signal among the control signals; A generation unit for generating a second control signal based on the output from the delay unit, and A processor which sends a third control signal to the gate driver based on the first control signal, the second control signal, and the data clock signal Driving device for a liquid crystal display comprising a. In claim 1, And the processing unit includes a clock counter and prevents the second control signal from going low for a predetermined clock from the rising edge of the first control signal. In claim 2, And the predetermined clock is 10 clocks. In claim 3, And the first control signal is a data enable signal indicating the presence or absence of data. In claim 4, And the signal controller generates a vertical synchronization start signal (STV) for instructing to start outputting the gate signal based on the third control signal. In claim 5, And the second and third control signals are gate clock signals for controlling the output timing of the gate signals.