KR20050036589A - Driving method of plasma display panel and plasma display device - Google Patents

Abstract

A method of varying an address pulse width applied to an address electrode of a plasma display panel in an address period is provided. The screen load ratio is calculated from the input video signal, and the length of the idle period according to the change of the number of sustain discharge pulses is calculated when the total number of sustain discharge pulses is changed according to the screen load ratio. The amount of change in one address pulse width is calculated by dividing the length of the rest period by the total number of subfields and the total number of lines. This change is reflected in the turn-on time of the switch connected to the power supply in the power recovery circuit. In this way, the address pulse width can be sufficiently secured, and address discharge can be stably generated.

Description

Driving method of plasma display panel and plasma display device {DRIVING METHOD OF PLASMA DISPLAY PANEL AND PLASMA DISPLAY DEVICE}

The present invention relates to a driving circuit of a plasma display panel (PDP), and more particularly to an address driving circuit for applying an addressing voltage.

A plasma display panel is a flat display device that displays characters or images by using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, the electrode is exposed without the insulating discharge space, so that the current flows in the discharge space while the voltage is applied, and there is a disadvantage in that a resistance for limiting the current must be made. On the other hand, an AC plasma display panel has an advantage of having a longer lifetime than a DC type because the dielectric layer covers the electrode, thereby limiting the current by forming a natural capacitance component and protecting the electrode from the impact of ions during discharge.

1 is a partial perspective view of an AC plasma display panel.

As shown in FIG. 1, the scan electrode 4 and the sustain electrode 5 covered with the dielectric layer 2 and the protective film 3 are arranged in parallel on the glass substrate 1. On the glass substrate 6, a plurality of address electrodes 8 covered with the insulator layer 7 are provided. The partition 9 is formed on the insulator layer 7 between the address electrodes 8 in parallel with the address electrode 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both side surfaces of the partition wall 9. The glass substrates 1 and 2 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

2 shows an electrode arrangement diagram of a plasma display panel.

As shown in FIG. 2, the electrodes of the plasma display panel have a matrix form of n × m. Specifically, the address electrodes A ₁ to A _m are arranged in the column direction and the scan electrodes (in the row direction). Y _{1 to} Y _n and sustain electrodes X _{1 to} X _n are arranged. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG.

In general, such an AC-type plasma display panel is driven by dividing a frame into a plurality of subfields, and each subfield is composed of a reset period, an addressing period, and a sustain period.

The reset period is a period of initializing the state of each cell in order to perform an addressing operation smoothly on the cell, and the addressing period is obtained by addressing a cell (addressed cell) that is turned on to select a cell that is turned on and a cell that is not turned on. This is the period during which wall charges are accumulated. The sustain period is a period in which a discharge for actually displaying an image on the addressed cell is applied by applying a sustain discharge voltage pulse.

In this way, since all subfields contain address periods, the length of the address periods assigned to each subfield is inevitably shortened. As described above, when the widths of the pulses applied to the scan electrode and the address electrode selected in the address period are shortened, the probability of a defect occurring in the address discharge increases. If a failure occurs in the address discharge, a failure occurs in which the discharge does not occur in the discharge cell to be turned on in the sustain period.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method and a driving apparatus for a plasma display panel in which an address discharge can easily occur in an address period.

In order to solve this problem, the present invention reflects the length of the rest period, which depends on the screen load ratio, in the address pulse width.

According to one aspect of the present invention, a plasma display device is provided. In the plasma display device, one frame is driven by being divided into a plurality of subfields having respective weights, and each subfield includes an address period for selecting a discharge cell to be turned on from among the plurality of discharge cells, and each subfield for the selected discharge cell. And a sustain period for discharging for a time corresponding to the weight. The plasma display device includes a plurality of address electrodes formed in one direction and a plurality of scan electrodes formed in a direction intersecting the address electrodes, and a plasma in which discharge cells are formed in an area where the scan electrodes and the address electrodes intersect. While the display panel and the scan electrode are sequentially selected, a driver for selecting a discharge cell to be turned on by applying an address pulse to an address electrode of the discharge cell to be turned on among the discharge cells adjacent to the selected scan electrode, and a controller for determining the width of the address pulse. Include. The controller calculates the length of the sustain period according to the screen load ratio, calculates the length of the pause period of one frame according to the length of the sustain period, and the address pulse width to be changed from the calculated length of the pause period. And an address pulse width determiner for determining the?

According to an embodiment of the present invention, the screen load ratio may be determined from a level of an input video signal.

According to another embodiment of the present invention, the controller calculates address data indicating a subfield to be turned on for each discharge cell from the input image signal, and the screen load ratio may be determined from the address data.

According to another embodiment of the present invention, the address pulse width to be changed may correspond to the length of the rest period divided by the number of subfields in one frame and the number of scan electrodes sequentially selected in one subfield. .

According to another embodiment of the present invention, when the screen load ratio is high, the length of the sustain period can be shortened and the address pulse width can be increased.

According to another embodiment of the present invention, the driving unit, the first switching element is electrically connected between the first power supply for supplying the first voltage and the address electrode through the address selection circuit, the second supply for supplying the second voltage A second switching element electrically connected between a power supply and an address electrode through an address selection circuit, at least one inductor electrically connected with a first end through an address selection circuit to an address electrode, and second and third terminals of the inductor A third switching element electrically connected between the third power supply for supplying a voltage, and a fourth switching element electrically connected between the second end of the inductor and the third power supply, wherein the address pulse is a first switching element. May be turned on and applied.

According to another embodiment of the present invention, the driver may determine the turn-on time of the first switching element according to the address pulse width to be changed determined by the address pulse width determiner.

According to another embodiment of the present invention, for a first address electrode which is selected by an address selection circuit among a plurality of address electrodes and to which an address pulse is applied, the driving unit turns on the third switching element and passes the first address through the inductor. Increasing the voltage of the electrode, turning on the first switching element to maintain the first voltage at the first address electrode, turning on the fourth switching element to decrease the voltage at the first address electrode, and turning on the second switching element The voltage of the first address electrode may be maintained at the second voltage.

According to another embodiment of the present invention, the third power source is a capacitor, and the second switching element may be turned off during the address period.

According to another embodiment of the present invention, for a first address electrode which is selected by an address selection circuit among a plurality of address electrodes and to which an address pulse is applied, the driving unit turns on the third switching element and passes the first address through the inductor. Increase the voltage of the electrode, turn on the first switching element to maintain the voltage of the first address electrode at the first voltage, turn on the fourth switching element with the first switching element turned on, and charge the capacitor; The voltage of the first address electrode may be reduced by turning off the first switching element.

According to another feature of the invention, a plurality of address electrodes formed in one direction, a plurality of scan electrodes formed in a direction crossing the address electrode, the discharge cells are formed in the region where the scan electrode and the address electrode intersect A method of driving a plasma display panel is provided. In this driving method, one frame is driven by being divided into a plurality of subfields having respective weights, each subfield being an address period for selecting a discharge cell to be turned on from among a plurality of discharge cells, and each subfield for the selected discharge cell. And a sustain period for discharging for a time corresponding to the weight. The driving method may include: calculating a screen load ratio from an input image signal, calculating a length of a pause period of one frame according to the screen load ratio, and determining an address pulse width to be changed from the calculated length of the idle period And adjusting the turn-on time of the switching element electrically connected between the power supply for supplying the voltage corresponding to the address pulse and the address electrode according to the address pulse width to be changed.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. When a part is connected to another part, this includes not only a direct connection but also an indirect connection between other elements in between.

A plasma display device, a driving device and a driving method of the plasma display panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

3 is a schematic conceptual diagram of a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 3, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, an address driver 200, a scan / hold driver 300, and a controller 400. In FIG. 3, the scan / maintenance driver 300 is illustrated as one block. However, in general, the scan / maintenance driver 300 is formed separately from the scan driver and the sustain driver.

The plasma display panel 100 includes a plurality of column address electrode extending in a direction (A ₁ ~A _m), the plurality of scan electrodes extending yirumyeonseo in pairs in the row direction (Y ₁ ~Y _n) and a plurality of sustain electrodes ( X _{1 to} X _n ). The address driver 200 applies an address signal for selecting a discharge cell to be displayed to receive the address driving control signal from the controller 400 to the address electrodes (A ₁ ~A _m). The scan / hold driver 300 receives the sustain discharge control signal from the controller 400 and alternately inputs a sustain discharge pulse to the scan electrodes Y _{1 to} Y _n and the sustain electrodes X _{1 to} X _n to discharge cells selected. Perform a maintenance discharge on. The control unit 400 receives an image signal from the outside, generates an address driving control signal and a sustain discharge control signal, and applies them to the address driver 200 and the scan / sustain driver 300, respectively.

In general, a plasma display panel is driven by dividing one frame into a plurality of subfields, and a discharge cell to be discharged is selected among the plurality of discharge cells in an address period of each subfield. At this time, in order to select the discharge cells, in the address period, the selection voltage is sequentially applied to the scan electrodes, and the scan electrodes to which the selection voltage is not applied are biased with a positive voltage. An address pulse is applied to an address electrode passing through the discharge cell to be selected from among the plurality of discharge cells formed by the scan electrode to which the selection voltage is applied, and a reference voltage is applied to the address electrode that is not selected. In general, a positive voltage is used as the voltage of the address pulse and a ground voltage or a negative voltage is used as the selection voltage, so that discharge occurs at the address electrode to which the address pulse is applied and the scan electrode to which the selection voltage is applied, thereby selecting the corresponding discharge cell. . And ground voltage is often used as a reference voltage. In the following, the width in which the address voltage is applied to the address electrode when one scan electrode is selected is defined as the "address pulse width", and the period until the one scan electrode is selected and the next scan electrode is selected is the "address pulse". Period ".

The control unit 400 according to an embodiment of the present invention calculates a load ratio according to the signal level of the input video signal, and outputs a control signal for controlling the address pulse width based on the load ratio. Hereinafter, the controller 400 according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 4.

4 is a block diagram illustrating a controller 400 of a plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the controller 400 according to an exemplary embodiment of the present invention includes an address period determiner 410 and an address data generator 420, and the address period determiner 410 includes a load factor calculator 410. 411, a pause period calculator 412, and an address pulse width determiner 413.

The load factor calculator 411 of the address period determiner 410 calculates the screen load factor L / R for each frame from the input video signal. In general, the screen load ratio L / R is given as an average of the input image signal levels as shown in Equation 1 below.

Here, R _ij , G _ij , and B _ij are levels of R, G, and B video signals input, respectively, i and j represent rows and columns, and M and N represent the number of rows and columns.

The idle period calculator 412 determines the idle period in one frame according to the screen load ratio L / R. In general, when the screen load ratio L / R is high, many discharge cells are turned on, and when the discharge cells are turned on, power consumption increases. Therefore, in the plasma display panel, an automatic power control (APC) algorithm is generally applied to determine the total number of sustain discharge pulses allocated to one frame according to the screen load ratio (L / R). In general, one frame is composed of a plurality of subfields, and each subfield has an appropriate weight to express a gray level. At this time, when the total number of sustain discharge pulses is determined, the number of sustain discharge pulses allocated to each subfield is determined according to the weight. If the screen load ratio (L / R) is high, many discharge cells are turned on, and thus a lot of power is consumed, thereby reducing the power consumption by reducing the total number of sustain discharge pulses. As described above, if the number of sustain discharge pulses is reduced, the length of the sustain period assigned to each subfield is reduced, thereby increasing the rest period.

At this time, the length of the idle period is the length of the reset period, the margin between the reset period and the address period, the length of the address period, the margin between the address period and the sustain period, the length of the sustain period, and between the sustain period and the reset period in one frame. It is given by subtracting the margin. At this time, the length of the address period is given by the product of an already determined address pulse period and the number of lines of the scan electrodes, and the length of the sustain period is determined by the total sustain discharge pulse determined by the sustain discharge pulse period and the screen load ratio (L / R). It is given as the product of numbers. Here, the sustain discharge pulse period means a period until one sustain discharge pulse is applied to the scan electrode and the next sustain discharge pulse is applied to the sustain electrode. In this way, the length of the rest period is expressed by the following expression (2).

Where T _rest is the length of the rest period, T _frame is the length of one frame, T _reset is the length of the reset period, M _ra is the margin between the reset period and the address period, T _ap is the address pulse period, and N _l is the number of lines. Where M _as is the margin between the address and sustain periods, T _sp is the sustain discharge pulse period, N _s is the total number of sustain discharge pulses determined by the screen load factor (L / R), and M _sr is between the sustain and reset periods. Indicates margin.

The address pulse width determiner 413 determines whether to increase or decrease the address pulse width from the length T _rest of the pause period determined by the pause period calculator 412. When the length T _{rest of} the rest period is determined, the length T _rest of the rest period is divided and assigned to each subfield, and the allocated length is allocated to each address pulse in each subfield. Therefore, when the change amount of the address pulse width is a value obtained by dividing the length of the idle period allocated to one subfield by the total number of lines N ₁ , this is given by Equation 3.

Here, N _sf represents the number of subfields in one frame.

Address pulse width determination unit 413 thus calculates the change amount (T _a) of the address pulse width, and passes this information to the address driver 200.

The address driver 200 applies an address pulse to the address electrodes (A ₁ ~A _m) in accordance with the address data determined by the address data generating unit 420. The In this case, the address data generator 420 generates data on whether each pixel is turned on in each subfield according to the input image signal. That is, the address data generator 420 generates address data on whether or not to apply an address pulse to an address electrode corresponding to each pixel in each subfield and transmits the address data to the address driver 200.

The address driver 200 applies an address electrode (A ₁ ~A _m) an address pulse to a corresponding pixel is turned on each time a scanning electrode selected according to the address data received from the address data generating section 420. The At this time, an address pulse width to be applied is determined according to the amount of change of the address pulse width (T _a), the address change of the pulse width (T _a) the amount of change of increase is positive if the address pulse width and address pulse width (T _a) is If negative, the address pulse width is reduced.

In FIG. 4, the screen load ratio L / R is calculated from the level of the input video signal. Alternatively, the screen load ratio L / R may be calculated from the address data of the address data generator 420. Since the power consumption of the plasma display panel is determined by the number of discharge cells that are turned on, the load factor determination unit 411 determines the number of discharge cells that are turned on from the address data of the address data generator 420 to determine the screen load factor ( L / R) can be determined.

And the capacity existing between the address electrodes (A ₁ ~A _m) to the address if the address pulse applied to the electrodes in (A ₁ ~A _m) and another electrode _{(X 1 ~X n, Y 1} ~Y n) loading This results in reactive power. In order to recover and reuse such reactive power, the address driver 200 includes a power recovery circuit. Hereinafter, a method of adjusting the address pulse width in the address driver 200 including the power recovery circuit will be described in detail with reference to FIGS. 5 to 10.

5 is a diagram illustrating an address driving circuit according to a first embodiment of the present invention. In FIG. 5, the capacitive component formed by the address electrode and the scan electrode is illustrated as a panel capacitor.

As shown in Fig. 5, the address driving circuit according to the first embodiment of the present invention includes a power recovery circuit 210 and a plurality of address selection circuits 220 _{1 to} 220 _m . The address selection circuits 220 _{1 to} 220 _{m are} connected to the plurality of address electrodes A _{1 to} A _m , respectively, and include two switching elements A _H and A _L , respectively. The switching elements A _H and A _L may be made of a field effect transistor having a body diode, or may be made of other switching elements having the same or similar function. The first terminal of the switching device (A _H) is connected between the power recovery circuit 210 and the address electrodes (A ₁ ~A _m), when the switching element (A _H) is turned on to be supplied from the power recovery circuit 210 address voltage (V _a) is transmitted to the address electrodes (a ₁ ~A _m). The switching device (A _L) is an address electrode (A ₁ ~A _m) and is connected between the reference voltage (ground voltage), the switching device (A _L), the ground voltage is an address electrode (A ₁ ~A _m) when the turn-on Delivered.

In this way, the switching elements A _H and A _{L of the} address selection circuits 220 _{1 to} 220 _m respectively connected to the address electrodes A _{1 to} A _m are turned on or turned off by the control signal, thereby causing the address electrodes A ₁ to be turned off. ~A _m) an address voltage (V _a) or the ground voltage is applied to the. That is, the switching element (A _H) during the address period is turned on and address voltage (V _a) is applied to the address electrode is a selection switching element (A _L) is turned on and the ground voltage applied to the address electrode is not a selection .

The power recovery circuit 210 includes switching elements A _a , A _r , A _f , A _g , inductors L ₁ , L ₂ , diodes D ₁ , D ₂ , and capacitors C ₁ , C ₂ . It includes. The switching elements A _a , A _r , A _f , A _g may be made of field effect transistors having a body diode, or may be made of other switching elements having the same or similar functions. And switching device (A _a) is connected between the second terminal of the switching device (A _H) of the address voltage (V _a) power (or power supply lines) and address select circuit (220 ₁ ~220 _m) for supplying, capacitors (C _1, C ₂₎ are connected in series between a power supply for supplying an address voltage (V _a) and the ground voltage. _First terminals of the inductors L ₁ and L ₂ are connected to the second terminals of the switching elements A _H of the address selection circuits 220 _{1 to} 220 _m , respectively. A switching element Ar and a diode D ₁ are connected in series between the contacts of the capacitors C ₁ , C ₂ and the second terminal of the inductor L ₁ , and the second terminal of the inductor L ₂ The diode D ₂ and the switching element A _f are connected in series between the contacts of the capacitors C ₁ and C ₂ .

At this time, between the inductor (L _1), a diode (D ₁₎ and the switching element (A _r) connection procedure between may vary, as in the inductor (L _2), a diode (D ₂₎ and switching device (A _f) The order of connections can also be changed. The diodes D ₁ and D ₂ are for preventing current paths that may occur due to the body diodes formed in the switching elements _Ar and A _f , respectively, and may be removed if the body diodes do not exist. And the second terminal and the address so that the voltage applied to the address electrodes (A ₁ ~A _m) in the power recovery circuit 210 operates not exceed the address voltage (V _a), a clamping diode (D _3), the inductor (L ₁₎ It can be connected between the power supply for supplying the voltage (V _a ). Similarly, the can be connected between the second terminal of the address electrodes (A ₁ ~A _m) so that the clamping voltage is not smaller than the ground voltage applied to the diode (D ₄₎ is the ground voltage and the inductor (L _2).

And although shown as being a single power recovery circuit 210 connected to Fig. 5 in the address selecting circuit (220 ₁ ~220 _m), to the address selection circuit (220 ₁ ~220 _m) into groups each group The power recovery circuit 210 may be connected. In the Figure 5 but series connection between the capacitors (C _1, C ₂₎ an address voltage (V _a) the supply voltage and the ground voltage, it is also possible to remove the capacitor (C ₁₎ in FIG.

Next, the operation of the address driving circuit according to the first embodiment of the present invention will be described with reference to FIG.

6 is a driving timing diagram of the address driving circuit of FIG. 5. For convenience the address selecting circuits (220 ₁ ~220 _m) In the description of Fig. 6 was omitted, a switch (A _H) is turned-ON address selection circuit only to the address electrodes (A ₁ ~A _m) coupled to (220 ₁ ~220 _m) An address pulse is applied.

And in the mode 6 1 (M1) the switching device (A _g) before the start is turned on is assumed that 0V is applied to the address electrode of the panel capacitor (C _p).

First, the mode 1 (M1) in the switching device (A _g) are turned off is turned on and the switching element (A _r). Then, a resonance path is formed by the capacitor C ₂ , the switching element _Ar , the diode D ₁ , the inductor L ₁ , and the panel capacitor C _p , and the panel capacitor C _p2 is formed by the resonance path. The voltage V _p of increases.

Next, in the mode 2 (M2), when the voltage of the panel capacitor C _p becomes the address voltage V _a , the switching element A _a is turned on and the switching element A _r is turned off to the panel capacitor C _p2. ) voltage (V _p2) of the V are maintained as _a voltage. In mode 2 (M2), since the time when the switching element A _a is turned on becomes the address pulse width, the turn-on time of the switching element A _a is the change amount T _a of the address pulse width at the existing time T _i . Plus time.

In mode 3 M3, switching element A _a is turned off and switching element A _f is turned on. Then, the panel capacitor (C _p), the inductor (L _2), a diode (D _2), the switching device (A _f) and the panel capacitor (C _p) by the resonance path is formed in the resonance path to the capacitor (C _2), The voltage V _p of decreases.

When the voltage V _p of the panel capacitor C _p becomes 0 V, the switching element A _f is turned off and the switching element A _g is turned on in the mode 4 M4 to turn on the voltage of the panel capacitor C _p . (V _p ) is kept at 0V.

Thus mode 1 to the via 4 (M1~M4) power recovery circuit 210 supplies an address voltage (V _a) to the address electrode of the discharge cells to be turned on. The address electrode of the discharge cell that is not turned on is maintained at 0 V through the switching element A _L of the address selection circuit. Also address driver 200 determines a turn-on time of the switching device (A _a) in accordance with the address change of the pulse width (T _a) determined from the received address period 410.

In the first embodiment of the present invention, the address pulse width is adjusted by adjusting the turn-on time of the switching element A _a of the address driving circuit including the power recovery circuit. However, because a sub-field case, and the entire pixels are turned on in the full white pattern is applied when the address voltage (V _a) to all the address electrodes (A ₁ ~A _m) during the address period, the need for the power recovery circuit none. In other words, if the power recovery circuit is used in the full white pattern, unnecessary power is consumed more. Hereinafter, an embodiment in which the power recovery operation is automatically stopped in the power recovery circuit in the case of the full white pattern will be described with reference to FIGS. 7 to 9.

7 is a schematic diagram of an address driving circuit according to a second embodiment of the present invention. The second embodiment the address driving circuit in the switching element (A _g) connected to the ground voltage during the power recovery operation according to the present invention is always turned off. Thus, Fig. 7, was omitted from the diagram of the switching device (A _g), it was also shown for convenience only two adjacent address selecting circuit _{(220 2i-1, 220 2i} ) of the description.

The operation of the address driving circuit of FIG. 7 will be described below by taking a representative pattern displayed on the screen in one subfield as an example. In this exemplary pattern address selection circuit has a full white pattern without a change in the switching (220 ₁ ~220 _m) the number of dot-on switching change / off pattern and an address selection circuit (220 ₁ ~220 _m) of. Such a pattern is determined by the switching of the address selection circuits 220 _{1 to} 220 _m , and the driving timing of the switching elements A _a , A _r , and A _f of the power recovery circuit 210 may be determined even when implementing any pattern. same. The switching change of the address selection circuit means that the turn-on / turn-off operations of the switching element A _H and the switching element A _L of the address selection circuit are repeated when the scan electrodes are sequentially selected. That is, when the scan electrodes are sequentially selected, when the address voltage and the ground voltage are alternately applied to the address electrodes, a lot of switching changes of the address selection circuit occur.

The dot on / off pattern is a display pattern generated by applying an address voltage to the odd and even address electrodes alternately when the scan electrodes are sequentially selected. For example, when the first scan electrode (Y ₁ ) is selected, an address voltage is applied to the odd address electrode to select the odd column of the first row, and the even number when the second scan electrode (Y ₂ ) is selected. An address voltage is applied to the address electrodes to select light emission in the even columns of the second row.

The full white pattern is a display pattern generated by continuously applying address voltages to all address electrodes when the scan electrodes are sequentially selected. That is, the switching elements A _H of all the address selection circuits are always turned on.

As described above, the switching element A _L of the address selection circuit is periodically turned on in the dot on / off pattern and the line on / off pattern, but the switching element A _L is not turned on in the full white pattern. The voltage of the capacitor C ₂ varies in the address driving circuit of FIG. 7 according to whether the switching element A _L is turned on.

1. Dot on / off pattern-see Figure 8

First, a time series operation change of the address driving circuit in the case where a pattern with a large number of switching changes of the address selection circuits 220 _{1 to} 220 _m is displayed by taking a dot on / off pattern as an example will be described with reference to FIG. 8. Here, the operation change is performed in eight modes M1 to M8, and the mode change is caused by the operation of the switching element. The phenomenon referred to as resonance here is not continuous oscillation, and the voltage caused by the combination of the inductor L ₁ or L ₂ and the panel capacitor C _p1 or C _p2 occurring at the turn-on of the switching elements _Ar and A _f and This is a change of current.

8 is a driving timing diagram of the address driving circuit of FIG. 7 for illustrating a dot on / off pattern.

In the case of displaying a dot on / off pattern in the circuit of FIG. 7, the switching element of the address selection circuit 220 _2i-1 connected to the odd-numbered address electrode A _2i-1 when one scan electrode is selected ( The switching element A _L2 of the address selection circuit 220 _2i connected to A _H1 ) and the even-numbered address electrode A _2i is turned on, and the switching element A _H2 and the address selection circuit of the address selection circuit 220 _2i are turned on. 220 _2i-1 ), the switching element A _L1 is turned off. When the next scan electrode is selected, the switching element A _H1 and the switching element A _L2 are turned off and the switching element A _H2 and the switching element A _L1 are turned on. This operation is repeated. When the dot on / off pattern is displayed in this manner, the turn-on / turn-off operation of the switching elements A _H1 and A _H2 and the switching elements A _L1 and A _L2 of the address selection circuits 220 _2i-1 and 220 _2i . This is repeated over and over.

In FIG. 8, the switching elements A _H1 , A _L2 and A _a are turned on and the switching elements A _H2 and A _L1 are turned off before the mode 1 M1 starts, so that the panel capacitor C _p1 has _a voltage V _a. It is assumed that 0V is applied to the panel capacitor C _p2 . In other words, it is assumed that _a voltage V _a is applied to the odd _- numbered address electrode A _2i-1 and 0 V is applied to the even-numbered address electrode A _2i .

First, in the mode 1 M1, the switching elements A _H1 , A _L2 and A _a are turned on and the switching elements A _f are turned on while the switching elements A _H2 and A _L1 are turned off. The power source (V _a), the switching device (A _a), the inductor (L _2), a diode (D _2), the switching device (A _f) and the inductor (L ₂₎ through the path of the capacitor (C ₂₎ and a capacitor ( current is injected to C _2), and the voltage is charged in the capacitor (C _2).

Next, in mode 2 (M2), the switching element A _a is turned off so that the panel capacitor C _p1 , the body diode of the switching element A _H1 , the inductor L ₂ , the diode D ₂ , the switching element ( A _f ) and a capacitor C ₂ form a resonant path. Due to this resonance path, the voltage V _p1 of the panel capacitor C _p1 decreases, and since the switching element A _L2 is turned on, the voltage V _p2 of the panel capacitor C _p2 remains at 0V. And the discharge from the panel capacitor (C _p1), current (energy) is supplied to the capacitor (C _2), and a voltage is charged in the capacitor (C _2).

In the mode 3 M3, the switching elements A _H1 and A _L2 are turned off, the switching elements A _H2 and A _L1 are turned on, and 0 V is applied to the panel capacitor C _p1 . The switching element A _f is turned off and the switching element A _r is turned on so that the capacitor C ₂ , the switching element A _r , the diode D ₁ , the inductor L ₁ , and the switching element A _{H2 are turned on.} ) And a panel capacitor C _p2 . The current is supplied from the capacitor C ₂ by the resonance path to increase the voltage V _p2 of the panel capacitor C _p2 , and the capacitor C ₂ is discharged. At this time, the panel capacitor (C _p2) voltage (V _p2) is V when _a voltage go beyond the switching element (A _a), because the body diode is turned on, the panel capacitor voltage (V _p2) of (C _p2) of the V _a voltage Do not exceed After the panel capacitor C _p2 becomes the voltage V _a , the current remaining in the inductor L ₁ is freewheeled through the body diode of the switching element A _a .

Mode 4 (M4) in the switching device (A _a) is turned on and the switching element (A _r) are turned off, the voltage (V _p2) of the panel capacitor (C _p2) is maintained at _a voltage V.

As described above, the power recovery circuit 210 supplies the voltage V _a to the address electrode A _2i through the switching element A _H2 of the address selection circuit 220 _2i through the modes 1 to 4 (M1 to M4). The address electrode A _2i-1 is maintained at 0 V through the switching element A _L1 of the address selection circuit 220 _2i-1 .

Next, in mode 5 (M5) to mode 8 (M8), only the switching element operation of the address selection circuit is changed and the switching element operation of the power recovery circuit is the same.

The mode 5 (M5) in the switching device (A _{H2, L1} A, A _a) is turned on and the switching element (A _H1, A _L2) is turned on, the switching element (A _f) in the OFF state is turned on. The power source (V _a), the switching device (A _a), the inductor (L _2), a diode (D _2), the switching device (A _f) and the inductor (L ₂₎ through the path of the capacitor (C ₂₎ and a capacitor ( a C ₂₎ current is injected, and a voltage is charged in the capacitor (C _2).

Next, in mode 6 (M6), the switching element A _a is turned off so that the panel capacitor C _p2 , the body diode of the switching element A _H2 , the inductor L ₂ , the diode D ₂ , the switching element ( A _f ) and a capacitor C ₂ form a resonant path. Due to this resonance path, the voltage V _p2 of the panel capacitor C _p2 decreases and the switching element A _L1 is turned on so that the voltage V _p1 of the panel capacitor C _p1 is kept at 0V. And the discharge from the panel capacitor (C _p2), current (energy) is supplied to the capacitor (C _2), and a voltage is charged in the capacitor (C _2).

In mode 7 M7, the switching elements A _H2 and A _L1 are turned off, the switching elements A _H1 and A _L2 are turned on, and 0 V is applied to the panel capacitor C _p2 . The switching element A _f is turned off and the switching element A _r is turned on so that the capacitor C ₂ , the switching element A _r , the diode D ₁ , the inductor L ₁ , and the switching element A _{H2 are turned on.} ) And the panel capacitor C _p1 is formed. Current is supplied from the capacitor C ₂ by the resonance path, so that the voltage V _p1 of the panel capacitor C _p1 increases, and the capacitor C ₂ is discharged. At this time, the panel capacitor (C _p1) voltage (V _p1) is V when _a voltage go beyond the switching element (A _a), because the body diode is turned on, the panel capacitor voltage (V _p1) of (C _p1) of the V _a voltage Do not exceed After the panel capacitor C _p1 becomes the voltage V _a , the current remaining in the inductor L ₁ is freewheeled through the body diode of the switching element A _a .

Mode 8 (M8) in the switching element (A _r) is turned off and turns on the switching element (A _a) the voltage (V _p1) of a panel capacitor (C _p1) is held by _a V voltage.

As described above, the power recovery circuit 210 supplies the V _a voltage to the address electrode A _2i-1 through the switching element A _H1 of the address selection circuit 220 _2i-1 through the modes 5 to 8 (M5 to M8). To supply. The address electrode A _2i is maintained at 0 V through the switching element A _L2 of the address selection circuit 220 _2i . As the operations of the modes 1 to 8 (M1 to M8) are repeated, a dot on / off pattern is realized.

At this time, if the capacitor (C ₂₎ to V _a / 2 voltage is charged and the capacitor (C ₂₎ capacitance is large capacitor (C ₂₎ to V _a / applying a second voltage to the power supply for supplying of the principles of the LC resonance Panel capacitors (C _p1 or C _p2 ) charged to the voltage V _a in modes 2 or 6 (M2 or M6) to 0 V and panel capacitors discharged to 0 V in modes 3 or 7 (M3 or M7) C _p1 or C _p2 ) can be charged up to the voltage V _a .

First, in mode 1 (M1), the current (energy) is supplied to the capacitor (C ₂ ) through the inductor (L ₂ ) in the power supply, and in the mode 2 (M2), the panel capacitor (C _p1 ) is discharged and the capacitor (C) is discharged. ₂ ) Current (energy) is supplied. That is, mode 1 and 2 (M1, M2) is the energy in the capacitor (C ₂₎ charging voltage is increased by ΔV1 of the capacitor (C _2). Next, in mode 3 M3, current is supplied from capacitor C ₂ through inductor L ₁ to increase the voltage of panel capacitor C _p2 , and the remaining current is freewheeled. That is, in the mode 3 (M3) is the energy discharged from the capacitor (C ₂₎ the voltage of the capacitor (C ₂₎ is lowered by ΔV2. By the way, assuming that the initial a V _a / 2 voltage in the capacitor (C ₂₎ is charged in, since by the power further supply of energy from the capacitor (C _2), the mode 1 (M1) during charging of the capacitor (C ₂₎ The charging energy is greater than the discharge energy of the capacitor C ₂ . That is, ΔV1 is greater than ΔV2. The energy charged and discharged to the capacitor C ₂ in the modes 5 to 8 (M5 to M8) is also the same as in the modes 1 to 4 (M1 to M4). Since the panel capacitors C _p1 or C _p2 are discharged and charged again in modes 3 or 7 (M3 and M7) after the residual voltage becomes 0 V, the panel capacitors are repeated even if the modes 1 to 8 (M1 to M8) are repeated. The energy discharged from the capacitor C ₂ to charge (C _p1 or C _p2 ) is substantially constant.

However, the capacitor from when the increasing voltage of the capacitor (C ₂₎ charging energy is large capacitor (C ₂₎ than the discharge energy of the mode 1 and 2 (M1, M2) or modes 5 and 6 (M5, M6) (C 2 Decreases the energy charged in That is, when the operations of the modes 1 to 8 (M1 to M8) are repeated repeatedly, the charging energy of the capacitor C ₂ is decreased, and finally, the equilibrium state in which the charging energy and the discharge energy of the capacitor C ₂ are equal to each other. Becomes In equilibrium, the voltage charged in the capacitor C ₂ is greater than the voltage V _a / 2 and smaller than the voltage V _a .

Thus the capacitor to the panel capacitor (C _p1, C _p2) by the principle of resonance in the capacitor is a voltage charged in the (C ₂₎ is greater than V _a / 2 voltage, mode 3, and 7 (M3, M7) (C 2) A voltage corresponding to twice the voltage of, i.e., _a voltage greater than the voltage V _a may be charged. Therefore, even when a parasitic component exists in the address driving circuit, the voltage of the panel capacitors C _p1 and C _p2 may increase to the voltage V _a due to resonance, and thus the switching element A _a may be zero voltage switching. Can be.

2. Full White Pattern-see Figure 9

Taking a full white pattern as an example, the time-series operation change of the address driving circuit in the case of displaying a pattern with little switching change of the address selection circuits 220 _{1 to} 220 _m will be described with reference to FIG. 9. Here, the operation change is sequential in four modes M1 to M4, and the mode change is caused by the operation of the switching element. In addition, the phenomenon called resonance is not continuous oscillation, and the voltage caused by the combination of the inductor L ₁ or L ₂ and the panel capacitor C _p1 , C _p2 occurring at the turn-on of the switching elements _Ar and A _f and This is a change of current.

9 is a driving timing diagram of the address driving circuit of FIG. 7 for illustrating a full white pattern. In the case of displaying the full white pattern in the circuit of FIG. 9, the switching elements A _H1 and A _H2 of the address selection circuits 220 _2i-1 and 220 _2i are always turned on while the scan electrodes are sequentially selected.

In FIG. 9, it is assumed that the switching elements A _H1 , A _H2 , and A _a are turned on before the mode 1 M1 is started, so that _a voltage V _a is applied to the panel capacitors C _p1 and C _p2 .

First, in mode 1 M1, the switching element A _f is turned on while the switching elements A _H1 , A _H2 and A _a are turned on. Then, as in the mode 1 M1 of FIG. 8, current is injected into the inductor L ₂ and the capacitor C ₂ to charge the capacitor C ₂ .

Next, in mode 2 (M2), switching element Aa is turned off, so that panel capacitors C _p1 and C _p2 , body diodes of switching elements A _H1 and A _H2 , inductor L ₂ , diode D _2. ), A switching path A _f and a capacitor C ₂ form a resonance path. By the resonance path, the voltages V _p1 and V _p2 of the panel capacitors C _p1 and C _p2 decrease, and the voltage is charged in the capacitor C ₂ as in the mode 2 M2 of FIG. 8.

In mode 3 (M3), switching element A _f is turned off and switching element A _r is turned on, so that capacitor C ₂ , switching element A _r , diode D ₁ , and inductor L ₁ The resonance path is formed by the switching element A _H2 and the panel capacitors C _p1 and C _p2 . By this resonance path, the voltages V _p1 and V _p2 of the panel capacitors C _p1 and C _p2 increase and the capacitor C ₂ is discharged. At this time, when the voltages V _p1 and V _{p2 of the} panel capacitors C _p1 and C _p2 exceed the voltage V _a , the body diode of the switching element Aa is turned on so that the voltages of the panel capacitors C _p1 and C _p2 are turned on. Does not exceed the voltage V _a .

Mode 4 (M4) in the switching device (A _r) is turned off and is turned on and the switching element (Aa) is maintained at a voltage (V _p1, V _p2) is V _a voltage of the panel capacitor (C _p1, C _p2).

Thus, through the mode 1 to 4 (M1~M4) power recovery circuit 210 includes a switching element (A _{H1, H2} A), the address electrode (A _2i- through the address selecting circuit _{(220 2i-1, 220 2i} ) ₁ , A _2i ) to supply the voltage V _a . When the full white pattern is displayed, the modes 1 to 4 (M1 to M4) are repeated while the switching elements A _H1 and A _H2 are continuously turned on.

At this time, since the switching elements A _L1 and A _L2 of the address selection circuits 220 _2i-1 and 220 _2i are not turned on in the full white pattern, the residual voltages of the panel capacitors C _p1 and C _p2 are not discharged. That is, the mode 2 back through the (M2) the panel capacitor (C _p1, C _p2) is the mode 3, after the discharge, the panel capacitor (C _p1, C _p2) while the residual voltage is not discharged (M3) through the Is charged. Therefore, assuming that energy is recovered and used 100%, the energy charging the capacitor C ₂ in the mode 2 (M2) and the energy discharged from the capacitor C ₂ in the mode 3 (M3) become substantially the same. However, the capacitor (C ₂₎ to supply a current to the capacitor (C ₂₎ for since the process of the mode 1 (M1) for charging further perform, in the case of displaying the full white pattern, the voltage charged in the capacitor (C ₂₎ (ΔV1 ) Is always greater than the voltage ΔV2 discharged from the capacitor C ₂ .

When the voltage of the capacitor (C ₂₎ of the process, when the voltage (ΔV1) to be charged is larger than the voltage (ΔV2) is discharged from the capacitor (C _2), Mode 1 to 4 (M1~M4) repeated in the capacitor (C ₂₎ Will increase. Then, when the voltage of the capacitor (C ₂ ) increases, the current discharged from the panel capacitors (C _p1 , C _p2 ) to the capacitor (C ₂ ) in the mode 2 (M2) decreases, thereby discharging the panel capacitors (C _p1 , C _p2 ). The amount is reduced. That is, as shown in FIG. 9, when the processes of the modes 1 to 4 (M1 to M4) are repeated, the amount of the voltages V _p1 and V _{p2 of} the panel capacitors C _p1 and C _p2 decreases.

And since the voltage (V _p1, V _p2) of when the voltage of the capacitor (C ₂₎ increasing haejimyeon substantially equal to V _a voltage, a panel capacitor (C _p1, C _p2) equal to the voltage of the capacitor (C ₂₎ In the mode 2 (M2), the panel capacitors C _p1 and C _p2 do not discharge. And the mode 2 (M2) the panel capacitor (C _p1, C _p2) voltage (V _p1, V _p2) is not reduced mode 3 the panel capacitor (C _p1, C _p2) in (M3) in the not charged. As such, when the voltage of the capacitor C ₂ increases to the voltage V _a , substantially no current moves in the modes 2 and 3 (M2 and M3). That is, when the full white pattern is displayed, the power recovery circuit 210 does not substantially operate.

As described above, in the power recovery circuit according to the second embodiment of the present invention, the voltage level of the capacitor C ₂ is changed by the switching operation of the address selection circuit so that the operation of the power recovery circuit is set. At this time, the voltage of the capacitor (C ₂₎ is determined by the energy discharged from the energy charged in the capacitor (C ₂₎ and a capacitor (C _2). And a capacitor (C ₂₎ charging energy is composed of a discharge energy of the energy to the panel capacitor is supplied through the inductor from the electrical discharge energy of the capacitor (C ₂₎ is made on a charge energy of the panel capacitor, the capacitor (C ₂₎ half of the address voltage (V _a / 2) If the terminal voltage of the level, the charge energy of the capacitor (C ₂₎ is greater than the discharge energy of the capacitor (C _2).

However, in the case of the dot on / off pattern, since the panel capacitor charged up to the address voltage is completely discharged to the ground voltage by turning on the switching element A _L of the address selection circuit, the panel capacitor is charged again to the address voltage, so that the operation is repeated. Even if the discharge energy of the capacitor C ₂ , which is the charge energy of the panel capacitor, is almost constant. On the other hand, a capacitor (C ₂₎ substantially V _a / 2 the voltage in the charge capacitor (C ₂₎ increasing the voltage of the capacitor (C ₂₎ charging energy is larger than the discharge energy, and of this capacitor (C ₂ in accordance with the Decreases the charging energy. Therefore, if the operation is repeated by reducing the charge energy of the capacitor (C ₂₎ be an equilibrium state becomes substantially the same as the discharge energy of the capacitor (C ₂₎ is made as the power recovery operation.

In other words, the address selecting circuit, the panel capacitor is charged after being fully discharged from a plurality of panel capacitors connected to the (220 ₁ ~200 _m) switching the change many address selection circuit (220 ₁ ~200 _m) to the ground voltage to the address voltage In many cases, capacitor C ₂ is charged to _a voltage between the voltage V _a / 2 to the voltage V _a to perform a power recovery operation.

In the case of the full white pattern, the switching element A _L connected to the panel capacitor charged up to the address voltage is not turned on. However, the capacitor does (C ₂₎ becomes larger than a V _a / 2 voltage the voltage of the charging energy is large capacitor (C ₂₎ than the discharge energy, the voltage of the panel capacitor by the resonance of the inductor and the panel capacitor is not discharged until a ground voltage . In addition, since the switching element A _L connected to the panel capacitor that has been charged up to the address voltage is not turned on, a residual voltage is generated in the panel capacitor. Due to this residual voltage, the charging energy of the panel capacitor and the discharge energy of the panel capacitor are equally reduced, and accordingly, the voltage of the capacitor C ₂ continues to increase. As the voltage of the capacitor C ₂ increases, the residual voltage of the panel capacitor also increases, so that there is almost no energy charged and discharged in the panel capacitor, so that little energy is consumed in the power recovery circuit.

The power recovery operation is hardly performed like the full white pattern even in a pattern in which only one color is displayed on all screens or a pattern in which address voltage is continuously applied only to a certain amount of address electrodes.

As described above, in the second embodiment of the present invention, the power recovery operation is performed in the pattern requiring the power recovery operation due to the large number of switching variations of the address selection circuit, and the power recovery operation in the pattern in which the switching recovery of the address selection circuit is almost unnecessary and the power recovery operation is not necessary. Does not automatically. Also it controls the turn-on time of the switching device (A _a) in accordance with the change amount (T _a) of the address pulse width as in the first embodiment in the second embodiment of the present invention.

Above, in the first and second embodiments of the present invention, the capacitor (C ₂₎ is however different from the inductor (L ₁₎ and capacitor inductor (L ₂₎ that is used to charge the (C ₂₎ to be used there is the discharge, FIG. 10 An inductor L may be used as shown. That is, as shown in FIG. 10, the first terminal of the inductor L is connected to the second terminal of the switching element A _H of the address selection circuit 220 _{1 to} 220 _m , and the second terminal of the inductor L is connected. The diodes D ₁ and D ₂ may be connected in parallel. In this manner, the current discharged from the capacitor (C ₂₎ current and the capacitor (C ₂₎ to be filled in the flows to all through the inductor (L).

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, the address discharge can be stably caused by allocating the length of the rest period that increases with the screen load ratio L / R to the address pulse width.

1 is a partial perspective view of an AC plasma display panel.

2 shows an electrode arrangement diagram of a plasma display panel.

3 is a schematic conceptual diagram of a plasma display device according to an exemplary embodiment of the present invention.

4 is a block diagram illustrating a controller of a plasma display panel according to an exemplary embodiment of the present invention.

5 is a diagram illustrating an address driving circuit according to a first embodiment of the present invention.

6 is a driving timing diagram of the address driving circuit of FIG. 5.

7 is a schematic diagram of an address driving circuit according to a second embodiment of the present invention.

8 is a driving timing diagram of the address driving circuit of FIG. 7 for illustrating a dot on / off pattern.

9 is a driving timing diagram of the address driving circuit of FIG. 7 for illustrating a full white pattern.

10 is a diagram illustrating an address driving circuit according to a third embodiment of the present invention.

Claims (20)

Each frame is driven by dividing a frame into a plurality of subfields having respective weights, each subfield corresponding to an address period for selecting a discharge cell to be turned on among a plurality of discharge cells and a weight of each subfield for the selected discharge cell. A plasma display device comprising: a sustain period for discharging for a time period; A plasma display panel including a plurality of address electrodes formed in one direction and a plurality of scan electrodes formed in a direction crossing the address electrodes, wherein the discharge cells are formed in an area where the scan electrodes and the address electrodes intersect. , A driving unit for selecting the discharge cells to be turned on by applying an address pulse to the address electrodes of the discharge cells to be turned on among the discharge cells adjacent to the selected scan electrodes while the scan electrodes are sequentially selected; and A controller for determining a width of the address pulse Including; The control unit, A pause period calculating unit for calculating a length of the sustain period according to a screen load ratio, and calculating a length of a pause period of one frame according to the length of the sustain period, and And an address pulse width determiner configured to determine an address pulse width to be changed from the calculated length of the idle period. The method of claim 1, And the screen load ratio is determined from a level of an input video signal. The method of claim 1, The control unit calculates address data indicating a subfield to be turned on for each discharge cell from the input image signal, And the screen load ratio is determined from the address data. The method of claim 1, The address pulse width to be changed corresponds to a value obtained by dividing the length of the idle period by the number of subfields in one frame and the number of scan electrodes sequentially selected in one subfield. The method according to any one of claims 1 to 4, When the screen load ratio is high, the length of the sustain period is shortened and the address pulse width is increased. The method according to any one of claims 1 to 4, The driving unit, A first switching element electrically connected between a first power supply for supplying a first voltage and the address electrode through an address selection circuit; A second switching element electrically connected between the second power supply for supplying a second voltage and the address electrode through the address selection circuit; At least one inductor having a first end electrically connected to the address electrode through the address selection circuit; A third switching element electrically connected between a second end of the inductor and a third power supply for supplying a third voltage; and A fourth switching element electrically connected between the second end of the inductor and the third power source, And the address pulse is applied when the first switching element is turned on. The method of claim 6, And the driver determines a turn-on time of the first switching element according to the address pulse width to be changed determined by the address pulse width determiner. The method of claim 7, wherein A first address electrode selected by the address selection circuit among the plurality of address electrodes and to which the address pulse is applied, The driving unit may turn on the third switching device to increase the voltage of the first address electrode through the inductor, turn on the first switching device to maintain the first voltage at the first address electrode, and And turning on a fourth switching element to decrease the voltage of the first address electrode, and turning on the second switching element to maintain the voltage of the first address electrode at the second voltage. The method of claim 6, And the third power supply is a capacitor. The method of claim 9, And the second switching element is turned off during the address period. The method of claim 10, A first address electrode selected by the address selection circuit among the plurality of address electrodes and to which the address pulse is applied, The driving unit turns on the third switching element to increase the voltage of the first address electrode through the inductor, and turns on the first switching element to maintain the voltage of the first address electrode at the first voltage. And turning on the fourth switching element to charge the capacitor while the first switching element is turned on, and turning off the first switching element to reduce the voltage of the first address electrode through the inductor. Device. The method of claim 6, The driving unit includes a first diode formed in a path between the second end of the inductor, the third switching element and the third power source, and a path between the second end of the inductor, the fourth switching element and the third power source. Further comprising a second diode formed in, And an anode direction of the first diode and the second diode is opposite. A plasma display panel including a plurality of address electrodes formed in one direction and a plurality of scan electrodes formed in a direction crossing the address electrodes, wherein the discharge cells are formed in an area where the scan electrodes and the address electrodes intersect. In the method of driving, Each frame is driven by dividing a frame into a plurality of subfields having respective weights, each subfield corresponding to an address period for selecting a discharge cell to be turned on among a plurality of discharge cells and a weight of each subfield for the selected discharge cell. A sustain period for discharging for a time period, The driving method, Calculating a screen load ratio from an input video signal; Calculating a length of a pause period of one frame according to the screen load ratio; Determining an address pulse width to be changed from the calculated length of the rest period, and Adjusting a turn-on time of a switching element electrically connected between a power supply for supplying a voltage corresponding to the address pulse and the address electrode according to the address pulse width to be changed; Method of driving a plasma display panel comprising a. The method of claim 13, And the screen load ratio is calculated by accumulating the level of the input image signal. The method of claim 13, And calculating the screen load ratio by calculating address data indicating subfields to be turned on for each discharge cell from the input image signal. The method of claim 13, And calculating the address pulse width to be changed by dividing the length of the idle period by the number of subfields in one frame and the total number of scan electrodes sequentially selected in one subfield. The method according to any one of claims 13 to 16, And applying the address pulse to a first address electrode corresponding to a discharge cell to be turned on among the plurality of address electrodes. The method of claim 17, Increasing the voltage of the first address electrode through a first inductor having a first end electrically connected to the first address electrode; Maintaining a voltage of the first address electrode at a first voltage substantially; Supplying a current to a second inductor electrically connected to the first address electrode while maintaining the voltage of the first address electrode substantially at the first voltage, and Reducing the voltage of the selected first electrode through the second inductor Method of driving a plasma display panel comprising a. The method of claim 18, And a capacitor is electrically connected to a second end of the first inductor and a second end of the second inductor when the voltage of the first address electrode is increased or decreased. The method of claim 19, And the first inductor and the second inductor are the same inductor.