KR20050024593A - method of forming interconnection lines in a semiconductor device - Google Patents

Abstract

PURPOSE: A method of forming interconnection lines in a semiconductor device is provided to prevent an increase of a contact resistance between the interconnection lines and a contact plug due to residues of an etch stop layer by eliminating a process for forming the etch stop layer within an interlayer dielectric. CONSTITUTION: An interlayer dielectric and a hard mask layer are formed on a semiconductor substrate. An interconnection line groove and a hard mask layer pattern are formed by patterning partially the hard mask layer and the interlayer dielectric. A depth of the interconnection line groove is smaller than a thickness of the interlayer dielectric. A photoresist pattern is formed on the semiconductor substrate to form a line-shaped opening. An interconnection line contact hole(316) is formed by etching the interlayer dielectric. A conductive layer pattern is formed to fill the interconnection line contact hole and the interconnection line groove.

Description

Method of forming interconnection lines in a semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a wiring method for a semiconductor device.

As semiconductor devices are highly integrated, the cell size occupied by memory cells per unit area is rapidly decreasing, and a multilayer wiring structure is adopted to fabricate highly integrated semiconductor devices. As a result, the pitch of the line and space (L / S) type or the contact type is reduced, and the aspect ratio of the contact hole connecting the lower wiring layer and the upper wiring layer is increased.

In the case of forming the wiring and the wiring contact having a fine pitch size by the photolithography process, miniaturization of the photoresist pattern is required, and the misalign margin is reduced, and thus there is a limit in reproducing the process.

1 and 2 are cross-sectional views illustrating a conventional bit line forming method.

Referring to FIG. 1, a first interlayer insulating film 102 is formed on a semiconductor substrate 100.

A first photoresist pattern (not shown) is formed on the first interlayer insulating film 102. The first photoresist pattern is formed using a photolithography process to have openings exposing predetermined regions of the first interlayer insulating film 102. The first interlayer insulating layer 102 in the exposed portion is etched using the first photoresist pattern as an etch mask to form a contact hole. The first photoresist pattern is removed.

Subsequently, a conductive film such as a polysilicon film completely filling the contact holes is formed on the entire surface of the semiconductor substrate from which the first photoresist pattern is removed. The conductive layer is planarized until the first interlayer insulating layer 102 is exposed to form contact plugs 104 in the contact holes. The planarization process for forming the contact plugs 104 is performed through a chemical mechanical polishing process or an etch back process. In this case, the contact plugs 104 may be overpolished or overetched. As a result, as shown in FIG. 1, upper surfaces of the contact plugs 104 may be lower than an upper surface of the first interlayer insulating layer 102. In other words, the contact plugs 104 may be recessed during the planarization process.

An etch stop film 106 and a second interlayer insulating film 108 are sequentially formed on the entire surface of the semiconductor substrate having the contact plugs 104. Subsequently, the second interlayer insulating film 108 is planarized. The etch stop layer 106 is formed to fill the recessed regions on the contact plugs 104.

Referring to FIG. 2, a second photoresist pattern (not shown) is formed on the second interlayer insulating film 108. The second photoresist pattern is formed by performing a photolithography process to have openings exposing predetermined regions of the second interlayer insulating film 108. The second interlayer insulating layer 108 and the etch stop layer 106 are etched using the second photoresist pattern as an etch mask. As a result, bit line grooves are formed in the second interlayer insulating film 108. Subsequently, a conductive film such as tungsten is deposited to remove the second photoresist pattern and completely fill the bit line grooves. The conductive layer is planarized to expose the second interlayer insulating layer 108 to form bit lines 110 in electrical contact with the top surfaces of the contact plugs 104 formed in the second interlayer insulating layer 108.

In the etching process for forming the bit line as described above, when the upper surface of the contact plugs 104 is over-etched or over-polished, the etch stop layer is formed on the contact plugs 104. 106 may remain on the contact plugs 104 without being fully etched. As a result, the contact area between the bit lines 110 and the contact plug 104 is reduced and the contact resistance is increased, resulting in poor device characteristics.

In addition, when a misalignment occurs in the above-described photolithography process for forming the bit line, the contact area between the bit lines 110 and the contact plugs 104 is reduced, as well as the contacts adjacent to the bit lines 110. A bridge may be formed between the plugs 104 to cause a malfunction of the semiconductor device.

That is, after the bit line grooves are formed, a pre-cleaning process is performed to remove the natural oxide formed on the upper surface of the polymer and contact plugs 104 formed on the inner wall of the bit line grooves during the etching process. In this process, an upper portion of the first interlayer insulating layer 102 between the contact plugs 104 may be etched. As a result, when the bit line 110 is formed in a subsequent process, the bit line 110 is electrically connected between the two contact plugs 104 in the first interlayer insulating layer 102 under the bit line 110 by the bit line 110. A short circuit occurs. In addition, when the misalignment is severe, the bit lines 110 are formed on the first interlayer insulating layer 102 and the two contact plugs 104 between the two contact plugs 104 so that the two Bridges may be formed between the contact plugs 104.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device wiring method capable of forming a wiring contact without using an etch stop film in an interlayer insulating film.

Another object of the present invention is to provide a wiring method of a semiconductor device for solving the above-described misalignment problem by simultaneously forming contact holes and wiring.

In order to achieve the above technical problem, the present invention provides a wiring method of a semiconductor device by a self align contact method, characterized in that to form a wiring and a wiring contact at the same time using a hard mask film and a photoresist pattern. do.

In the semiconductor device wiring method according to the present invention, an interlayer insulating film and a hard mask film are sequentially formed on a semiconductor substrate. The hard mask layer and the predetermined region of the interlayer insulating layer are sequentially patterned to form parallel wiring grooves in a line shape in the interlayer insulating layer, and the depth of the wiring grooves is smaller than the thickness of the interlayer insulating layer. A photoresist pattern is formed on the semiconductor substrate having the wiring grooves, and the photoresist pattern is formed to have a line-shaped opening that intersects the wiring grooves. Thereafter, the interlayer insulating layer is etched using the photoresist pattern and the hard mask layer as an etch mask to form interconnection contact holes exposing the semiconductor substrate. A conductive layer pattern is formed to fill the wiring contact holes and the wiring grooves.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

3 is a partial plan view of a cell array region of a semiconductor device having a bit line formed according to an embodiment of the present invention. 4A through 7C are cross-sectional views illustrating a method of forming a bit line of a semiconductor device in accordance with an embodiment of the present invention, according to a process sequence. 4A to 7C, FIGS. 4A, 5A, 6A, and 7A are vertical cross-sectional views taken along the line I-I 'of FIG. 3, and FIGS. 4B, 5B, 6B, and 7B are II-II of FIG. These are vertical cross sections in the II 'direction. 5C and 7C are vertical cross-sectional views in the III-III ′ direction of FIG. 3.

3, 4A, and 4B, a field oxide (FOX) is formed in the semiconductor substrate 300 to define the active regions 301. This is done by, for example, a process such as local oxidation of silicon (LOCOS) or shallow trench isolation (STI). Thereafter, gate patterns 302 are formed on the semiconductor substrate 300 to cross the active regions 301. The gate patterns 302 may correspond to stacked gate patterns of a flash memory device. An interlayer insulating film 304 and a hard mask film are sequentially deposited on the semiconductor substrate having the gate patterns 302. The interlayer insulating film 304 is formed of, for example, an SiO ₂ film, and the hard mask film is formed of, for example, a SiON film or a SiN film.

A first photoresist pattern 308 is formed on the hard mask layer. The first photoresist pattern 308 has a line-shaped opening that exposes a predetermined region of the hard mask layer. Subsequently, the hard mask layer 306 is etched using the first photoresist pattern 308 as an etch mask, and then the interlayer dielectric layer 304 is etched to a predetermined depth to form bit line grooves in the interlayer dielectric layer 304. 310 are formed. As a result, the bit line grooves 310 are formed in a parallel line shape, and a hard mask layer pattern 306 masked by the first photoresist pattern 308 is formed between the bit line grooves 310. . The bit line grooves 310 are formed to have a depth smaller than the thickness of the interlayer insulating layer 304.

3, 5A, 5B, and 5C, after removing the first photoresist pattern 308, the second photoresist pattern 312 is formed on the semiconductor substrate on which the bit line grooves 310 are formed. To form. The second photoresist pattern 312 is formed in block units to have an opening having a line shape orthogonal to the bit line grooves 310. As a result, as shown in FIG. 3, the contact opening is defined by the hard mask layer patterns 306 and the second photoresist pattern 312 that are orthogonal to each other.

Referring to FIGS. 3, 6A, and 6B, the interlayer insulating layer 304 is etched using the second photoresist pattern 312 and the hard mask layer pattern 306 as an etching mask to etch the semiconductor. Contact holes 316 are formed to expose the substrate 300.

As described above, according to the present invention, the bit line grooves 310 are formed first, and then the contact is performed without removing the hard mask layer patterns 306 formed parallel to the left and right sides of the bit line grooves 310. The holes 316 are used as etching masks during etching. As a result, the contact holes 316 are formed in the region where the bit line grooves 310 are formed, thereby eliminating a problem caused by misalignment. That is, the hard mask layer patterns 306 may be used continuously without being removed during the process from forming the bit line grooves 310 to forming the contact holes 314 to prevent misalignment. .

3, 7A, 7B, and 7C, after forming the contact holes 316, the second photoresist pattern 312 is removed. A conductive material such as tungsten is deposited on the contact holes 316 and the bit line grooves 310. Subsequently, a planarization process such as chemical mechanical polishing is performed to polish the conductive material until the interlayer insulating layer 304 is exposed to simultaneously form the contact plugs 320 and the bit lines 322.

In this process, preferably, the bit line grooves (eg, for electrical insulation between adjacent bit lines 322 or the contact plugs 320 before forming the contact plugs 320 and the bit lines 322) are formed. The spacers 318 made of SiN may be formed on the inner walls of the 310 and the contact holes 306. In order to form the spacers 318, first, the second photoresist pattern 312 is removed. Subsequently, SiN is deposited and etched back on the semiconductor substrate 300 on which the bit line grooves 310 and the contact holes 316 are formed to form the spacers 318.

As described above, according to the present invention, it is possible to prevent the increase in contact resistance between the wiring and the contact plug due to the residue of the etch stop film by enabling the wiring of the semiconductor element without forming the etch stop film in the interlayer insulating film.

In addition, since the wiring and the contact plug can be simultaneously formed as described above, the misalignment of the wiring and the contact plug can be minimized and the interlayer insulating film deposition process is reduced compared to the prior art, thereby contributing to the process simplification.

1 and 2 are cross-sectional views illustrating a conventional bit line forming method.

3 is a partial plan view of a cell array region of a semiconductor device having a bit line formed according to an embodiment of the present invention.

4A through 7C are cross-sectional views illustrating a method of forming a bit line of a semiconductor device in accordance with an embodiment of the present invention, according to a process sequence.

* Description of the main parts of the drawing *

100,300 semiconductor substrate 102first interlayer insulating film

104,320: contact plug 106: etch stop film

108: second interlayer insulating film 110,322: bit line

302: gate pattern 304: interlayer insulating film

306: hard mask film pattern 308: first photoresist pattern

310: bit line groove 312: second photoresist pattern

316: contact hole 318: spacer

Claims (4)

An interlayer insulating film and a hard mask film are sequentially formed on the semiconductor substrate, Patterning the hard mask layer and a predetermined region of the interlayer insulating layer in order to form parallel wiring grooves and hard mask layer patterns in a line shape in the interlayer insulating layer, wherein the depths of the wiring grooves are smaller than the thickness of the interlayer insulating layer; A photoresist pattern is formed on the semiconductor substrate having the wiring grooves, wherein the photoresist pattern is formed to have an opening in the form of a line crossing the wiring grooves. Forming interconnection contact holes exposing the semiconductor substrate by etching the interlayer insulating layer using the photoresist pattern and the hard mask layer patterns as an etch mask; And forming a conductive film pattern filling the wiring contact holes and the wiring grooves. The method of claim 1, And said hard mask film is a SiON film or a SiN film. The method of claim 1, And forming spacers on sidewalls of the wiring grooves and the wiring contact holes before forming the conductive layer pattern. The method of claim 3, wherein And the spacers are made of SiN.