KR20050023964A - Plasma display panel - Google Patents

Abstract

PURPOSE: A plasma display panel is provided to prevent a current from being concentrated to a part of a pad electrode, by arranging a plurality of current paths on a common electrode line so as to distribute the current. CONSTITUTION: A plasma display panel comprises a first electrode(112Y) and a second electrode(112Z) arranged in parallel with each other on an upper substrate; a common electrode line; and a plurality of pad portions(144a,144b,144c). The common electrode line is formed at one edge of the upper substrate, and connected to one of the first and second electrodes. The common electrode line has a certain part which is removed so as to form a plurality of current paths. The pad portions are formed on the common electrode line such that the pad portions supply a common voltage applied from an external source to one of the first and second electrodes connected to the common electrode line.

Description

Plasma Display Panel {PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel capable of preventing current from being concentrated on a part of a pad electrode.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (hereinafter referred to as "PDPs"), and electroluminescence (Electro). -Luminescence (EL) display.

PDP is a display device using a gas discharge has the advantage that it is easy to manufacture a large panel. As a PDP, a three-electrode AC surface discharge type PDP having three electrodes and driven by an alternating voltage is typical.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a first electrode 12Y and a second electrode 12Z formed on the upper substrate 10, and an address formed on the lower substrate 18. An electrode 20X is provided.

The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the first electrode 12Y and the second electrode 12Z side by side.

As shown in FIG. 2, the first electrode 12Y is connected to the plurality of first electrode pad portions 34 formed at one side of the upper substrate 10 through the link portion 32. Each of the plurality of first electrode pad portions 34 is connected to the plurality of first electrodes 12Y. In this case, the number of the first electrode pad portions 34 varies depending on the size of the panel, but is limited to having six pad portions as an example.

As shown in FIG. 2, the second electrode 12Z is commonly connected to the common electrode line 42 formed at the other edge of the upper substrate 10. In this case, a plurality of second electrode pad portions 44 are formed on the common electrode line 42. Each of the plurality of second electrode pad portions 44 is composed of a plurality of electrodes for connection with a flexible printed circuit film connected to a second electrode driver not shown. The plurality of second electrode pad portions 44 are formed in the middle region of the panel to reduce the number of flexible printed circuit films.

Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 14. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge, and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the first electrode 12Y and the second electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells.

The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne for discharging is injected into the gas discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The three-electrode AC surface discharge type PDP is driven by being divided into a plurality of subfields, and gray scale display is performed by emitting light a number of times proportional to the weight of video data in each subfield period. The subfield is driven again by being divided into an initialization period, an address period, a sustain period, and an erase period.

Here, the initialization period is a period during which uniform wall charges are formed in the discharge cells, the address period is a period during which selective address discharge occurs according to the logic value of the video data, and the sustain period is a discharge cell in which the address discharge has occurred. Is a period for maintaining the discharge. The erasing period is a period of erasing the sustain discharge generated in the sustain period.

Since the common voltage is supplied to the common electrode line 42 in such a PDP, only three flexible printed circuit films can apply sufficient potential. However, since the second pad electrode portion 44 is formed in the center region of the panel, the second pad electrode portion 44 is far from the second electrode lines formed at both ends of the panel. In other words, since the second electrode pad portion 44 is formed in the center region of the panel, the first pad portion 44a formed on the upper side of the second electrode pad portion 44 from the second electrode lines formed at the upper end of the panel. ) The distance to the end becomes longer. Accordingly, most of the current generated in the second electrode lines formed on the upper side of the panel is caused by one pass connected to the common electrode line 42 as shown in FIG. 3A. The problem arises that is concentrated in the padline of the "A" part of. Similarly, the distance from the second electrode lines formed at the lower end of the panel to the end of the third pad portion 44c formed at the lower side of the second electrode pad portion 44 is walked. Accordingly, the current generated in the second electrode lines formed on the lower side of the panel is mostly passed by the third pad part 44c due to one pass connected to the common electrode line 42 as shown in FIG. 3B. A problem arises that is concentrated in the padline of the "B" part of. Therefore, the "A" portion of the first pad portion 44a and the "B" portion of the second pad portion 44c may become hot, and there is a risk of cracking or cracking of the substrate. There is a problem that the temperature difference criteria may be lowered.

Accordingly, an object of the present invention is to provide a plasma display panel capable of preventing current from being concentrated on a part of a pad electrode.

In order to achieve the above object, a plasma display panel according to an embodiment of the present invention is formed on a first electrode and a second electrode parallel to each other on the upper substrate, and formed on one side edge of the upper substrate, the first and second electrodes A common electrode line connected to any one of the common electrodes and partially removed to have a plurality of current paths, and one of the first and second electrodes formed on one side of the common electrode line and connected to the common electrode line A plurality of pads for supplying a common voltage from the outside are provided.

The plurality of current paths is characterized in that formed at least two or more.

Each of the plurality of current paths is formed with a different area.

Each of the plurality of current paths is formed in the same area.

The common electrode line may be partially removed in a quadrangular shape to have a plurality of current paths.

The common electrode line may be partially removed in a trapezoidal shape to have a plurality of current paths.

The part to be removed is characterized in that the same length is removed.

The removed portion is characterized in that it is removed in different lengths.

The common electrode line is divided into a first part having at least three current paths, a second part having at least two current paths, and a third part having at least one current path.

The areas of each of the current paths of the first, second and third portions may be set differently from each other.

The area of the third partial current path is set to be wider than the area of the second partial current path.

The area of the second partial current path is set to be wider than the area of the first partial current path.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 7B.

4 is a diagram illustrating a plasma display panel according to a first embodiment of the present invention.

Referring to FIG. 4, the plasma display panel according to the first embodiment of the present invention is formed on an upper substrate (not shown) on which the first electrode 112Y and the second electrode 112Z are arranged side by side, and at one edge of the upper substrate. A plurality of first pad electrode portions 134 connected to the first electrode 112Y, second pad electrode portions 144 formed on the other edge of the upper substrate, and commonly connected to the second electrode 112Z; And an address electrode (not shown) formed on a lower substrate (not shown).

An upper dielectric layer and a protective film (not shown) are stacked on the upper substrate on which the first electrode 112Y and the second electrode 112Z are formed side by side. Here, wall charges generated during plasma discharge are accumulated in the upper dielectric layer. The protective film prevents damage to the upper dielectric layer due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons.

The first electrode 112Y is connected to the plurality of first electrode pad portions 134 formed at one side of the upper substrate through the link portion 132. Each of the plurality of first electrode pad portions 134 is connected to the plurality of first electrodes 112Y. At this time, the number of the first electrode pad portion 134 varies depending on the size of the panel, but is limited to having six pad portions as an example.

The second electrode 112Z is commonly connected to the common electrode line 142 formed at the other edge of the upper substrate. In this case, a second electrode pad part 144 is formed on the common electrode line 142.

Each of the first to third pad portions 144a, 144b, and 144c of the second electrode pad portion 144 is connected to a plurality of flexible printed circuit films 146 connected to a second electrode driving portion (not shown). It consists of electrodes. The first to third pad parts 144a, 144b, and 144c are formed in the center area of the panel.

In this case, a part of the common electrode line 142 may be removed to prevent current generated in the second electrode lines formed at both ends of the panel from being concentrated on some pad lines of the second electrode pad part 144. Create multiple current paths.

In detail, when the voltage is supplied to the first electrode lines 112Y ₁ to 112Y _n and the common voltage is supplied to the second electrode lines 112Z ₁ to 112Z _n , the first electrode 112Y and the second electrode are provided. Discharge is generated between the electrodes 112Z. The discharge current generated by the discharge between the two electrodes is not shown through the second electrode pad part 44 via the common electrode line 142 _where the second electrode lines 112Z ₁ to 112Z _n are commonly bundled. It is supplied to a flexible printed circuit film connected to the two-electrode driver. In this case, since the common voltage is supplied to the common electrode line 142, only three flexible printed circuit films may apply sufficient potential. Since the second electrode pad part 144 is formed in the center area of the panel, current generated in the second electrode lines formed at both ends of the panel is generated by the first pad part 144a and the second electrode pad part 144. Some pad lines of the third pad portion 144c are concentrated. In order to prevent such current concentration, a plurality of current paths are formed by removing a part of the common electrode line 142 connected to the second electrode lines formed at both ends of the panel. At this time, a part of the common electrode line is removed in a quadrangular shape or a part of a trapezoidal shape to have a plurality of current paths.

In other words, as illustrated in FIG. 5A, the plurality of second electrode lines formed at the upper end of the panel are connected to the common electrode lines 142 having the plurality of current paths, so that current flows to the first pad part 144a. Supplied. Accordingly, current may be distributed by a plurality of current paths, thereby preventing concentration of current on some pad lines of the first pad part 144a. Similarly, as shown in FIG. 5B, the plurality of second electrode lines formed at the lower end of the panel are connected to the common electrode lines 142 having the plurality of current paths, so that current flows to the third pad portion 144c. Supplied. Therefore, current may be distributed by a plurality of current paths, thereby preventing concentration of current on some pad lines of the third pad part 144c. At this time, the plurality of current paths are connected to the common electrode line 142 from the upper end of the panel to the upper side of the first pad portion 144a and the lower end of the panel to the lower side of the third pad portion 144c. In addition to the same length is formed. In addition, not only two or more paths formed in the common electrode line 142 may be set differently from each other.

The lower dielectric layer and the partition wall (not shown) are formed on the lower substrate on which the address electrode is formed, and phosphors are coated on the surfaces of the lower dielectric layer and the partition wall. The address electrode is formed in a direction crossing the first electrode 112Y and the second electrode 112Z. The partition wall is formed in parallel with the address electrode to prevent the ultraviolet rays and the visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne for discharging is injected into the gas discharge space provided between the upper and lower substrates and the partition wall.

6 is a diagram illustrating a plasma display panel according to a second embodiment of the present invention.

Referring to FIG. 6, the plasma display panel according to the second embodiment of the present invention has the same components except that only the structure of the common electrode line is changed compared to the first embodiment of the present invention. Therefore, the same reference numerals are given to the same components as in the first embodiment, and detailed descriptions of the respective components except for the common electrode line will be omitted below.

Meanwhile, in the second embodiment of the present invention, the common electrode line (to prevent the current generated from the second electrode lines formed at both ends of the panel from being concentrated on some pad lines of the second electrode pad part 144). The area of each current path formed in 142 is set differently.

In detail, when the voltage is supplied to the first electrode lines 112Y ₁ to 112Y _n and the common voltage is supplied to the second electrode lines 112Z ₁ to 112Z _n , the first electrode 112Y and the second electrode are provided. Discharge is generated between the electrodes 112Z. The discharge current generated by the discharge between the two electrodes is not shown through the second electrode pad part 44 via the common electrode line 142 _where the second electrode lines 112Z ₁ to 112Z _n are commonly bundled. It is supplied to a flexible printed circuit film connected to the two-electrode driver. In this case, since the common voltage is supplied to the common electrode line 142, only three flexible printed circuit films may apply sufficient potential. Since the second electrode pad part 144 is formed in the center area of the panel, current generated in the second electrode lines formed at both ends of the panel is generated by the first pad part 144a and the second electrode pad part 144. Some pad lines of the third pad portion 144c are concentrated. In order to prevent such current concentration, a part of the common electrode line 142 is removed to set different areas of current paths formed in the common electrode line 142 connected to the second electrode lines formed at both ends of the panel. do. In this case, a part of the common electrode line 142 is removed in a quadrangular form or a part is removed in a trapezoidal form. The removed parts have different lengths. Accordingly, the common electrode line 142 may include a first portion 142c having at least one current path, a second portion 142b having at least two current paths, and a third portion having at least three current paths. Divided by 142a.

In other words, as shown in FIG. 7A, the plurality of second electrode lines formed at the upper end of the panel are connected to the common electrode lines 142 having different numbers of current paths formed therebetween, and are connected to each other. Is supplied to the first pad portion 144a. That is, current is distributed by the third portion 142a having at least three current paths so that heat is dispersed, and current is dispersed by the second portion 142b having at least two current paths, thereby dissipating heat. Similarly, as illustrated in FIG. 7B, the plurality of second electrode lines formed at the lower end of the panel are connected to and distributed with the common electrode lines 142 having different areas and having different numbers of current paths. The supplied current is supplied to the third pad portion 144c.

As described above, the plasma display panel according to the embodiment of the present invention forms a plurality of paths in the common electrode line to which the plurality of sustain electrode lines are connected. The current is distributed by the plurality of passes to prevent concentration of current on some pad lines of the electrode pads connected to the common electrode line.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell of a conventional plasma display panel.

FIG. 2 is a plan view illustrating pad electrode portions connected to first and second electrodes shown in FIG. 1; FIG.

3A and 3B are detailed views of upper and lower second electrode pad portions of the plasma display panel illustrated in FIG. 2;

4 illustrates a plasma display panel according to a first embodiment of the present invention.

5A and 5B are diagrams showing in detail a first pad portion and a third pad portion of the plasma display panel shown in FIG. 4;

6 illustrates a plasma display panel according to a second embodiment of the present invention.

7A and 7B are diagrams illustrating in detail a first pad part and a third pad part of the plasma display panel shown in FIG. 6;

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 112Y: first electrode

12Z, 112Z: Second electrode 14,22: Dielectric layer

16: protective film 18: lower substrate

20X: address electrode 24: partition wall

26: phosphor layer 32,132: link portion

34,134: first electrode pad portion 42,142: common electrode line

44,144: second electrode pad portion 44a, 44b, 44c, 144a, 144b, 144c: pad portion

Claims (12)

A first electrode and a second electrode formed parallel to each other on the upper substrate; A common electrode line formed at one edge of the upper substrate and commonly connected to any one of the first and second electrodes and partially removed to have a plurality of current paths; And a plurality of pad parts formed on one side of the common electrode line to supply a common voltage from the outside to any one of the first and second electrodes connected to the common electrode line. . The method of claim 1, At least two current paths are formed. The method of claim 1, And each of the plurality of current paths has a different area. The method of claim 1, And each of the plurality of current paths has the same area. The method of claim 1, And the common electrode line is partially removed in a quadrangular shape so as to have a plurality of current paths. The method of claim 1, The common electrode line is a plasma display panel, characterized in that part is removed in a trapezoidal shape to have a plurality of current paths. The method according to claim 5 or 6, And the removed portion is removed in the same length. The method according to claim 5 or 6, And the removed portions are removed in different lengths. The method of claim 8, The common electrode line is divided into a first portion having at least three current paths, a second portion having at least two current paths, and a third portion having at least one current path. The method of claim 9, And an area of each of the current paths of the first portion, the second portion, and the third portion is set to be different from each other. The method of claim 10, And the area of the third partial current path is wider than the area of the second partial current path. The method of claim 11, And the area of the second partial current path is wider than the area of the first partial current path.