KR20050022437A - Method for manufacturing a shallow trench isolation layer of the semiconductor device - Google Patents
Method for manufacturing a shallow trench isolation layer of the semiconductor device Download PDFInfo
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- KR20050022437A KR20050022437A KR1020030060637A KR20030060637A KR20050022437A KR 20050022437 A KR20050022437 A KR 20050022437A KR 1020030060637 A KR1020030060637 A KR 1020030060637A KR 20030060637 A KR20030060637 A KR 20030060637A KR 20050022437 A KR20050022437 A KR 20050022437A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 반도체 소자에서 소자간 분리를 위한 셀로우 트렌치 소자분리(STI : Shallow Trench Isolation)막 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a shallow trench isolation (STI) film for separation between devices in a semiconductor device.
반도체 소자의 제조기술이 발달됨에 따라 반도체 소자의 집적도또한 증가하여 반도체 소자의 미세화가 진행되고 있다. 반도체 소자의 미세화 기술에 있어서, 소자를 집적화하기 위하여 소자 사이를 분리하는 소자분리막의 축소 기술이 중요한 항목중의 하나로 대두되었다.As the manufacturing technology of the semiconductor device is developed, the degree of integration of the semiconductor device is also increased, and thus, the semiconductor device is being miniaturized. In the technology of miniaturization of semiconductor devices, in order to integrate devices, a technology of reducing a device isolation film that separates devices has emerged as one of the important items.
종래의 소자분리기술로는 반도체기판상에 두꺼운 산화막을 선택적으로 성장시켜 소자분리막을 형성하는 로커스(LOCOS : LOCal Oxidation of Silicon) 기술이 있다. 로커스 소자분리막은 산화막 성장시 기판 측면으로 성장되기 때문에 소자분리막의 폭을 감소시키는데 한계가 있었다. 따라서 고집적 반도체 소자에서는 LOCOS 소자분리막보다는 소자분리막 폭을 줄일 수 있는 셀로우 트렌치 소자분리막(STI)이 주로 사용되고 있다.Conventional device isolation technology includes a LOCOS (LOCal Oxidation of Silicon) technology to selectively grow a thick oxide film on the semiconductor substrate to form a device isolation film. Since the locus device isolation layer is grown to the side of the substrate when the oxide film is grown, there is a limit to reducing the width of the device isolation layer. Therefore, in the highly integrated semiconductor device, a shallow trench device isolation film (STI) capable of reducing the width of the device isolation film rather than the LOCOS device isolation film is mainly used.
도 1은 종래 기술에 의한 반도체 소자의 셀로우 트렌치 소자분리막 제조 방법을 나타낸 흐름도이다. 도 2a 내지 도 2e는 종래 기술에 의한 셀로우 트렌치 소자분리막의 제조 공정을 나타낸 공정 순서도이다. 이들 도면들을 참조하면 종래 기술의 셀로우 트렌치 소자분리막 제조 공정은 다음과 같다.1 is a flowchart illustrating a method for manufacturing a shallow trench isolation layer of a semiconductor device according to the related art. 2A to 2E are process flowcharts illustrating a manufacturing process of a shallow trench isolation layer according to the prior art. Referring to these drawings, the conventional trench trench isolation layer manufacturing process is as follows.
우선 도 2a에 도시된 바와 같이, 반도체 기판으로서 실리콘 기판(10)을 열산화하여 패드(pad) 절연막(12)으로서 실리콘 산화막(SiO2)을 100Å∼200Å 성장시키고 그 위에 하드 마스크(hard mask)막(14)으로서 실리콘 질화막(Si3N4)을 1500Å∼2000Å 증착한다. 그리고 도면에 도시하지는 않았지만, 셀로우 트렌치 소자분리막의 마스크 패턴을 이용한 사진 및 식각 공정을 진행하여 하드 마스크막(14) 및 패드 절연막(12)을 패터닝하여 반도체 소자의 소자분리 영역(isolation region)이 되는 기판을 오픈시킨다. 그 다음 건식 식각 (dry etch)공정으로 기판(10)을 소정 깊이, 예컨대 3000Å∼5000Å로 식각하여 셀로우 트렌치 소자분리막이 형성될 부위인 트렌치(16)를 형성한다.(S10)First, as shown in FIG. 2A, the silicon substrate 10 is thermally oxidized as a semiconductor substrate, thereby growing a silicon oxide film SiO 2 as a pad insulating film 12 to 200 占 Å and a hard mask film thereon. As (14), a silicon nitride film (Si3N4) is deposited at 1500 kPa to 2000 kPa. Although not shown in the drawing, the hard mask layer 14 and the pad insulating layer 12 are patterned by performing a photolithography and an etching process using a mask pattern of the shallow trench isolation layer to form an isolation region of the semiconductor device. The substrate to be opened. Subsequently, the substrate 10 is etched to a predetermined depth, for example, 3000 Å to 5000 Å by a dry etch process to form the trench 16, which is a portion where the shallow trench isolation layer is to be formed (S10).
계속해서 도 2b에 도시된 바와 같이, 트렌치 내측면에 라이너 절연막(linear dielectric layer)(18)을 형성한다.(S12) 이때 라이너 절연막(18)은 열산화(thermal oxidation) 공정으로 형성된 실리콘 산화막(SiO2)이다. 라이너 절연막(18)의 두께는 250Å∼350Å정도이다. Subsequently, as shown in FIG. 2B, a linear dielectric layer 18 is formed on the inner side of the trench. (S12) The liner insulating layer 18 is formed of a silicon oxide film formed by a thermal oxidation process. SiO2). The thickness of the liner insulating film 18 is about 250 GPa-350 GPa.
그 다음 도 2c에 도시된 바와 같이, 상기 결과물의 트렌치(16)가 매립되도록 갭필 절연막(20)으로서 실리콘산화막(SiO2) 또는 TEOS(tetraetylorthosilicate)를 증착한다.(S14) 이때 갭필 절연막(20)은 HDP(High Density Plasma) 증착, PE-CVD(Plasma Enhanced Chemical Vapor Deposition) 증착, AP-CVD(Atmospheric Pressure Chemical Vapor Deposition) 증착 등으로 형성한다.Next, as shown in FIG. 2C, a silicon oxide film (SiO 2) or a TEOS (tetraetylorthosilicate) is deposited as the gap fill insulating film 20 so that the trench 16 of the resultant material is embedded (S14). It is formed by HDP (High Density Plasma) deposition, PE-CVD (Plasma Enhanced Chemical Vapor Deposition) deposition, AP-CVD (Atmospheric Pressure Chemical Vapor Deposition) deposition.
그리고 도면에 도시되지 않았지만, 갭필 절연막(20)의 불순물을 제거하기 위하여 세정 공정을 진행한다.(S16) 이때 세정 공정은 인산(H3PO4) 또는 불산(HF) 등이 포함된 습식 세정 용액을 사용하여 진행한다.Although not shown in the drawings, a cleaning process is performed to remove impurities from the gapfill insulating film 20 (S16). The cleaning process uses a wet cleaning solution containing phosphoric acid (H 3 PO 4) or hydrofluoric acid (HF). Proceed.
그런 다음 도 2d에 도시된 바와 같이, 갭필 절연막(20)의 밀도를 높이기 위하여 어닐링 공정을 진행한다.(S18)Then, as shown in FIG. 2D, an annealing process is performed to increase the density of the gap fill insulating film 20 (S18).
그리고나서 도 2e에 도시된 바와 같이, 하드 마스크(14)막 패턴이 드러날 때까지 갭필 절연막(20)을 화학적기계적연마(CMP : Chemical Mechanical Polishing)로 식각하여 그 표면을 평탄화(20a)한 후에 세정 공정을 진행한다.(S20∼S22) 이후 도면에 도시되지 않았지만, 인산 용액 등으로 하드 마스크(14)막 패턴을 제거하고 패드 절연막(12) 패턴을 제거하여 셀로우 트렌치 소자분리막을 완성한다.Then, as shown in FIG. 2E, the gap fill insulating film 20 is etched by chemical mechanical polishing (CMP) until the hard mask 14 film pattern is exposed, and then the surface thereof is flattened (20a) and cleaned. (S20 to S22) Subsequently, although not shown in the drawing, the shallow trench isolation layer is completed by removing the hard mask 14 film pattern with a phosphoric acid solution or the like and removing the pad insulating film 12 pattern.
그런데 이와 같은 종래 기술에 의한 셀로우 트렌치 소자분리막의 제조 공정시 라이너 절연막(18)을 형성한 후에 갭필 절연막(20)을 진행하지 않고 바로 갭필 절연막 다음의 세정 공정을 진행하게 된다면 라이너 절연막(18) 두께가 줄어들뿐만 아니라 하드 마스크막(14) 패턴이 측면이 식각되어 원하는 셀로우 트렌치 소자분리막을 얻을 수 없었다. 그러므로, 이러한 반도체 기판은 불량으로 판정되어 더 이상의 셀로우 트렌치 소자분리막 제조 공정을 진행하지 않고 불량처리하였다.However, when the liner insulating layer 18 is formed in the manufacturing process of the trench trench isolation layer according to the related art, the liner insulating layer 18 may be cleaned immediately after the gap fill insulating layer 20 without performing the gap fill insulating layer 20. Not only was the thickness reduced, but the hard mask layer 14 pattern was etched on the side, so that the desired shallow trench isolation layer could not be obtained. Therefore, such a semiconductor substrate was judged to be defective and was defectively processed without further proceeding with the shallow trench element isolation film manufacturing process.
본 발명의 목적은 라이너 절연막을 형성한 후에 바로 갭필 절연막 이후의 세정 공정을 진행할 경우 불량처리하지 않고 그대로 라이너 절연막의 두께를 보상하는 라이너 절연막의 추가 증착 공정을 진행한 후에 갭필 절연막 증착 공정을 진행함으로써 불량 기판을 재사용하여 반도체 기판의 불량률을 줄일 수 있는 반도체 소자의 셀로우 트렌치 소자분리막 제조 방법을 제공하는데 있다.An object of the present invention is to proceed with the gap-fill insulating film deposition process after the additional deposition process of the liner insulating film to compensate for the thickness of the liner insulating film as it is without a bad treatment when the cleaning process after the gap-fill insulating film immediately after forming the liner insulating film The present invention provides a method of manufacturing a cell trench trench isolation film for a semiconductor device capable of reducing a defect rate of a semiconductor substrate by reusing a defective substrate.
상기 목적을 달성하기 위하여 본 발명은 반도체 소자 분리를 위한 셀로우 트렌치 소자분리막을 형성하는 방법에 있어서, 반도체 기판 상부에 패드 절연막과 하드 마스크막을 순차적으로 적층하고 이들을 패터닝하는 단계와, 하드 마스크막 및 패드 절연막 패턴에 의해 드러난 반도체 기판을 소정 깊이로 식각하여 트렌치를 형성하는 단계와, 트렌치 내측면의 기판에 라이너 절연막을 형성하는 단계와, 라이너 절연막이 형성된 결과물에 세정 공정을 실시하여 하드 마스크막 및 패드 절연막 패턴의 높이 및 측면을 축소시킴과 동시에 라이너 절연막의 두께를 줄이는 단계와, 트렌치 내측면의 라이너 절연막을 설정된 두께로 보상하는 단계와, 트렌치가 완전히 매립되도록 갭필 절연막을 형성한 후에 세정 공정을 진행하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method of forming a shallow trench isolation layer for semiconductor device isolation, comprising: sequentially depositing and patterning a pad insulating film and a hard mask film on a semiconductor substrate; Etching the semiconductor substrate exposed by the pad insulating film pattern to a predetermined depth to form a trench; forming a liner insulating film on the substrate on the inner side of the trench; Reducing the thickness of the pad insulating film and reducing the thickness of the liner insulating film, compensating the liner insulating film on the inner side of the trench to a predetermined thickness, and forming a gap fill insulating film so that the trench is completely filled. Including the step of proceeding.
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 3은 본 발명에 따른 반도체 소자의 셀로우 트렌치 소자분리막 제조 방법을 나타낸 흐름도이고, 도 4a 내지 도 4g는 본 발명에 따른 셀로우 트렌치 소자분리막의 제조 공정을 나타낸 공정 순서도이다. 이들 도면들을 참조하면, 본 발명의 셀로우 트렌치 소자분리막의 제조 공정은 다음과 같다.3 is a flowchart illustrating a method of manufacturing a shallow trench isolation layer of a semiconductor device according to the present invention, and FIGS. 4A to 4G are flowcharts illustrating a process of manufacturing a shallow trench isolation layer according to the present invention. Referring to these drawings, the manufacturing process of the cell trench trench isolation film of the present invention is as follows.
우선 도 4a에 도시된 바와 같이, 반도체 기판으로서 실리콘 기판(100)을 열산화하여 패드 절연막(102)으로서 실리콘 산화막(SiO2)을 100Å∼200Å 성장시키고 그 위에 하드 마스크막(104)으로서 실리콘 질화막(Si3N4)을 1500Å∼2000Å 증착한다. 그리고 도면에 도시하지는 않았지만, 셀로우 트렌치 소자분리막의 마스크 패턴을 이용한 사진 및 식각 공정을 진행하여 하드 마스크막(104) 및 패드 절연막(102)을 패터닝하여 반도체 소자의 소자분리 영역이 되는 기판을 오픈시킨다. 그 다음 건식 식각 공정으로 기판(100)을 소정 깊이, 예컨대 3000Å∼5000Å로 식각하여 셀로우 트렌치 소자분리막이 형성될 부위인 트렌치(106)를 형성한다.(S100)First, as shown in FIG. 4A, the silicon substrate 100 is thermally oxidized as a semiconductor substrate to grow a silicon oxide film SiO 2 as a pad insulating film 102, and a silicon nitride film as a hard mask film 104 thereon. Si 3 N 4) is deposited from 1500 kPa to 2000 kPa. Although not shown in the drawings, a hard mask film 104 and a pad insulating film 102 are patterned by using a photo pattern and an etching process using a mask pattern of a shallow trench device isolation film to open a substrate to be a device isolation region of a semiconductor device. Let's do it. Subsequently, the substrate 100 is etched to a predetermined depth, for example, 3000 m to 5000 m by a dry etching process to form the trench 106, which is a portion where the shallow trench isolation layer is to be formed (S100).
계속해서 도 4b에 도시된 바와 같이, 트렌치 내측면에 라이너 절연막(108)을 형성한다.(S102) 이때 라이너 절연막(108)은 열산화 공정으로 형성된 실리콘 산화막(SiO2)이다.Subsequently, as shown in FIG. 4B, a liner insulating film 108 is formed on the inner side of the trench (S102). The liner insulating film 108 is a silicon oxide film SiO2 formed by a thermal oxidation process.
트렌치 내측면에 라이너 절연막(108)을 형성한 후에, 갭필 절연막을 진행하지 않고 바로 갭필 절연막 다음의 인산(H3PO4) 또는 불산(HF) 등을 사용한 습식 세정 공정(S104)을 진행하게 된다면 도 4c와 같이 하드 마스크막(104) 및 패드 절연막(102) 패턴의 높이 및 측면이 습식 세정 용액에 의해 축소됨과 더불어 라이너 절연막(108)의 두께또한 줄어든다. 여기서 축소된 하드 마스크막은 104a로 두께가 줄어든 라이너 절연막은 108a로 표시한다.After the liner insulating film 108 is formed on the inner side of the trench, a wet cleaning process (S104) using phosphoric acid (H 3 PO 4) or hydrofluoric acid (HF) immediately after the gap fill insulating film is performed without performing the gap fill insulating film. Likewise, the height and side surfaces of the hard mask film 104 and the pad insulating film 102 are reduced by the wet cleaning solution, and the thickness of the liner insulating film 108 is also reduced. Here, the reduced hard mask film is 104a and the thickness of the liner insulating film is reduced to 108a.
이와 같이 갭필 절연막이후의 세정 공정에 의해 식각된 하드 마스크막(104a) 및 패드 절연막(102)과 함께 두께가 줄어든 라이너 절연막(108a)은 종래 기술에서 불량처리되었다. 하지만 본 발명은 이러한 불량처리된 기판을 폐기처리하지 않고 재사용한다.As described above, the liner insulating film 108a having a reduced thickness along with the hard mask film 104a and the pad insulating film 102 etched by the cleaning process after the gap fill insulating film has been poorly treated in the prior art. However, the present invention reuses such defective substrates without discarding them.
이에 도 4d에 도시된 바와 같이, 상기 세정 공정에 의해 식각된 하드 마스크막(104a)은 그대로 두고 두께가 줄어든 라이너 절연막(108a)을 설정된 두께로 보상한다.(S106) 여기서, 라이너 절연막(108a)의 보상하는 방법은 반응로에서 시간이 오래걸리는 열산화 공정보다는 시간이 빠른 O2 플라즈마 증착 공정으로 라이너 절연막을 설정된 두께가 될 때까지 추가 증착(110)한다. 예를 들어, 디자인룰에 따른 라이너 절연막의 두께가 100Å이며 잘못된 세정 공정에 의해 식각 손상된 라이너 절연막의 두께가 40Å이라면 O2 플라즈마 증착 공정으로 60Å의 라이너 절연막(110)을 추가 증착한다. As shown in FIG. 4D, the hard mask film 104a etched by the cleaning process is left as it is and the liner insulating film 108a whose thickness is reduced is compensated to the set thickness (S106). Here, the liner insulating film 108a is provided. Compensation method of the additional deposition 110 to the thickness of the liner insulating film by a faster O2 plasma deposition process than the time-consuming thermal oxidation process in the reactor until the set thickness. For example, if the thickness of the liner insulating film according to the design rule is 100 mm and the thickness of the liner insulating film etched by the wrong cleaning process is 40 mm, the 60 nm liner insulating film 110 is additionally deposited by the O2 plasma deposition process.
한편 본 발명은 갭필 절연막이후의 세정 공정에 의해 하드 마스크막(104a) 및 패드 절연막(102)의 높이 및 측면이 식각되기 때문에 트렌치 입구의 오픈 폭이 커지게 된다. 따라서 본 발명의 라이너 절연막(108a)의 추가 증착 공정시 트렌치 상부 모서리가 라운딩하게 되는 효과를 얻을 수 있다.In the present invention, since the height and side surfaces of the hard mask film 104a and the pad insulating film 102 are etched by the cleaning process after the gap fill insulating film, the opening width of the trench inlet is increased. Therefore, the upper edge of the trench may be rounded during the additional deposition process of the liner insulating layer 108a of the present invention.
그 다음 도 4e에 도시된 바와 같이 결과물의 트렌치가 완전히 매립되도록 갭필 절연막(112)으로서 실리콘산화막(SiO2) 또는 TEOS를 증착한다.(S108) 이때 갭필 절연막(112)은 HDP 증착, PE-CVD 증착, AP-CVD 증착 등으로 형성한다.Then, as illustrated in FIG. 4E, a silicon oxide film (SiO 2) or TEOS is deposited as the gap fill insulating film 112 so that the resulting trench is completely filled. (S108) At this time, the gap fill insulating film 112 is HDP deposited or PE-CVD deposited. And AP-CVD deposition.
그리고 도면에 도시되지 않았지만, 갭필 절연막(112)의 불순물을 제거하기 위하여 인산(H3PO4) 또는 불산(HF) 등이 포함된 습식 세정 용액을 사용한 세정 공정을 진행한다.(S110)Although not shown in the figure, a cleaning process using a wet cleaning solution containing phosphoric acid (H 3 PO 4), hydrofluoric acid (HF), or the like is performed to remove impurities from the gapfill insulating film 112 (S110).
그런 다음 도 4f에 도시된 바와 같이, 갭필 절연막(112)의 밀도를 높이기 위하여 어닐링 공정을 진행한다.(S112)Then, as shown in FIG. 4F, an annealing process is performed to increase the density of the gap fill insulating film 112 (S112).
그리고나서 도 4g에 도시된 바와 같이, 하드 마스크(104a)막 패턴이 드러날 때까지 갭필 절연막(112)을 화학적기계적연마(CMP)로 식각하여 그 표면을 평탄화(112a)한 후에 세정 공정을 진행한다.(S114∼S116) 이후 도면에 도시되지 않았지만, 인산 용액 등으로 하드 마스크(104a)막 패턴을 제거하고 패드 절연막(102) 패턴을 제거하여 셀로우 트렌치 소자분리막을 완성한다.Then, as illustrated in FIG. 4G, the gap fill insulating film 112 is etched by chemical mechanical polishing (CMP) until the hard mask 104a film pattern is exposed, and then the surface thereof is flattened 112a and then the cleaning process is performed. Although not shown in the drawings after (S114 to S116), the shallow trench isolation layer is completed by removing the hard mask 104a film pattern with a phosphoric acid solution or the like and removing the pad insulating film 102 pattern.
이상 상술한 바와 같이, 본 발명은 라이너 절연막을 형성한 후에 바로 갭필 절연막 이후의 세정 공정을 진행할 경우 불량처리하지 않고 그대로 라이너 절연막의 두께를 보상하고자 라이너 절연막의 추가 증착 공정을 진행한 후에 갭필 절연막 증착 공정을 진행함으로써 불량 기판을 재사용하여 반도체 기판의 불량률을 줄일 수 있는 효과가 있다.As described above, in the present invention, when the cleaning process after the gap fill insulating film is performed immediately after the liner insulating film is formed, the gap fill insulating film is deposited after the additional deposition process of the liner insulating film is performed to compensate for the thickness of the liner insulating film as it is without defect treatment. By proceeding the process it is possible to reuse the defective substrate to reduce the defect rate of the semiconductor substrate.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
도 1은 종래 기술에 의한 반도체 소자의 셀로우 트렌치 소자분리막 제조 방법을 나타낸 흐름도,1 is a flowchart illustrating a method of manufacturing a cell trench trench isolation film of a semiconductor device according to the prior art;
도 2a 내지 도 2e는 종래 기술에 의한 셀로우 트렌치 소자분리막의 제조 공정을 나타낸 공정 순서도,2a to 2e is a process flowchart showing a manufacturing process of a cell trench trench isolation film according to the prior art,
도 3은 본 발명에 따른 반도체 소자의 셀로우 트렌치 소자분리막 제조 방법을 나타낸 흐름도,3 is a flowchart illustrating a method of manufacturing a shallow trench isolation layer in a semiconductor device according to the present invention;
도 4a 내지 도 4g는 본 발명에 따른 셀로우 트렌치 소자분리막의 제조 공정을 나타낸 공정 순서도.Figures 4a to 4g is a process flow chart showing the manufacturing process of the trench trench isolation layer in accordance with the present invention.
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