KR20050015520A - Multi-domain liquid crystal display including the same - Google Patents

Abstract

PURPOSE: A multi-domain LCD(Liquid Crystal Display) is provided to improve the response speed of liquid crystal molecules while securing total transmissivity of the LCD by optimizing the interval and width of domain controllers. CONSTITUTION: A multi-domain LCD includes the first insulating substrate, the first signal line(131) formed on the first insulating substrate, the second signal line(171) formed on the first insulating substrate to intersect the first signal line, a pixel electrode(190) formed in a pixel region disposed at the intersection of the first and second signal lines, and a thin film transistor connected to the first signal line, the second signal line and the pixel electrode. The multi-domain LCD further includes the second insulating substrate opposite to the first insulating substrate, a common electrode formed on the second insulating substrate, a liquid crystal layer formed between the first and second insulating substrates, and a plurality of domain controllers(191,192,193) that are formed on at least one of the first and second insulating substrates and split liquid crystal molecules of the liquid crystal layer into a plurality of domains in the pixel region. The domain controllers are arranged at an interval of 12 to 20 micrometer.

Description

Multi-domain liquid crystal display {MULTI-DOMAIN LIQUID CRYSTAL DISPLAY INCLUDING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a thin film transistor array panel having a vertical alignment mode for dividing a pixel into a plurality of domains to obtain a wide viewing angle, and a liquid crystal display including the same.

In general, a liquid crystal display device injects a liquid crystal material between an upper substrate on which a common electrode, a color filter, and the like are formed, and a lower substrate on which a thin film transistor and a pixel electrode are formed. By applying a different potential to form an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance is a device that represents the image.

However, it is an important disadvantage that the liquid crystal display device has a narrow viewing angle. In order to overcome these disadvantages, various methods for widening the viewing angle have been developed. Among them, the liquid crystal molecules are oriented vertically with respect to the upper and lower substrates, and the pixel is formed by forming a constant incision pattern or protrusion on the pixel electrode and the common electrode as the opposite electrode. The method of partitioning into multiple domains is gaining popularity.

However, a liquid crystal display device having a vertical alignment mode having protrusions and cutout patterns has limitations in reducing the response speed of liquid crystals. One of the causes is that when the driving voltage is applied, the liquid crystal molecules arranged adjacent to the incision pattern, which is the edge of the domain, are rearranged quickly by the orientation field determined by the fringe field, but arranged in the center of the domain. The responsiveness of the liquid crystal molecules is slowed down because the reorientation is determined by the collision or collision caused by the arrangement of the liquid crystal molecules arranged outside the domain. In order to solve this problem, the incision patterns may be arranged at narrow intervals, but the aperture ratio of the pixel is lowered, which causes a decrease in the light transmittance.

Another object of the present invention is to provide a display panel capable of improving the response speed of a liquid crystal of a liquid crystal molecule while securing a transmittance of a pixel, and a liquid crystal display including the same.

In order to solve this problem, in the present invention, the interval between the domain regulating means is arranged in the range of 12-20 µm.

The liquid crystal display according to the exemplary embodiment of the present invention may include a first insulating substrate, a first signal line formed on the first insulating substrate, a second signal line formed on the first insulating substrate, and insulated from and intersecting the first signal line; A pixel electrode formed for each pixel defined by crossing the first signal line and the second signal line, a thin film transistor connected to the first signal line, the second signal line, and the pixel electrode, a second insulating substrate facing the first insulating substrate, The liquid crystal molecules of the liquid crystal layer formed on at least one side of the common electrode formed on the second insulating substrate, the liquid crystal layer formed between the first insulating substrate and the second insulating substrate, and the first insulating substrate and the second insulating substrate. And a plurality of domain regulating means for dividing a into a plurality of domains in a pixel. At this time, a plurality of domain regulating means are arranged at intervals ranging from 12 μm to 20 μm.

It is preferable that the liquid crystal contained in the liquid crystal layer has negative dielectric anisotropy and the long axis of the liquid crystal is vertically aligned with respect to the first and second substrates.

The domain regulating means may be an incision that the common electrode or the pixel electrode has, and the width of the domain regulating means is preferably in the range of 9 µm to 12 µm.

The domain regulating means of the common electrode has an end portion which partially overlaps the boundary of the pixel electrode, and the distance between the boundary of the pixel electrode and the boundary of the end of the common electrode covering the pixel electrode is preferably 8 µm or more.

At this time, the negative dielectric anisotropy of the liquid crystal layer is in the range of -3.5 to -3.8, and the rotational viscosity of the liquid crystal layer is preferably 120 mPa's or less.

It is preferable that the domain regulating means is substantially ± 45 degrees with respect to the first signal line, and the domain regulating means is substantially mirror-symmetrical with respect to the upper and lower bisectors of the pixel.

The domain regulating means may be a protrusion formed on the common electrode or the pixel electrode.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a multi-domain liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a first embodiment of the present invention, and FIG. 2 illustrates a structure of an opposing display panel for a liquid crystal display according to a first embodiment of the present invention. 3 is a layout view illustrating a structure of a liquid crystal display according to a first exemplary embodiment in which the display panels of FIGS. 1 and 2 of the present invention are aligned with each other, and FIG. 4 illustrates IV-IV of the liquid crystal display of FIG. 3. Is a cross-sectional view taken along a line.

The liquid crystal display device is formed of a liquid crystal molecule that is formed between the thin film transistor array panel 100 on the lower side and the upper opposing display panel 200 facing them, and is substantially perpendicular to the two display panels 100 and 200. It consists of a liquid crystal layer 3 including 310.

The thin film transistor array panel 100 made of a transparent insulating material such as glass is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and includes a pixel electrode having cutouts 191, 192, and 193. 190 is formed, and each pixel electrode 190 is connected to a thin film transistor to receive an image signal voltage. In this case, the thin film transistor is connected to the gate line 121 for transmitting the scan signal and the data line 171 for transmitting the image signal, respectively, to turn on and off the pixel electrode 190 according to the scan signal. . The lower polarizer 12 is attached to the bottom surface of the thin film transistor array panel 100. Here, the pixel electrode 190 may not be made of a transparent material in the case of a reflective liquid crystal display, and in this case, the lower polarizer 12 is also unnecessary.

It is also made of a transparent insulating material such as glass, and the opposite display panel 200 facing the thin film transistor array panel 100 has a black matrix 230 and a red, green, and blue color filter to prevent light leakage generated at the edge of the pixel. The reference electrode 270 is formed of a 240 and a transparent conductive material such as ITO or IZO. The black matrix 230 may be formed not only in the peripheral portion of the pixel area but also in the portion overlapping the cutouts 271, 272, and 273 of the reference electrode 270. This is to prevent light leakage caused by the cutouts 271, 272, and 273.

The liquid crystal display according to the first embodiment will be described in more detail.

In the thin film transistor array panel 100, a plurality of gate lines 121 may be formed on the lower insulating substrate 110 to transfer gate signals. The gate line 121 mainly extends in the horizontal direction, and a part of each gate line 121 forms a plurality of gate electrodes 124. The gate electrode 124 is formed in the form of a protrusion in the gate line 121, and the gate line 121 may have a contact portion for transferring a gate signal from the outside to the gate line 121, but otherwise An end portion of the gate line 121 is connected to an output terminal of the gate driving circuit formed directly on the substrate 110.

The storage electrode wirings are formed on the insulating substrate 110 in the same layer as the gate lines 121. Each storage electrode wiring includes a storage electrode line 131 extending parallel to the gate line 121 at the edge of the pixel region and a plurality of storage electrodes 133a, 133b, 133c, and 133d extending therefrom. . The pair of storage electrodes 133a, 133b, 133c, and 133d extend in the vertical direction and are connected to each other by the vertical electrode 133a and 133b which are connected to each other by the storage electrode line 131 extending in the horizontal direction, and the pixel electrode formed thereafter ( An oblique portion 133c and 133d overlapping the cutouts 191 and 193 of 190 and connecting the vertical portions 133a and 133b.

The gate line 121 and the sustain electrode wirings 131, 133a, 133b, 133c, and 133d are made of metal such as Al, Al alloy, Ag, Ag alloy, Cr, Ti, Ta, Mo, or the like. 4 and 5, the gate line 121 and the sustain electrode wirings 131, 133a, 133b, 133c, and 133d of the present embodiment are formed of a single layer, but have excellent physicochemical properties, such as Cr, Mo, and Ti. It may be made of a double layer including a metal layer, such as Ta, and an Al-based or Ag-based metal layer having a low specific resistance. In addition, the gate line 121 and the sustain electrode wirings 131, 133a, 133b, 133c, and 133d may be made of various metals or conductors.

The gate line 121 and the sustain electrode wirings 131, 133a, 133b, 133c, and 133d are inclined side by side, and the inclination angle with respect to the horizontal plane is preferably 30 to 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or the like is formed on the gate line 121 and the storage electrode wirings 131, 133a, 133b, 133c, and 133d.

A plurality of drain electrodes 175, including a plurality of data lines 171, are formed on the gate insulating layer 140. Each data line 171 extends mainly in a vertical direction and has a source electrode 173 extending from the data line 171 by extending a plurality of branches toward each drain electrode 175. The contact unit 179 located at one end of the data line 171 transfers an image signal from the outside to the data line 171. In addition, a leg metal piece 172 overlapping the gate line 121 is formed on the gate insulating layer 140.

Similar to the gate line 121, the data line 171 and the drain electrode 175 may be made of a material such as chromium and aluminum, and may be formed of a single layer or multiple layers.

Under the data line 171 and the drain electrode 175, a plurality of linear semiconductors 151 that extend mainly vertically along the data line 171 are formed. Each linear semiconductor 151 made of amorphous silicon extends toward each gate electrode 124, the source electrode 173, and the drain electrode 175 to have a channel portion 154.

Between the semiconductor 151, the data line 171, and the drain electrode 175, a plurality of linear ohmic contacts 161 and island-like ohmic contacts 165 for reducing contact resistance therebetween, respectively. Is formed. The ohmic contact 161 is made of amorphous silicon doped with silicide or n-type impurities at a high concentration, and has an ohmic contact 163 extending into a branch, and the island-type ohmic contact 165 has a gate electrode 124. Facing the ohmic contact 163.

On the data line 171 and the drain electrode 175, a-Si: C: O, a-Si formed by plasma enhanced chemical vapor deposition (PECVD), an organic material having excellent planarization characteristics, and photosensitivity. A protective film 180 made of a low dielectric constant insulating material such as: O: F or silicon nitride is formed.

The passivation layer 180 includes a plurality of contact holes 185 and 182 exposing at least a portion of the drain electrode 175 and an end portion 179 of the data line 171, respectively. On the other hand, when the end portion of the gate line 121 also has a contact portion for connecting to an external driving circuit, a plurality of contact holes penetrate the gate insulating layer 140 and the passivation layer 180 to end portions of the gate line 121. Can be exposed.

A plurality of data contact assistants 82 are formed on the passivation layer 180, including a plurality of pixel electrodes 190 having cutouts 191, 192, and 193. The pixel electrode 190 and the data contact auxiliary member 82 are formed using a transparent conductor such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductor having excellent light reflection characteristics such as aluminum (Al). do.

The cutouts 191, 192, and 193 formed in the pixel electrode 190 may be divided into the horizontal cutout 192 formed in the horizontal direction at a position that half-divides the pixel electrode 190. And diagonally cut portions 191 and 193 formed in diagonal directions, respectively, in the upper and lower portions of the upper and lower portions. The cutout 192 penetrates from the right side to the left side of the pixel electrode 190, and the inlet is broadly symmetrically extended. Accordingly, the pixel electrode 190 is substantially mirror-symmetrical with respect to a line (a line parallel to the gate line) that bisects the pixel region defined by the intersection of the gate line 121 and the data line 171, respectively.

At this time, the upper and lower oblique cuts 191 and 193 are perpendicular to each other, in order to evenly distribute the direction of the fringe field in four directions.

In addition, a storage wiring connecting bridge 194 is formed on the same layer as the pixel electrode 190 to connect the storage electrode 133a and the storage electrode line 131 of the pixels adjacent to each other across the gate line 121. The storage wiring connection bridge 194 is in contact with the storage electrode 133a and the storage electrode line 131 through the contact holes 183 and 184 formed over the passivation layer 180 and the gate insulating layer 140. The sustain wiring connection leg 194 overlaps the leg metal pieces 172, and these may be electrically connected to each other. The maintenance wiring connection bridge 194 electrically connects the entire maintenance wiring on the lower substrate 110. This holding wiring can be used to repair the defect of the gate line 121 or the data line 171, if necessary, and the leg metal piece 172 is held with the gate line 121 when irradiating a laser for such repair. It is formed to assist the electrical connection of the wiring connection bridge (194).

In the opposite display panel 200 facing the thin film transistor array panel 100, a black matrix 220 is formed on the upper insulating substrate 210 to prevent light leakage from the pixel edge. The red, green, and blue color filters 230 are formed on the black matrix 220. The planarization layer 250 is formed on the entire surface of the color filter 230, and the reference electrode 270 having the cutouts 271, 272, and 273 is formed thereon. The reference electrode 270 is formed of a transparent conductor such as ITO or indium zinc oxide (IZO).

A pair of cutouts 271, 272, and 273 of the common electrode 270 may form 45 ° with respect to the gate line 121 among the cutouts 191, 192, and 193 of the pixel electrode 190. 193 and alternately arranged in parallel with the diagonal line and an end portion overlapping the side of the pixel electrode 190. At this time, the end is classified into a longitudinal end part and a horizontal end part.

When the thin film transistor substrate and the opposing display panel having the above structure are aligned and combined, and a liquid crystal material is injected and vertically aligned therebetween, a basic structure of the liquid crystal display according to the present invention is provided.

When the thin film transistor array panel 100 and the opposing display panel 200 are aligned, the cutouts 191, 192, and 193 of the pixel electrode 190 and the cutouts 271, 272, and 273 of the reference electrode 270 are formed in the pixel area. Split into multiple domains. These domains are classified into four types according to the average major axis direction of the liquid crystal molecules located therein, and each domain is elongated to have a width and a length.

In this case, the cutouts 191, 192, and 193 of the pixel electrode 190 and the cutouts 271, 272, and 273 of the common electrode 270 act as domain regulating means for dividing and aligning the liquid crystal molecules, and the width ( W5 and W6) are preferably between 9 µm and 12 µm. In the case of forming projections of an inorganic material or an organic material on the upper or lower portion of the pixel electrode 190 and the common electrode 270 instead of the cutouts 271, 272, 273, 191, 192, and 193 as the domain restriction means. It is preferable to make it between 5 micrometers and 10 micrometers.

In addition, the interval W1 between the boundary of the cutouts 191, 192, and 193 of the pixel electrodes 190 disposed alternately with the boundary of the cutouts 271, 272, and 273 of the common electrode 270 adjacent thereto. ) And the boundary W2 between the boundary of the pixel electrode 190 and the boundary of the cutouts 271 and 273 of the common electrode 270 adjacent thereto are in the range of 12 μm to 20 μm, more preferably 17 μm to 19 μm. It is preferable that it is in the micrometer range. At this time, the sides of the pixel electrode 190 parallel to the cutouts 191, 192, and 193 are domain restricting means. By disposing the domain regulating means at such intervals, in the liquid crystal display according to the exemplary embodiment of the present invention, the interval between the cutouts 271, 272, 273, 191, 192, and 193 is narrowed to secure the response speed of the liquid crystal molecules. In this case, although the aperture ratio of the pixel was reduced, the transmittance could be ensured. This will be described in detail later through experimental examples.

In the liquid crystal display according to the exemplary embodiment of the present invention, the liquid crystal material has a negative dielectric anisotropy (Δε) in the range of -3.5 to -4.5, and the rotational viscosity (γ1) of the liquid crystal material is preferably 120 mPa's or less. The refractive index anisotropy Δn ranges from 0.07 to 0.09.

In addition, the cutouts 271, 272, and 273 of the common electrode 270 overlapping the boundary of the pixel electrode 190 and the pixel electrode 190 exposed through the cutouts 271, 272 and 273 of the common electrode 270. It is preferable that the space | intervals W3 and W4 between boundaries of () are at least 8 micrometers or more.

Meanwhile, the TFT panel for a liquid crystal display according to another exemplary embodiment of the present invention may have a structure different from that of FIGS. 1 to 4, and the TFT panel may include red, green, and blue color filters. The feature may alternatively have, and will be described in detail with reference to the drawings.

FIG. 5 is a layout view illustrating a structure of a liquid crystal display according to a second exemplary embodiment of the present invention. FIG. 6 is a cross-sectional view of the liquid crystal display of FIG. 5 taken along the line VI-VI ′, and FIG. 8 is a layout view illustrating a structure of a liquid crystal display according to a third exemplary embodiment, and FIG. 8 is a cross-sectional view of the liquid crystal display of FIG. 7 taken along the line VIII-VIII ′.

As shown in Figs. 5 and 6, the layer structure of the thin film transistor array panel for liquid crystal display according to the present embodiment is generally the same as the layer structure of the thin film transistor array panel for liquid crystal display shown in Fig. 1. That is, the plurality of linear semiconductors including the plurality of gate lines 121 including the plurality of gate electrodes 124 is formed on the substrate 110, and the gate insulating layer 140 and the plurality of protrusions 154 thereon. 151, a plurality of linear ohmic contact members 161 each including a plurality of protrusions 163, and a plurality of island type ohmic contact members 165 are sequentially formed. A plurality of data lines 171 and a drain electrode 175 including a plurality of source electrodes 173 are formed on the ohmic contact member 161 and the gate insulating layer 140, and a passivation layer 180 is formed thereon. . The passivation layer 180 and / or the plurality of contact holes 182 and 185 are formed, and the plurality of pixel electrodes 190 and the plurality of contact assistants 82 are formed on the passivation layer 180.

However, unlike the thin film transistor array panel illustrated in FIGS. 1 to 4, in the thin film transistor array panel according to the present exemplary embodiment, the semiconductor 151 may include the data line 171 and the drain electrode except for the protrusion 154 where the thin film transistor is located. It has substantially the same planar shape as the 175a and 175b and the ohmic contacts 161 and 165 thereunder.

In addition, a part 133b ′ of the sustain electrode 133b extending in the vertical direction protrudes to the cutout 192 of the pixel electrode 190.

The thin film transistor array panel for the present liquid crystal display device forms the data line 171, the drain electrodes 175a, 175b, and 175c and the semiconductor layer 151 by a photolithography process using a single photoresist pattern, and the photoresist pattern is a thin film. The portion corresponding to the channel portion of the transistor has a lower thickness than the portion corresponding to other data lines and drain electrodes. In this case, the photoresist pattern is an etch mask for patterning the semiconductor 151, and the thick portion is used as an etch mask for patterning the data line and the drain electrode. In this manufacturing method, two different thin films may be formed in one photosensitive film pattern to minimize manufacturing costs.

In addition, the gate line 121 having the gate electrode 124 has one end portion 129 having a contact portion for connection with an external circuit, and a passivation layer 180 and a gate insulating layer 140 on the passivation layer 180. A gate contact auxiliary member 81 connected to the end portion 128 of the gate line 121 is formed through the contact hole 181.

As shown in FIGS. 7 and 8, the layer structure of the thin film transistor array panel for liquid crystal display according to the third exemplary embodiment of the present invention is generally the same as the layer structure of the thin film transistor array panel for liquid crystal display shown in FIG. 4. Do.

However, red, green, and blue color filters 230 are sequentially formed in the pixel under the passivation layer 180. The red, green, and blue color filters 230 each have a boundary above the data line 171 and are vertically formed along a pixel column, and neighboring color filters partially overlap each other on the data line 171. The hill can be formed on the data line 171. In this case, the red, green, and blue color filters 230 overlapping each other may have a function of a black matrix that blocks light leaking between neighboring pixel areas. Therefore, only the common electrode 270 may be formed in the opposing display panel for the liquid crystal display according to the present exemplary embodiment, since the black matrix is omitted.

Next, as described above, an experimental example of the present invention will be described in detail.

9 is a table illustrating a change in aperture ratio of pixels according to a width and an interval of a domain regulating means in the liquid crystal display according to the experimental example of the present invention, and FIGS. 10 and 11 are domains in the liquid crystal display according to the experimental example of the present invention. 12 is a table showing response rates for gray levels of liquid crystal molecules with respect to the width and the interval of the regulation means, and FIG. 12 is a table showing the transmittance of pixels with respect to the width and the interval of the domain regulation means in the liquid crystal display according to the experimental example of the present invention. 13 is a graph showing waveforms of textures of pixels versus widths and intervals of domain regulating means in the liquid crystal display according to the experimental example of the present invention.

Here, each of "A", "B", and "C" has a spacing W1 between the boundary of the pixel electrode 190 and the cutout 273 of the common electrode 270 adjacent thereto is 19 μm, 17 μm, 16 Μm, the spacing W2 between the borders of the common electrodes 270 and the cutouts 273 and 193 of the pixel electrode 190 adjacent to each other is 19 μm, 18 μm, and 23 μm, and the incision of the common electrode 270 is performed. The width W5 of the portion 273 is 11 μm, 10 μm, and 11 μm, and the width W6 of the cutout portion 193 of the pixel electrode 190 is each liquid crystal display device designed to be 7 μm.

In this case, the liquid crystal display is in a vertical alignment mode, and the transmittances of the polarizing plates are orthogonal to each other. In most liquid crystal display devices, the polarizing plates are disposed such that the polarization axes are parallel to the gate lines 121 and the data lines 171. As described above, when measuring the waveform of only the texture, the transmission axis of the polarizing plate was disposed so as to be in a diagonal direction with respect to the gate line and the data line. The dielectric anisotropy of the liquid crystal material of the A, B, and C liquid crystal display devices was -3.8, and was driven with a driving voltage ranging from 0.5V to 6V, and displayed bright colors with a driving voltage of 5V to 6V. The dark color is indicated by the driving voltage.

9 is a table showing changes in pixel aperture ratios of A, B, and C liquid crystal display devices when the width and spacing of domain regulating means are changed in the liquid crystal display device according to the experimental example of the present invention. Here, a is W5 in FIG. 3, b is W2 in FIG. 3, b 'is W1 in FIG. 3, and c is W6.

FIG. 10 is a table measuring response speeds of liquid crystal molecules according to various gray levels of the liquid crystal display of FIG. C, and FIG. 11 is a table measuring response speeds of liquid crystal molecules according to various gray levels of the liquid crystal display of FIG. Here, 1, 8, 16, 24, 32, 40, 48, 56, and 64 are gray scales in which response speed is measured among 64 gray scales. 10 and 11, the upper part is a rising time of the liquid crystal molecules and the lower part is a falling time, based on the diagonal direction.

In FIG. 12, K1 is a rotational viscosity of a liquid crystal material, K2 is a cell gap, which is a gap between a thin film transistor array panel and a substitute panel in a liquid crystal display, and primary efficiency is applied to a pixel structure such as a signal line, a pixel electrode, or an insulating film. Is the transmittance by the liquid crystal, such as retardation, drive voltage, or dielectric anisotropy of the liquid crystal, and the tertiary efficiency is the transmittance due to the uniformity of the liquid crystal array. The total transmittance is the product of the primary efficiency, the secondary efficiency and the tertiary efficiency, and the 2 * 3rd efficiency is the product of the secondary efficiency and the tertiary efficiency. As shown in the table, for the liquid crystal display device of B, the transmittance and the like of the liquid crystal display device were measured by varying the rotational viscosity (K1) of the liquid crystal material into two types, 135 mPa's and 110 mPa's. Here, the texture is an area in which the liquid crystal molecules are not sufficiently controlled by the domain dividing means. In this area, light is dark when displaying bright colors, and light leaks when displaying dark colors.

FIG. 13 shows the transmittance of the polarizing plates 12 and 22 attached to the outer surfaces of the two display panels 100 and 200 at 45 ° / 135 ° with respect to the gate line and the data line, thereby measuring the luminance amount due to texture only. It is a graph. Here, the horizontal axis is time, and the vertical axis is a numerical value in terms of luminance due to texture, and 23 μm, 19 μm, and 17/18 μm are defined between the cutouts 273 and 193 or between the cutouts 273 and 193 and the pixel electrode ( The intervals W1 and W2 between the boundaries of 190;

As shown in FIG. 9, the gaps W1 and W2 between the cutouts 273 and 193 or between the cutouts 273 and 193 and the boundary between the pixel electrodes 190 may be narrowed as compared to the liquid crystal display of C. In the liquid crystal display devices A and B, the aperture ratios decreased from 39.5% to 37.7% and 37.86%.

However, as shown in FIGS. 10 and 11, when the gaps W1 and W2 between the cutouts 273 and 193 or between the cutouts 273 and 193 and the boundary of the pixel electrode 190 are narrowed, C Compared with the liquid crystal display of, the liquid crystal display of A has a rise time of about 10% faster in the response speed of the liquid crystal molecules. At this time, the polling time was hardly changed.

In addition, as shown in FIG. 12, the distances W1 and W2 between the cutouts 273 and 193 or between the cutouts 273 and 193 and the boundary between the pixel electrodes 190 are compared with those of the C liquid crystal display device. Even if it narrowed down, although the aperture ratio decreased as shown in FIG. 9 in the liquid crystal display device of A and B, the total transmittance was measured to be 3.77 and 3.80 almost equally. This is shown as the transmittance of text increases. Therefore, as in the embodiment of the present invention, the aperture ratio decreases when the gaps W1 and W2 are narrowed between the cutouts 273 and 193 or between the cutouts 273 and 193 and the boundary between the pixel electrodes 190. It is seen that the region in which the liquid crystal molecules are not preferably controlled decreases to increase the tertiary efficiency, thereby improving the total transmittance. Preferably, the texture generated due to the uncontrolled arrangement of the liquid crystal molecules is a major cause of decreasing tertiary efficiency. As described above, when the gaps W1 and W2 are narrowed between the cutouts 273 and 193 or between the cutouts 273 and 193 and the boundary between the pixel electrodes 190 as described above. It can be seen that the response speed of the liquid crystal molecules is faster, and particularly when the rotational viscosity of the liquid crystal material is 110 mPa's, the polling time of the liquid crystal molecules is significantly faster.

In addition, as shown in FIG. 13, the gaps W1 and W2 between the cutouts 273 and 193 or the boundary between the cutouts 273 and 193 and the pixel electrode 190 were narrowed to 19 μm to 19 μm or more. When it is narrowed to the range of 17 μm, it can be seen that the amount of luminance due to the texture decreases. As a result, when the width W1 and W2 are narrowed, the texture decreases, thereby improving the total transmittance of the liquid crystal display.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

As described above, according to the exemplary embodiment of the present invention, the response speed of the liquid crystal molecules can be improved while ensuring the total transmittance of the liquid crystal display device even when the aperture ratio is reduced by optimizing the spacing and width of the domain regulating means.

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention.

2 is a layout view of a common electrode display panel of the liquid crystal display according to the first exemplary embodiment of the present invention.

3 is a layout view of a liquid crystal display according to a first exemplary embodiment of the present invention;

4 is a cross-sectional view taken along line IV-IV ′ of FIG. 3,

5 is a layout view illustrating a structure of a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 6 is a cross-sectional view of the liquid crystal display of FIG. 5 taken along the line VI-VI ′. FIG.

FIG. 7 is a layout view illustrating a structure of a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view of the liquid crystal display of FIG. 7 taken along the line VIII-VIII ′,

9 is a table showing a change in aperture ratio of a pixel according to a width and an interval of domain regulating means in the liquid crystal display according to the experimental example of the present invention;

10 and 11 are tables showing response rates for gray levels of liquid crystal molecules with respect to the width and the interval of the domain regulating means in the liquid crystal display according to the experimental example of the present invention.

12 is a table showing transmittance of pixels with respect to a width and an interval of a domain regulating means in the liquid crystal display according to the experimental example of the present invention;

FIG. 13 is a graph illustrating waveforms of textures of pixels with respect to widths and intervals of domain regulating means in the liquid crystal display according to the experimental example of the present invention.

Claims (10)

First insulating substrate, A first signal line formed on the first insulating substrate, A second signal line formed on the first insulating substrate and insulated from and intersecting the first signal line; A pixel electrode formed for each pixel defined by the crossing of the first signal line and the second signal line; A thin film transistor connected to the first signal line, the second signal line, and the pixel electrode; A second insulating substrate facing the first insulating substrate, A common electrode formed on the second insulating substrate, A liquid crystal layer formed between the first insulating substrate and the second insulating substrate, A plurality of domain restricting means formed on at least one side of the first insulating substrate and the second insulating substrate and dividing the liquid crystal molecules of the liquid crystal layer into a plurality of domains in the pixel; Including; And a plurality of said domain regulating means are arranged at intervals ranging from 12 mu m to 20 mu m. In claim 1, The liquid crystal contained in the liquid crystal layer has negative dielectric anisotropy and the liquid crystal has a long axis oriented perpendicular to the first and second substrates. In claim 2, The negative dielectric anisotropy of the liquid crystal layer is in the range of -3.5 to -4.8. In claim 2, The rotational viscosity of the liquid crystal layer is 120 mPa's or less liquid crystal display device. In claim 1, And the domain regulating means is a cutout of the common electrode or the pixel electrode. In claim 5, The width of the domain regulating means ranges from 9 μm to 12 μm. In claim 6, The domain regulating means of the common electrode has an end portion partially overlapping the boundary of the pixel electrode, and the distance between the boundary of the pixel electrode and the boundary of the end of the common electrode covering the pixel electrode is 8 μm or more. . In claim 1, And the domain restricting means is substantially ± 45 degrees with respect to the first signal line. In claim 1, And the domain restricting means is substantially mirror-symmetrical with respect to the upper and lower bisectors of the pixel. In claim 1, And the domain regulating means is a protrusion formed on the common electrode or the pixel electrode.