KR20050018520A - Liquid crystal display having multi domain and panel for the same - Google Patents

Abstract

PURPOSE: A multi-domain LCD(Liquid Crystal Display) and a TFT(Thin Film Transistor) substrate used for the LCD are provided to improve visibility and luminance by dividing a pixel electrode into at least two sub-pixel electrodes and applying different voltages to the sub-pixel electrodes. CONSTITUTION: A TFT substrate includes an insulating substrate, the first signal line formed on the insulating substrate, and the second signal line(171) intersecting the first signal line, being insulated from the first signal line. The TFT substrate further includes the first electrode and the second electrode(190b) formed in a pixel region disposed at the intersection of the first and second signal lines, and the third electrode(176) formed in the pixel region and superposed on the second electrode. The TFT substrate also has the first TFT(TFT1) having the first and second terminals connected to the first and second signal lines and the third terminal commonly connected to the first and second electrodes, and the second TFT(TFT2) having the first and second terminals respectively connected to the first signal line and the first electrode and the third terminal connected to the third electrode.

Description

Multi-domain liquid crystal display and display panel used therefor {LIQUID CRYSTAL DISPLAY HAVING MULTI DOMAIN AND PANEL FOR THE SAME}

The present invention relates to a liquid crystal display device and a display panel used therefor.

In general, a liquid crystal display device injects a liquid crystal material between an upper display panel on which a common electrode, a color filter, and the like are formed, and a lower display panel on which a thin film transistor and a pixel electrode are formed. By applying a different voltage to form an electric field to change the arrangement of the liquid crystal molecules, and through this to adjust the transmittance of light to represent the image.

However, it is an important disadvantage that the liquid crystal display device has a narrow viewing angle. In order to overcome these disadvantages, various methods for widening the viewing angle have been developed. Among them, liquid crystal molecules are oriented vertically with respect to the upper and lower display panels, and a method of forming a constant incision pattern or forming protrusions on the pixel electrode and the common electrode that is opposite thereto. This is becoming potent.

As a method of forming an incision pattern, an incision pattern is formed on each of the pixel electrode and the common electrode, and the viewing angle is widened by adjusting the direction in which the liquid crystal molecules lie down using a fringe field formed by the incision patterns. .

The protrusions are formed by forming protrusions on the pixel electrode and the common electrode formed on the upper and lower display panels, respectively, to adjust the lying direction of the liquid crystal molecules using an electric field distorted by the protrusions.

In another method, an incision pattern is formed on the pixel electrode formed on the lower panel, and protrusions are formed on the common electrode formed on the upper panel, so that the liquid crystal lies down using a fringe field formed by the incision pattern and the protrusion. There is a way to form a domain by controlling.

In such a multi-domain liquid crystal display, the gray scale inversion reference viewing angle defined as a contrast ratio reference viewing angle based on a contrast ratio of 1:10 or a limit angle of luminance inversion between gray scales is excellent, more than 80 ° in all directions. However, the gamma curve of the front side and the gamma curve of the side do not coincide with each other, resulting in inferior visibility in the left and right sides compared to the TN (twisted nematic) mode liquid crystal display. For example, in the patterned vertically aligned (PVA) mode, which makes an incision by domain dividing means, the screen looks brighter and the color tends to shift toward white as the side faces. Occasionally, the picture appears clumped and disappears. However, as liquid crystal display devices are used for multimedia in recent years, visibility has become increasingly important as pictures and moving pictures are viewed.

The technical problem to be achieved by the present invention is to implement a multi-domain liquid crystal display device having excellent visibility.

Another object of the present invention is to provide a thin film transistor array panel and a liquid crystal display including the same, which can prevent brightness from being reduced or blurring while ensuring visibility.

In order to solve this problem, the present invention divides the pixel electrode into two or more, and different potentials are applied to the two or more sub pixel electrodes. At this time, different potentials are the same, higher or lower than the image signal voltage transmitted through the data line.

More specifically, in the thin film transistor array panel according to the exemplary embodiment of the present invention, a first signal line is formed on an insulating substrate, and a second signal line insulated from and intersecting the first signal line is formed. A third electrode overlapping the first and second electrodes and the second electrode is formed in each pixel region defined by the intersection of the first signal line and the second signal line. In each pixel, the first thin film transistor and the first and second terminals are connected to the first signal line and the second signal line, and the third terminal is commonly connected to the first and second electrodes. The second terminal is connected to the neighboring first signal line and the first electrode, respectively, and the third terminal is formed with a second thin film transistor connected to the third electrode.

In this case, the first and second electrodes are divided first and second pixel electrodes, and the third electrode is a coupling electrode connected from the third terminal of the second thin film transistor.

At least one of the first and second pixel electrodes preferably has domain dividing means, and the coupling electrode preferably extends from the drain electrode of the second thin film transistor.

A gate insulating film formed between the first signal line and the second signal line, and a passivation film formed between the second signal line and the first and second pixel electrodes, wherein the second terminal of the second thin film transistor is formed on the passivation film. It is connected to the first pixel electrode through a contact hole.

The first and second pixel electrodes are substantially mirror-symmetrical with respect to the upper and lower bisectors of the pixel region, and two long sides of the adjacent boundary lines between the first pixel electrode and the second pixel electrode form 45 ° with the first signal line. Do.

The display device may further include a third signal line that is insulated from and crosses the second signal line and to which a reference potential is applied, and a portion of the third signal line overlaps with the third terminal of the second thin film transistor.

The area of the first pixel electrode and the area of the second pixel electrode may be in a range of 50: 50-80: 20, and may further include a third pixel electrode connected to the first thin film transistor.

In addition, the liquid crystal display according to the exemplary embodiment of the present invention includes a first insulating substrate, a gate line formed on the first insulating substrate and including first and second gate electrodes, a gate insulating film formed on the gate line, and a gate insulating film. A data line including a first semiconductor layer formed on the semiconductor layer, a resistive contact layer formed on the semiconductor layer, and a gate insulating layer, and at least a portion of which is formed on the resistive contact layer, and at least part formed on the resistive contact layer. First and second drain electrodes facing the first gate electrode with respect to the first gate electrode, and formed on an upper portion of the gate insulating layer, and having a second source electrode and a third drain electrode facing each other with respect to the second gate electrode; And the coupling electrode, the data line, the second source electrode, and the first to third drains formed on the gate insulating layer. A passivation layer formed on the pole and the coupling electrode and on the passivation layer and insulated from the first pixel electrode and the first pixel electrode connected to the first drain electrode and the second source electrode and connected to the second drain electrode. At least one of a second pixel electrode, at least partially overlapping the coupling electrode, a second insulating substrate facing the first insulating substrate, a common electrode formed on the second insulating substrate, a first substrate, and the second substrate; And second domain dividing means formed on at least one of the formed first domain dividing means, the first substrate, and the second substrate and dividing the pixel region into a plurality of small domains together with the first domain dividing means.

Preferably, the coupling electrode extends from the third drain electrode, the first domain dividing means is a cutout of at least one of the first pixel electrode and the second pixel electrode, and the second domain dividing means is a cutoff of the common electrode. It is desirable to disclaim.

Preferably, the area of the first pixel electrode and the area of the second pixel electrode are in a range of 50: 50-80: 20, at least a portion of which is formed on the ohmic contact layer and faces the first source electrode with respect to the first gate electrode. The display device may further include a third pixel electrode connected to the fourth drain electrode and the fourth drain electrode.

Preferably, the passivation layer is formed of an organic insulating material, and the semiconductor layer may extend to a lower portion of the data line, and may further include a color filter formed on one of the first and second insulating substrates.

In addition, the liquid crystal display according to another exemplary embodiment of the present invention is formed for each pixel region defined by crossing the first signal line, the second signal line insulated from the first signal line, and the first signal line and the second signal line. First and second pixel electrodes separated from each other, and a common electrode facing the first and second pixel electrodes, wherein the first and second pixel voltages of the first and second pixel electrodes with respect to the common voltage of the common electrode; Is different from the image signal voltage transmitted through the second signal line.

Preferably, the absolute value of the first pixel voltage is smaller than the absolute value of the second pixel voltage, and is connected to the first thin film transistor and the first pixel electrode for controlling the image signal voltage which is commonly transmitted to the first and second pixel electrodes. One terminal may further include a second thin film transistor connecting the second pixel electrode with a coupling capacitance.

The display device may further include a coupling electrode connected to the second thin film transistor and overlapping the second pixel electrode in an insulated state, wherein at least one of the first pixel electrode and the second pixel electrode has domain division means. .

The coupling electrode extends from the drain electrode of the second thin film transistor, and the first and second pixel electrodes are substantially mirror-symmetrical with respect to the upper and lower bisectors of the pixel region, and adjacent boundary lines of the first pixel electrode and the second pixel electrode are adjacent to each other. It is preferable that two long sides form 45 degrees with a 1st signal line.

The area of the first pixel electrode and the area of the second pixel electrode are in a range of 50: 50-80: 20 and preferably further include a third pixel electrode to which an image signal voltage is transmitted.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a structure of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the drawings.

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to a first embodiment of the present invention, FIG. 2 is a layout view of an opposing display panel for a liquid crystal display according to a first embodiment of the present invention, and FIG. 4 and 5 are cross-sectional views of the liquid crystal display of FIG. 3 taken along lines IV-IV 'and VV', respectively, and FIG. A circuit diagram showing a structure of a thin film transistor array panel for a liquid crystal display device according to a first embodiment of the present invention.

The liquid crystal display according to the exemplary embodiment of the present invention is injected between the lower panel 100 and the upper panel 200 facing the lower panel 100 and the lower panel 100 and the upper panel 200 to be perpendicular to the display panels 100 and 200. It consists of the liquid crystal layer 3 containing the liquid crystal molecule orientated in the direction. In this case, alignment layers 11 and 21 are formed on each of the display panels 100 and 200, and the alignment layers 11 and 21 may align the liquid crystal molecules of the liquid crystal layer 3 to be perpendicular to the display panels 100 and 200. It is preferred that the vertical alignment mode be, but it may not be.

First, the configuration of the lower panel is as follows.

First and second pixel electrodes 190a and 190b and a combination of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO) on the lower insulating substrate 110 made of a transparent insulating material such as glass An electrode 176 is formed. The first and second pixel electrodes 190a and 190b are directly connected to the first thin film transistor TFT1 (see FIG. 6) to receive an image signal voltage together. The second pixel electrode 190b may also be connected to the first pixel electrode. It overlaps with the coupling electrode 176 connected to the second thin film transistor TFT2 (see FIG. 6) connected to 190a. The first thin film transistor TFT1 is connected to the gate line 121 that transmits the scan signal and the data line 171 that transmits the image signal, respectively, to the first and second pixel electrodes 190a and 190b according to the scan signal. The applied image signal is turned on. In addition, the second thin film transistor TFT2 is connected to the neighboring gate line 121 and the first pixel electrode 190a and is transferred to the coupling electrode 176 according to a scan signal, and thus an image signal of the first pixel electrode 190a. To control. When the second thin film transistor TFT2 is turned on, the pixel voltage transferred to the first pixel electrode 190a is transferred to the coupling electrode 176, and the coupling electrode 176 overlaps the second pixel electrode 190b. The pixel voltages of the first and second pixel electrodes 190a and 190b that are coupled and capacitively transferred initially are changed, which will be described in detail later. In this case, the first and second pixel electrodes 190a and 190b are separated through the cutouts 191 and 193, and the coupling electrode 176 extends from one terminal of the second thin film transistor TFT2. The two pixel electrode 192 has a cutout 192. In addition, a lower polarizing plate (not shown) is attached to the lower surface of the insulating substrate 110. Here, the first and second pixel electrodes 190a and 190b may not be made of a transparent material in the case of a reflective liquid crystal display, and in this case, the lower polarizer is also unnecessary.

Next, the configuration of the upper panel is as follows.

Also, a black matrix 220 and a red, green, and blue color filter having an opening in the pixel area on the bottom surface of the upper insulating substrate 210 made of a transparent insulating material such as glass to prevent light leaking between the pixel areas ( 230 and a common electrode 270 formed of a transparent conductive material such as ITO or IZO. Herein, the common electrode 270 forms a fringe field together with the cutouts 191, 192, and 193 of the first and second pixel electrodes 190a and 190b to cut and align the liquid crystal molecules. 271, 272, and 273 are formed. The black matrix 220 may be formed not only in the peripheral portion of the pixel region but also in the portion overlapping the cutouts 271, 272, and 273 of the common electrode 270. This is to prevent light leakage caused by the cutouts 271, 272, and 273.

The thin film transistor array panel of the liquid crystal display according to the first embodiment will be described in more detail with reference to FIGS. 1 and 3 to 6.

A plurality of gate lines 121 and storage electrode wirings extending mainly in the horizontal direction are formed on the lower insulating substrate 110.

A plurality of portions of the gate line 121 extend upward and downward to form gate electrodes 124a and 124c of the first and second thin film transistors TFT1 and TFT2. One end portion of the gate line 121 may be widely extended to form a contact portion for connection with an external gate driving circuit, and in the case of having no contact portion as in the present embodiment, the gate driving portion is directly formed on the upper portion of the substrate. An end portion of the gate line 121 is directly connected to the output terminal of the circuit.

Each storage electrode wiring includes a storage electrode line 131 extending in the horizontal direction across the center of the pixel region and a plurality of storage electrodes 133a, 133b, and 136 extending therefrom. The pair of storage electrodes 133a, 133b, and 136 extend in the vertical direction and are connected to each other by the storage electrode line 131 extending in the horizontal direction. In this case, each of the storage electrode lines 131 may be formed of two or more horizontal lines. In addition, the storage electrode 136 extends in a large area, and overlaps with the subsequent coupling electrode 176 to form a storage capacitor.

The gate line 121 and the sustain electrode wirings 131, 133a, 133b, and 136 are made of metal such as Al, Al alloy, Ag, Ag alloy, Cr, Ti, Ta, Mo, or the like. 4 and 5, the gate line 121 and the sustain electrode wirings 131, 133a, 133b, and 136 of the present embodiment are formed of a single layer, but have excellent physicochemical properties of Cr, Mo, Ti, and Ta. It may be composed of a double layer including a metal layer such as Al and an Al-based or Ag-based metal layer having a low specific resistance. In addition, the gate line 121 and the storage electrode lines 131, 133a, 133b, and 136 may be made of various metals or conductors.

The gate line 121 and the storage electrode lines 131, 133a, 133b, and 136 are inclined at sides and preferably have an inclination angle of 30 to 80 ° with respect to the horizontal plane.

The gate insulating layer 140 made of silicon nitride (SiNx) or the like is formed on the gate line 121 and the storage electrode lines 131, 133a, 133b, and 136.

A plurality of drain electrodes 175a, 175b, and 175c, and a plurality of coupling electrodes 176 are formed on the gate insulating layer 140, as well as a plurality of data lines 171. Each of the data lines 171 extends mainly in the vertical direction and extends from the data lines 171 by emitting a plurality of branches toward the first and second drain electrodes 175a and 175b of each of the first thin film transistors TFT1. The source electrode 173a of the first thin film transistor TFT1 is provided. The second drain electrode 175b of the first thin film transistor TFT1 extends to the center portion of the pixel area. The drain electrode 175c of the second thin film transistor TFT2 is positioned above the gate electrode 124c of the second thin film transistor TFT2 and extends to be connected to the coupling electrode 176. A source electrode 173c of the second thin film transistor TFT2 is formed on the opposite side of the drain electrode 175c of the second thin film transistor TFT2. The coupling electrode 176 is connected to the drain electrode 175c of the second thin film transistor TFT2 and extends in a large area to overlap the storage electrode 136.

The data line 171, the source electrodes 173a and 173c, the drain electrodes 175a, 175b and 175c, and the coupling electrode 176 are also made of a material such as chromium and aluminum, like the gate line 121. Or it may be made of multiple layers.

Below the data line 171, the source electrodes 173a and 173c, and the drain electrodes 175a, 175b, and 175c, a plurality of linear semiconductors 151 extending vertically along the data line 171 are formed. . Each linear semiconductor 151 made of amorphous silicon extends toward the gate electrodes 124a and 124c, the source electrodes 173a and 173c, and the drain electrodes 175a, 175b and 175c, respectively, to form the first and second thin film transistors. The channel portions 154a and 154c are formed.

A plurality of linear ohmic contacts between the semiconductor 151 and the data line 171, the source electrodes 173a and 173c, and the drain electrodes 175a, 175b, and 175c to reduce contact resistance between the two, respectively. 161 and the island-like resistive contact members 165a and 165b are formed. The ohmic contact 161 is made of amorphous silicon doped with silicide or n-type impurities at a high concentration, and has an ohmic contact 163a extending in a branch.

On the data line 171, the source electrodes 173a and 173c, and the drain electrodes 175a, 175b, and 175c, an organic material having excellent planarization characteristics, photosensitive properties, and plasma enhanced chemical vapor deposition (PECVD) is formed. A protective film 180 made of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or silicon nitride is formed.

The passivation layer 180 may include a plurality of contact holes 185a and 185b exposing at least a portion of the first and second drain electrodes 175a and 175b of the first thin film transistor and the end portion 179 of the data line 171, respectively. 182 is provided, and a plurality of contact holes 183c exposing the source electrode 173c of the second thin film transistor TFT2 is provided. On the other hand, when the end portion of the gate line 121 also has a contact portion for connecting to an external driving circuit, a plurality of contact holes penetrate the gate insulating layer 140 and the passivation layer 180 to end portions of the gate line 121. Can be exposed.

A plurality of contact assistants 82 are formed on the passivation layer 180, including a plurality of first and second pixel electrodes 190a and 190b. The pixel electrodes 190a and 190b and the contact assistant 82 are made of a transparent conductor such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductor having excellent light reflection characteristics such as aluminum (Al). .

The pixel electrode is classified into a first pixel electrode 190a and a second pixel electrode 190b, and the first pixel electrode 190a is a drain electrode 175a of the first thin film transistor TFT1 through the contact hole 185a. The second pixel electrode 190b is connected to the drain electrode 175b of the first thin film transistor TFT1 through the contact hole 185b. In addition, the first pixel electrode 190a is connected to the source electrode 173c of the second thin film transistor TFT2 through the contact hole 183c, and the second pixel electrode 190b is connected to the drain electrode 175c. It overlaps with the coupling electrode 176. Accordingly, the second pixel electrode 190b is electromagnetically coupled (capacitively coupled) to the coupling electrode 176 connected to the second thin film transistor TFT2 connected to the first pixel electrode 190a.

The boundary dividing the first pixel electrode 190a and the second pixel electrode 190b is divided into portions perpendicular to the portions 191 and 193 forming 45 ° with respect to the gate line 121, and forming a 45 ° portion. The length of the two parts 191 and 193 is longer than that of the vertical part. In addition, the two portions 191 and 193 constituting 45 ° are perpendicular to each other.

The second pixel electrode 190b has a cutout 192, and the cutout 192 penetrates from the right side of the second pixel electrode 190b toward the left side, and the inlet is widened.

Each of the first pixel electrode 190a and the second pixel electrode 190b is substantially a line (parallel with the gate line) that bisects the pixel region defined by the intersection of the gate line 121 and the data line 171. Mirror image symmetry.

The data contact auxiliary member 82 is connected to the end portion 179 of the data line through the contact hole 182. At this time, in the embodiment in which the gate line 121 also has a contact portion at an end portion, a gate contact auxiliary member 81 connected to the gate line 121 may be added on the passivation layer 180.

As illustrated in FIGS. 2 and 3 to 5, a black matrix 220 is formed on the upper insulating substrate 210 facing the lower insulating substrate 110 to prevent light leakage. In this case, the black matrix 220 is schematically illustrated and may be changed into various shapes to block light leaking from around the pixel area or around the thin film transistor. The red, green, and blue color filters 230 are sequentially formed on the black matrix 220. The common electrode 270 having a plurality of cutouts 271, 272, and 273 is formed on the color filter 230. The common electrode 270 is formed of a transparent conductor such as ITO or indium zinc oxide (IZO).

The pair of cutouts 271, 272, and 273 of the common electrode 270 alternate with the portions 191 and 193 that form an angle of 45 ° with respect to the gate line 121 among the boundaries of the first pixel electrodes 190a and 190b. And an end portion arranged in parallel with the diagonal portions and overlapping sides of the first and second pixel electrodes 190a and 190b. At this time, the end is classified into a longitudinal end part and a horizontal end part.

When the thin film transistor array panel and the color filter display panel having the above structure are aligned and combined, and a liquid crystal material is injected and vertically aligned therebetween, a basic structure of the liquid crystal display according to the exemplary embodiment of the present invention is provided.

When the thin film transistor array panel and the color filter display panel are aligned, a pair of cutouts 271, 272, and 273 of the common electrode 270 divide two pixel electrodes 190a and 190b into a plurality of subregions by domain dividing means, respectively. In the present exemplary embodiment, as illustrated in FIG. 3, the two pixel electrodes 190a and 190b are divided into four sub-regions, respectively. As can be seen in FIG. 3, each subregion is elongated to distinguish the width direction from the length direction.

The portion of the liquid crystal layer 3 between the respective subregions of the pixel electrodes 190a and 190b and the corresponding subregions of the reference electrode 270 is referred to as " subregion " When applied, it is classified into four types according to the average major axis direction of the liquid crystal molecules positioned therein, and this is referred to as "domain" in the future.

In the liquid crystal display having the structure, an image signal voltage transmitted through the data line 171 is applied to the first and second pixel electrodes 190a and 190b through the first thin film transistor TFT1. The voltage applied to the first pixel electrode 190a and the second pixel electrode 190b is changed by capacitive coupling through the coupling electrode 176. In this case, the voltage of the first pixel electrode 190a is lower than the image signal voltage transmitted through the data line 171, and the voltage of the second pixel electrode 190b is higher than the image signal voltage. As such, when two pixel electrodes having different voltages are disposed in one pixel area, the two pixel electrodes may compensate for each other to reduce distortion of the gamma curve, which will be described later.

Next, the reason why the voltage of the first pixel electrode 190a low and the voltage of the high second pixel electrode 190b changes with respect to the image signal voltage will be described with reference to FIG. 7.

7 is a graph illustrating a change in voltage in a simulation using a liquid crystal display according to an exemplary embodiment of the present invention. In the liquid crystal display, the voltage of the pixel electrode is based on the common voltage of the common electrode.

As shown in FIG. 6, when an ON signal is transmitted to the gate line 121 positioned above, the same image is applied to the first and second pixel electrodes 190a and 190b through the first thin film transistor TFT1. When the signal voltage is transferred and the upper gate line 121 is turned off, the first and second pixel electrodes 190a and 190b are separated. Subsequently, when an ON signal is transmitted to the lower gate line 121, the first pixel electrode 190a and the coupling electrode 176 are electrically connected to each other through the second thin film transistor TFT2 so that the common electrode 270 is connected. The same potential is formed with respect to the common voltage. In this case, since the coupling electrode 176 and the second pixel electrode 190b overlap each other and are connected capacitively, when the voltage of the coupling electrode 178 changes, the voltage of the second pixel electrode 190b also changes.

In this case, in the liquid crystal display according to the embodiment of the present invention, Clca represents a liquid crystal capacitance formed between the first pixel electrode 190a and the common electrode 270, and Csta represents the first pixel electrode 190a and the sustain. Cgda represents a storage capacitance formed between the electrode wirings 131 and 133a, and Cgda represents a parasitic capacitance formed between the first drain electrode 175a and the gate electrode 124a of the first thin film transistor TFT1. The parasitic capacitance is formed between the source electrode 173c and the gate electrode 124c of the second thin film transistor TFT2. Clcb represents a liquid crystal capacitor formed between the second pixel electrode 190b and the common electrode 270, and Cstb represents a storage capacitor formed between the second pixel electrode 190b and the storage electrode wirings 131, 133b, and 136. Cbc denotes a coupling capacitance formed between the second pixel electrode 190b and the coupling electrode 176, and Cgdb denotes between the second drain electrode 175b and the gate electrode 124a of the first thin film transistor TFT1. Parasitic doses formed in Clcc represents a liquid crystal capacitance formed between the coupling electrode 176 and the common electrode 270, Cstc represents a storage capacitance formed between the coupling electrode 176 and the sustain electrode wiring 136, and Cgdc represents a second thin film transistor. The parasitic capacitance formed between the drain electrode 175c and the gate electrode 124c of (TFT2) is shown.

In FIG. 7, "A" is a line indicating a change in voltage delivered to the first pixel electrode 190a, and "B" is a line showing a change in voltage delivered to the second pixel electrode 190b and "C". Is a line representing the change in voltage delivered to the coupling electrode 176, "D" is a line representing the gate voltage transferred to the upper gate line 121, "E" is transmitted to the lower gate line 121. A line representing the gate voltage, and "F" is a line representing the image signal voltage transmitted through the data line 171. The horizontal axis represents time, and the vertical axis represents the common voltage Vcom and the gray scale voltages (-1V, -2V, -3V, -4V, -5V, and -6V).

As shown in FIG. 7, five voltage changes occurred in each of the n and n + 1 th frames. That is, when the upper gate line 121 is turned on, the same image signal voltages A and B are transmitted to the first and second pixel electrodes 190a and 190b, and the arbitrary voltage C is applied to the coupling electrode 176. Is charged. Subsequently, when the upper gate line 121 is turned off, kickback voltages due to parasitic capacitances of the first and second drain electrodes 175a and 175b and the gate electrode 124a of the first thin film transistor TFT1 are performed. Due to this, the voltages A, B, and C delivered to the respective electrodes 190a, 190b, and 176 vary slightly. Subsequently, when the lower gate line 121 is turned on, each of the electrodes 190a, 190b, and 176 due to the kickback voltage due to the parasitic capacitance of the drain electrode 175c and the gate electrode 124c of the second thin film transistor TFT2. The voltages A, B, and C delivered to are slightly changed. Subsequently, when the lower gate line 121 is turned on, the same potentials A and C are formed at the a pixel electrode 190a and the coupling electrode 176, and the voltage B of the second pixel electrode 190b is changed. In this case, the absolute value of the voltage A transmitted to the first pixel electrode 190a is smaller than the image signal voltage F transmitted through the data line 171 and is transferred to the second pixel electrode 190b. The absolute value of the given voltage B is larger than the image signal voltage F. FIG. Subsequently, when the second thin film transistor TFT2 is turned off, each electrode 190a, due to the kickback voltage due to the parasitic capacitance generated between the drain electrode 175c and the gate electrode 124c of the second thin film transistor TFT2, is formed. Voltages A, B, and C delivered to 190b and 176 vary slightly. In this case, the absolute value of the voltage A transmitted to the first pixel electrode 190a is smaller than the image signal voltage F transmitted through the data line 171 and transmitted to the second pixel electrode 190b. The absolute value of the voltage B is kept larger than the image signal voltage F.

In this case, the voltage difference between the first and second pixel electrodes 190a and 190b is determined by the various capacitances described above, and the most important variable is the coupling capacitance Cbc between the coupling electrode 176 and the second pixel electrode 190b. ) And the storage capacitor Cstc between the coupling electrode 176 and the storage capacitor wiring 136. At this time, the storage capacitor Cstc between the coupling electrode 176 and the storage capacitor wiring 136 is 1/10 of the storage capacitor Csta between the first pixel electrode 190a and the storage capacitor wirings 131 and 133a. It is preferable to be as small as -1/3, and the coupling capacitor Cbc between the coupling electrode 176 and the second pixel electrode 190b may include the storage capacitor Cstc between the coupling electrode 176 and the storage capacitor wiring 136. It is desirable not to exceed twice each other in a range similar to).

In addition, it is preferable that the coupling electrode 176 is completely covered by the second pixel electrode 190b, and thus the liquid crystal capacitance Clcc between the coupling electrode 176 and the common electrode 270 is almost close to zero. desirable. As in the exemplary embodiment of the present invention, the coupling electrode 176 is preferably formed of the same layer as the data line 171 and disposed between the second pixel electrode 190b and the storage electrode 136, where the maximum The aperture ratio of can be secured. Of course, the storage electrode 136 and the coupling electrode 176 may be disposed without overlapping each other, and the structure of the storage capacitor wirings 131, 133a 133b, and 136 may be variously modified, and the coupling electrode 176 may also be varied. Can be modified.

In addition, it is preferable that Cgda and Cgdb have similar sizes to each other, and Cgdc should be larger than Cgdb.

Next, the pixel voltage and the image signal voltage obtained through the simulation will be described in detail.

8 is a graph illustrating pixel voltages and image signal voltages obtained through a simulation using a liquid crystal display according to an exemplary embodiment of the present invention. The pixel voltages are “A” and “B” as voltages transmitted to the first and second pixel electrodes 190a and 190b, and the image signal voltages are represented by solid lines as voltages transmitted through the data line 171.

As shown in FIG. 8, when the image signal voltage is 2V, the difference between the voltages of the first and second pixel electrodes 190a and 190b is 0.59V, and when the image signal voltage is 5V, it is 1.19V. appear. At 5V, the voltage drop of the first pixel electrode 190a was 0.55V, and the voltage rise of the second pixel electrode 190b was 0.64V. Here, the voltage drop or the voltage rise can be freely adjusted by changing the capacitance value or the area of the electrode.

In the simulation according to the exemplary embodiment of the present invention, the ratio of the area of the first pixel electrode 190a to the area of the second pixel electrode 190b is preferably in a range of 50: 50-80: 20 under 70 ° C. It is most preferably in the range of 30 to 80:20, and the voltage ratio between the first pixel electrode 190a and the second pixel electrode 190b is most preferably in the range of 1: 1.3 to 1: 1.5. Let's explain.

9 and 10 are graphs showing voltage ratios and area ratios of divided pixel electrodes obtained through a simulation using a liquid crystal display according to an exemplary embodiment of the present invention. In FIG. 9, the horizontal axis represents an area ratio of occupied by the second pixel electrode 190b in one unit pixel. In FIG. 10, the horizontal axis represents a pixel voltage ratio of the first pixel electrode 190a and the second pixel electrode 190b. And the vertical axis in FIG. 10 is the amount of visibility distortion. Here, "60 degrees to the right" is a position which becomes 60 degrees to the right direction from the front of a liquid crystal display, and "diagonal 60 degrees" means the position which becomes 60 degrees to a diagonal direction from the front of a liquid crystal display.

Even if the pixel electrode is divided, the visibility of the liquid crystal display device must be minimized in order to ensure display characteristics. As shown in FIG. 9, the area occupied by the second pixel electrode 190b is 20 to minimize the amount of visibility distortion. -30% is preferred. Therefore, the area ratio of the first pixel electrode 190a and the second pixel electrode 190b is preferably in the range of 80: 20-70: 30.

In addition, as shown in FIG. 10, in order to minimize the amount of visibility distortion, the voltage ratio between the first pixel electrode 190a and the second pixel electrode 190b is preferably in the range of 1.3 to 1.5.

Next, as described above, when two or more pixel electrodes in which different voltages are transmitted are disposed in one pixel, the sub-pixel electrodes compensate for each other, and thus the distortion of the gamma curve will be described in detail.

FIG. 11A is a graph illustrating distortion of a gamma curve in a liquid crystal display without dividing one pixel, and FIG. 11B is a liquid crystal display in which one pixel is divided into two subpixels to which different pixel voltages are transmitted, as in an exemplary embodiment of the present invention. FIG. 11C is a graph illustrating distortion of a gamma curve in a liquid crystal display in which a pixel is divided into three sub-pixels to which different pixel voltages are transmitted. 11A to 11C, the horizontal axis is gray scale, the vertical axis is luminance amount according to gray scale, the solid line shows the front gamma curve, and the dotted line shows the side gamma curve. It is shown.

As shown in FIG. 11A, in the general liquid crystal display, that is, the liquid crystal display in which only one pixel electrode is formed in one pixel, the gamma curve of the side surface is greatly distorted upward compared to the front gamma curve. In particular, it can be seen that the luminance is drastically increased at low gray levels, resulting in severe distortion of the gamma curve.

However, as shown in FIG. 11B, the pixel electrode is divided into two pixel electrodes (a first sub pixel electrode and a second sub pixel electrode), and the first and second sub pixel electrodes are divided by a thin film transistor or a coupling electrode. When combined with each other, as in the exemplary embodiment of the present invention, the first and second pixel electrodes 190a and 190b transmit a pixel voltage higher or lower than the image signal voltage transmitted through the data line 171 to display an image. do. In this case, when the portion having the pixel electrode to which the pixel voltage higher than the image signal voltage is transmitted is the first sub pixel, and the portion having the pixel electrode to which the pixel voltage lower than the image signal voltage is transmitted is the second sub pixel, The second sub-pixel shifted to a low pixel voltage at is almost black, and only the first sub-pixel shifted to a high voltage mainly displays an image so that the luminance amount of all the pixels is reduced (Fig. 11B). " part). On the other hand, in a high gradation of more than an arbitrary gradation, the second sub-pixel also displays an image so that the luminance amount of all the pixels increases ("second sub-pixel" in Fig. 11B). Therefore, as shown in Fig. 11B, the distortion of the side gamma curve is reduced.

Of course, in an embodiment in which one pixel electrode is divided into three parts, a side gamma curve as shown in FIG. 11C can be obtained through the same principle, and thus distortion of the side gamma curve is further reduced, which will be described in detail. do.

In the above embodiment, only the structure in which the pixel electrode of the unit pixel is divided into two as shown in FIG. 6 is described. However, the pixel electrode may be divided into two or more, and the pixel electrode is divided into three. Shall be.

12 is a circuit diagram schematically illustrating a structure of a liquid crystal display including a thin film transistor array panel according to a second exemplary embodiment of the present invention.

As shown in FIG. 12, the structure of the thin film transistor array panel according to the second exemplary embodiment of the present invention is substantially the same as that of FIG. 6.

However, unlike FIG. 6, not only the first and second pixel electrodes 190a and 190b but also the third pixel electrode 190c are formed in each unit pixel, and the third pixel electrode 190c is formed of the first and second pixel electrodes 190c. The two pixel electrodes 190a and 190b are connected to the first thin film transistor TFT1 which is commonly connected.

In this structure, the first to third pixel electrodes 190a, 190b, and 190c are connected to the first thin film transistor TFT1 (see FIG. 6) to receive an image signal voltage together. As described above, the first and second pixels The pixel voltage transmitted to the electrodes 190a and 190b is changed, and the image voltage transmitted through the data line 171 is maintained in the third pixel electrode 190c.

Even if the pixel voltage is applied differently by dividing the pixel electrode to improve the side visibility of the display device, if the voltage drop is excessively greater than 1V, the luminance of the pixel is severe. In addition, when the image signal voltage is transmitted to one pixel electrode as it is to increase the voltage and the other pixel electrode is connected by the coupling capacitance, the brightness does not decrease, but there is a problem such as blurring of characters.

In the structure as in the embodiment of the present invention, since the voltage drop does not occur severely, the side visibility can be improved and the luminance can be prevented from being reduced. Also, there is no problem such as blurring of characters, thereby ensuring display characteristics of the display device. Could.

Meanwhile, the thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention may have a structure different from those of FIGS. 1 to 5, and may include red, green, and blue color filters. In this embodiment, a structure having all of them will be described in detail with reference to the accompanying drawings.

FIG. 13 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a third exemplary embodiment of the present invention, and FIGS. 14 and 15 are cut along the lines XIV-XIV ′ and XV-XV ′ in FIG. 13. It is sectional drawing.

As shown in FIGS. 13 to 15, the layer structure of the thin film transistor array panel for a liquid crystal display device according to the present embodiment is generally the same as the layer structure of the thin film transistor array panel for liquid crystal display devices shown in FIGS. 1 to 5. That is, the plurality of gate lines 121 including the plurality of gate electrodes 124a and 124b are formed on the substrate 110, and the gate insulating layer 140 and the plurality of protrusions 154a and 154b are formed thereon. A plurality of linear semiconductors 151, a plurality of linear ohmic contacts 161 each including a plurality of protrusions 163a, and a plurality of island-type ohmic contacts 163c, 165a, 165b, and 165c are formed in this order. On the ohmic contacts 161, 165a, 165b, and 165c and the gate insulating layer 140, a plurality of data lines 171 including a plurality of source electrodes 173a, first and second drain electrodes of the first thin film transistor ( 175a, .175b, the source electrode 173c, the drain electrode 175c, and the coupling electrode 176 of the second thin film transistor are formed, and a protective film 180 is formed thereon. The passivation layer 180 and / or the plurality of contact holes 182, 185a, 185b, and 183c are formed, and the plurality of first and second pixel electrodes 190a and 190b and the plurality of contact assistant members are disposed on the passivation layer 180. 82 is formed.

However, unlike the thin film transistor array panel illustrated in FIGS. 1 to 5, in the thin film transistor array panel according to the present exemplary embodiment, the semiconductor 151 may include the data line 171 and the first line except for the protrusions 154a and 154b in which the thin film transistor is located. Substantially the same as the first and second drain electrodes 175a and 175b, the source electrode 173c and the drain electrode 175c of the second thin film transistor, and the ohmic contacts 161, 163c, 165a, 165b, and 165c thereunder. It has a flat shape.

In addition, red, green, and blue color filters 230 are sequentially formed in the lower portion of the passivation layer 180. The red, green, and blue color filters 230 each have a boundary above the data line 171 and are vertically formed along a pixel column, and neighboring color filters partially overlap each other on the data line 171. The hill can be formed on the data line 171. In this case, the red, green, and blue color filters 230 overlapping each other may have a function of a black matrix that blocks light leaking between neighboring pixel areas. Accordingly, the black matrix may be omitted in the opposing display panel for the liquid crystal display according to the present exemplary embodiment so that only the common electrode 270 may be formed.

The thin film transistor array panel for the present liquid crystal display device forms the data line 171, the drain electrodes 175a, 175b, and 175c and the semiconductor layer 151 by a photolithography process using a single photoresist pattern, and the photoresist pattern is a thin film. The portion corresponding to the channel portion of the transistor has a lower thickness than the portion corresponding to other data lines and drain electrodes. In this case, the photoresist pattern is an etch mask for patterning the semiconductor 151, and the thick portion is used as an etch mask for patterning the data line and the drain electrode. In this manufacturing method, two different thin films may be formed in one photosensitive film pattern to minimize manufacturing costs.

In addition, one end portion 129 of the gate line 121 having the gate electrodes 124a and 124b has a contact portion for connection with an external circuit.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights. In particular, the arrangement of the cutouts formed in the pixel electrode and the common electrode may be variously modified.

Through the above configuration, the display characteristics can be improved by improving the side visibility of the liquid crystal display device while preventing luminance from being reduced and eliminating character disturbances.

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention.

2 is a layout view of an opposing display panel for a liquid crystal display according to a first exemplary embodiment of the present invention;

3 is a layout view of a liquid crystal display according to a first exemplary embodiment of the present invention;

4 and 5 are cross-sectional views of the liquid crystal display of FIG. 3 taken along lines IV-IV 'and V-V', respectively;

6 is a circuit diagram illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention.

7 is a graph illustrating a change in voltage in a simulation using a liquid crystal display according to an exemplary embodiment of the present invention.

8 is a graph illustrating pixel voltages and image signal voltages obtained through a simulation using a liquid crystal display according to an exemplary embodiment of the present invention.

9 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

10 and 11 are cross-sectional views taken along the lines X-X 'and XI-XI' of FIG. 9;

12 is a circuit diagram schematically illustrating a structure of a liquid crystal display including a thin film transistor array panel according to a second exemplary embodiment of the present invention.

FIG. 13 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a third exemplary embodiment of the present invention.

14 and 15 are cross-sectional views taken along the lines XIV-XIV ′ and XV-XV ′ in FIG. 13.

121 gate line, 124a, 124c gate electrode,

131, 133a, and 133b sustain electrodes, 176 bond electrodes,

171 data lines, 173a, 173c source electrode,

175a, 175b, 175c drain electrodes, 190a, 190b pixel electrodes,

191, 192, 193 incisions, 151, 154a, 154c amorphous silicon layer,

270 common electrode, 271, 272, 273 incision

Claims (30)

Insulation board, A first signal line formed on the insulating substrate, A second signal line insulated from and intersecting the first signal line, First and second electrodes formed in respective pixel regions defined by the crossing of the first signal line and the second signal line; A third electrode formed in each of the pixels and overlapping the second electrode; A first thin film transistor having first and second terminals connected to the first signal line and the second signal line, and having a third terminal connected to the first and second electrodes in common; First and second terminals are respectively connected to the adjacent first signal line and the first electrode, and the third terminal is connected to the third electrode. Thin film transistor array panel comprising a. In claim 1, The first and second electrodes are divided first and second pixel electrodes. The third electrode is a thin film transistor array panel connected to the third terminal of the second thin film transistor. In claim 2, And at least one of the first and second pixel electrodes has domain dividing means. In claim 2, And the coupling electrode extends from the drain electrode of the second thin film transistor. In claim 2, A gate insulating film formed between the first signal line and the second signal line and a protective film formed between the second signal line and the first and second pixel electrodes; The second terminal of the second thin film transistor is connected to the first pixel electrode through a contact hole formed in the passivation layer. In claim 2, The thin film transistor array panel of claim 1, wherein the first and second pixel electrodes are substantially mirror-symmetric with respect to upper and lower bisectors of the pixel region. In claim 6, 2. The thin film transistor array panel of claim 1, wherein two long sides of adjacent boundary lines between the first pixel electrode and the second pixel electrode form a 45 ° angle with the first signal line. In claim 2, And a third signal line insulated from and intersecting the second signal line and to which a reference potential is applied. In claim 8, A portion of the third signal line overlaps with the third terminal of the second thin film transistor. In claim 2, The area of the first pixel electrode and the area of the second pixel electrode are in a range of 50: 50-80: 20. In claim 2, And a third pixel electrode connected to the first thin film transistor. First insulating substrate, A gate line formed on the first insulating substrate and including first and second gate electrodes; A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film, An ohmic contact layer formed on the semiconductor layer; A data line formed on the gate insulating layer and including at least a portion of a first source electrode formed on the ohmic contact layer; First and second drain electrodes at least partially formed on the ohmic contact layer and facing the first source electrode with respect to the first gate electrode, A second source electrode and a third drain electrode formed on the gate insulating layer and facing each other with respect to the second gate electrode; A coupling electrode formed on the gate insulating film, A passivation layer formed on the data line, the second source electrode, the first to third drain electrodes, and the coupling electrode; A first pixel electrode formed on the passivation layer and connected to the first drain electrode and the second source electrode; A second pixel electrode insulated from the first pixel electrode, connected to the second drain electrode, and overlapping at least a portion of the coupling electrode; A second insulating substrate facing the first insulating substrate, A common electrode formed on the second insulating substrate, First domain dividing means formed on at least one of the first substrate and the second substrate, Second domain dividing means formed on at least one of the first substrate and the second substrate and dividing the pixel region into a plurality of small domains together with the first domain dividing means; Liquid crystal display comprising a. In claim 12, And the coupling electrode extends from the third drain electrode. In claim 12, The first domain dividing means is a cutout portion of at least one of the first pixel electrode and the second pixel electrode. And the second domain dividing means is a cutout of the common electrode. In claim 12, The area of the first pixel electrode and the area of the second pixel electrode are in a range of 50: 50-80: 20. In claim 12, A fourth drain electrode formed on at least a portion of the ohmic contact layer and facing the first source electrode with respect to the first gate electrode, A third pixel electrode connected to the fourth drain electrode Liquid crystal display further comprising. In claim 12, The passivation layer is formed of an organic insulating material. In claim 12, And the semiconductor layer extends below the data line. In claim 12, And a color filter formed on one of the first and second insulating substrates. First signal line, A second signal line insulated from and intersecting the first signal line, First and second pixel electrodes formed in respective pixel regions defined by crossing the first signal line and the second signal line, and separated from each other; A common electrode facing the first and second pixel electrodes Including; The first and second pixel voltages of the first and second pixel electrodes with respect to the common voltage of the common electrode are different from the image signal voltage transmitted through the second signal line. The method of claim 20, The absolute value of the first pixel voltage is less than the absolute value of the second pixel voltage. The method of claim 20, And a first thin film transistor configured to control the image signal voltage which is commonly transmitted to the first and second pixel electrodes. The method of claim 22, And a second thin film transistor connected to the first pixel electrode and having one terminal connected to the second pixel electrode with a coupling capacitance. The method of claim 23, And a coupling electrode connected to the second thin film transistor and overlapping the second pixel electrode in an insulated state. The method of claim 24, And at least one of the first pixel electrode and the second pixel electrode has domain dividing means. The method of claim 24, And the coupling electrode extends from the drain electrode of the second thin film transistor. The method of claim 24, And the first and second pixel electrodes are substantially mirror-symmetric with respect to upper and lower bisectors of the pixel region. The method of claim 27, And two long sides of adjacent boundary lines between the first pixel electrode and the second pixel electrode are 45 ° with the first signal line. The method of claim 20, The area of the first pixel electrode and the area of the second pixel electrode are in a range of 50: 50-80: 20. The method of claim 20, And a third pixel electrode to which the image signal voltage is transmitted.