KR20050013042A - Light emitting diode having vertical electrode structure, manufacturing method of the same and etching method of sapphire substrate - Google Patents

Abstract

PURPOSE: A light emitting diode having a vertical electrode structure, a manufacturing method for the same are provided for simplifying a manufacturing process. CONSTITUTION: A basic substrate(17) is provided with a via. A first conductive contact layer(15) is formed on the basic substrate. A first conductive clad layer(143) is formed on the first conductive contact layer. A light emitting layer(142) is formed on the first conductive clad layer. A second conductive clad layer(141) is formed on the light emitting layer. A second conductive contact layer(13) is formed on the second conductive clad layer. A first electrode(12) is formed on the second conductive contact layer. A second electrode(19) is connected with the first conductive contact layer through the via.

Description

Light emitting diode having vertical electrode structure, manufacturing method of the same and etching method of sapphire substrate

The present invention relates to a light emitting diode and a method of manufacturing the same.

A light emitting diode is an optical device that generates light when a forward current flows. A light emitting diode is a light emitting diode that emits blue and ultraviolet light following a red and green light emitting diode using a pn junction structure of a compound semiconductor such as indium phosphorus (InP), gallium arsenide (GaAs), and gallium phosphorus (GaP). Has been developed and widely used in display devices, light source devices, and environmental application devices. Recently, white light emitting diodes that emit white light using three chips of red, green, and blue or phosphors have been developed and applied to lighting. The range is getting wider.

In the case of using a nitride based thin film structure as a light emitting material in such a light emitting diode, sapphire having a similar lattice constant and crystal structure is used as a base substrate to reduce crystal defects during epitaxial growth.

By the way, since sapphire is an insulator, both a 2nd electrode and a 1st electrode are formed in the growth surface side of an epi layer. As such, when both electrodes are formed on the same surface, the area of the electrode required for wire bonding must be secured, and thus the chip area of the light emitting diode must also be larger than a predetermined size. Therefore, it is an obstacle to the improvement of the chip production per wafer. In addition, since the insulator is used as a substrate, it is difficult to discharge static electricity from the outside, which is likely to cause defects due to static electricity. This reduces the reliability of the device and introduces several limitations in the packaging process. In addition, since sapphire has low thermal conductivity, it is difficult to dissipate heat generated while driving a light emitting diode to the outside, and thus, sapphire is also restricted in applying a large current for high power.

The present invention has been made to solve the above problems, and an object thereof is to provide a light emitting diode having a vertical electrode structure and a method of manufacturing the same.

Another object of the present invention is to simplify the process of manufacturing a light emitting diode having a vertical electrode structure.

1 is a cross-sectional view of a light emitting diode having a vertical electrode structure according to a first embodiment of the present invention.

2 is a cross-sectional view of a light emitting diode chip having a vertical electrode structure according to a first embodiment of the present invention.

3 is a plan view of a light emitting diode chip having a vertical electrode structure according to a first embodiment of the present invention viewed from a sapphire substrate.

4 is a plan view of a light emitting diode chip having a vertical electrode structure according to a second embodiment of the present invention viewed from a sapphire substrate.

5 is a photograph of the surface of the sapphire substrate after forming a specific pattern on the sapphire substrate by the wet etching method and then etching the sapphire substrate by the wet etching method.

6 is a graph showing etching rates of sapphire and GaN by ICP / RIE dry etching.

7 is a graph showing the etching rate when wet etching sapphire and GaN with a mixture solution of sulfuric acid and phosphoric acid.

8 is a surface photograph of a buffer layer after removing a sapphire substrate by a wet etching method.

9 is a voltage-current characteristic curve of a nitride based semiconductor layer after removing the sapphire substrate by a wet etching method.

10 is a cross-sectional view of a light emitting diode having a vertical electrode structure according to a third embodiment of the present invention.

11 is a cross-sectional view of a light emitting diode chip having a vertical electrode structure according to a third embodiment of the present invention.

12 is a plan view of a light emitting diode chip having a vertical electrode structure according to a third embodiment of the present invention as viewed from a sapphire substrate.

13 is a cross-sectional view of a light emitting diode chip having a vertical electrode structure according to a fourth embodiment of the present invention.

14 is a cross-sectional view of a light emitting diode having a vertical electrode structure according to a fifth embodiment of the present invention.

15 is a cross-sectional view of a light emitting diode chip having a vertical electrode structure according to a fifth embodiment of the present invention.

FIG. 16 is a plan view of a light emitting diode chip having a vertical electrode structure according to a fifth embodiment of the present invention, viewed from a first electrode side. FIG.

17 is a cross-sectional view of a light emitting diode chip having a vertical electrode structure according to a sixth embodiment of the present invention.

FIG. 18 is a plan view of a light emitting diode chip having a vertical electrode structure according to a fifth embodiment of the present invention as viewed from the first electrode side. FIG.

12 first electrode

11 first reflections and Sumi layer

13 p-type contact layer

15 n-type contact layer

16 buffer layer

17 sapphire substrate

18 Second Reflection and Ohmic Layer

19 second electrode

141 p-type cladding layer

142 light emitting layer

143 n-type cladding layer

20, 21 leadframe

22 conductive paste

23 transparent ohmic layers

24 wire

25 transmissive first electrode

26 first electrode pad

27 insulating film

28 mesh second electrode

29 First electrode pad (when the first electrode is mesh)

In order to achieve the above object, the present invention proposes the following light emitting diode.

A base substrate having vias formed by etching part or almost the entire surface of the base substrate for thin film growth, a first conductive contact layer formed on the base substrate, and a first substrate formed on the first conductive contact layer A first conductive cladding layer, a light emitting layer formed on the first conductive cladding layer, a second conductive cladding layer formed on the light emitting layer, a second conductive type cladding layer formed on the second conductive cladding layer, A light emitting diode including a first electrode formed on the second conductive contact layer and a second electrode connected to the first conductive contact layer through the via is provided.

In this case, a buffer layer is formed between the base substrate and the first conductive type contact layer and has a via overlapping at least a portion of the via of the base substrate, between the first electrode and the second conductive type contact layer. The display device may further include a first reflection and ohmic layer formed thereon, and a second reflection and ohmic layer formed between the second electrode and the first conductive type contact layer. The second electrode may extend to a position outside the via to form a pad on the base substrate, and the first electrode may be formed of Ni, Cr, Rh, Pd, Au, Ti, Pt, Au. , A single layer or a plurality of layers including at least one of Ta, Al, the second electrode is a single layer or a plurality of at least one of Ti, Al, Rd, Pt, Ta, Ni, Cr, Au It can be made of layers. In addition, when the second electrode is viewed from the base substrate, the planar shape may be formed in a shape having a plurality of branches extending from the center point.

Here, the buffer layer has a composition ratio of _{In x (Ga y Al 1-} y) is preferably made of N, and the _{In x (Ga y Al 1-} y) N may be x≥0, y≥0. In addition, the base substrate may be made of sapphire, the thickness of the base substrate is 40um to 300um, the surface of which the thin film is not formed is preferably mirror-polished, the roughness of the mirror-polished surface of the base substrate It is preferable that it is 1 micrometer or less.

The first conductivity type may be n-type, the second conductivity type may be p-type, and vias of the base substrate and the buffer layer may be slightly wider as they approach the first conductivity type contact layer. It is preferable that it is a narrowing form and the unevenness | corrugation is formed in the surface where the thin film of the said base substrate is not formed. The unit length of the concave-convex portion and the concave portion is that the light emitted by the light emitting diode is 1 / 4n of the wavelength (n is the refractive index of the medium. Therefore, the refractive index of sapphire in the case of convex, and the refractive index of air in the case of concave). It is desirable to have photonic crystal characteristics.

In addition, the first electrode may be adhered through a conductive paste, and the second electrode may further include a lead frame electrically connected through wire bonding.

A reflective and ohmic layer formed between the first electrode and the second conductive type contact layer, and formed between the second electrode and the first conductive type contact layer and extending outside the via to form the base. The substrate may further include a transparent conductive layer covering a predetermined surface of the substrate surface, wherein the transparent conductive layer includes at least one of ITO, ZrB, ZnO, InO, SnO, In _x , and (Ga _y Al _1-y ) N. It is preferable to make it.

The first electrode may be formed of a transparent conductive material, and may be formed between the second electrode and the first conductive type contact layer and may reflect and / or cover the inner surface of the via as well as the base substrate. It is preferable to further include a mix layer, and the first electrode preferably comprises at least one of ITO, ZrB, ZnO, InO, SnO, and In _x (Ga _y Al _1-y ) N. When the first electrode is formed of In _x (Ga _y Al _1-y ) N, the thickness thereof is preferably about 20 μm to 200 μm.

In this case, the buffer layer preferably includes In _x (Ga _y Al _1-y ) N, and the surface of the first electrode may be formed in the irregular shape of the net, is formed on the first electrode The display device may further include a first electrode pad penetrating the first electrode and contacting the second conductive contact layer. In addition, the second electrode may be bonded through a conductive paste, and the first electrode may further include a lead frame electrically connected through wire bonding.

The first electrode may be formed of a transparent electrode such as NiO, Ni / Au, and the first electrode may be formed of an ohmic metal and may have a network structure through which light may pass, and the base substrate may be easily extracted. Corners on the opposite side of the surface where the buffer layer is formed may be chamfered, and the first and second conductive contact layers, the first and second clad layers, and the light emitting layer may be In _x (Ga _y Al _1-y ). It is preferable that N (x ≧ 0, y ≧ 0).

The light emitting diode may be formed by sequentially forming a buffer layer, a first conductive contact layer, a first conductive clad layer, a light emitting layer, a second conductive clad layer, a second conductive contact layer, and a first electrode on the base substrate. Lapping and polishing a substrate, forming a protective film on the surface of the first electrode and the base substrate, partially etching the protective film on the base substrate to partially expose the surface of the base substrate, and a surface of the base substrate. Etching the exposed portion and the underlying buffer layer to form a via, forming a second electrode connected to the first conductive type contact layer through the via; It is manufactured through.

In this case, after laminating the first electrode, the method may further include heat treatment at a temperature between 500 ° C. and 700 ° C. in an furnace of oxygen or nitrogen atmosphere, and before lapping and polishing the base substrate. Preferably, the method further includes attaching an auxiliary substrate. The auxiliary substrate may be an insulating substrate such as sapphire, glass, or quartz, a semiconductor substrate such as Si, GaAs, InP, or InAs, a conductive oxide substrate such as indium tin oxide (ITO), ZrB, or ZnO, CuW, Mo, Au, It may be any one of a metal substrate, such as Al and Au, and it is preferable to use wax as an adhesive for attachment of the said auxiliary substrate.

In the lapping and polishing of the base substrate, the surface of the base substrate may be mirror polished to have a roughness of 1 μm or less. In the step of photographic etching the protective film on the base substrate, a wet using a BOE solution as an etching solution may be used. Etching methods can be used, or RIE dry etching can be used.

In the forming of the via, any one of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), and aluene (Aluetch: 4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) A mixed solution of one or a combination thereof may be used as an etching solution, and the etching solution is preferably used in a state of being heated to a temperature of 30 ° C. or higher.

Alternatively, the forming of the via may include sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), and aluene (Aluetch: 4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O). Wet etching using a mixed solution of any one or a combination thereof as an etchant and ICP / RIE or RIE dry etching may be performed in parallel. The wet etching may be used to etch the base substrate, and the dry etching may be used to etch the buffer layer, and the buffer layer may be In _x (Ga _y Al _1-y ) N (x≥0, y≥ 0) and may be used as an etch stop layer of the wet etching. In addition, by monitoring the electrical characteristics in the via using a probe (probe station) it can be confirmed whether the first conductive type contact layer is exposed, the dry etching is carried out in BCL ₃ , Cl ₂ , HBr, Ar At least one may be used as an etching gas.

Further, a second ohmic layer is further formed on the second conductive contact layer before forming the first electrode, and a second ohmic contacting the first conductive contact layer before forming the second electrode. It is preferable to further form a mix layer, and the first and second ohmic layers may have light reflection characteristics according to the structure of the light emitting diode to extract light. Alternatively, the first ohmic layer may have a light reflection characteristic, or the second ohmic layer may be made of a light transmissive conductive material.

In the forming of the first electrode, a through hole exposing the second conductive contact layer is formed, and a first electrode pad is formed on the first electrode to contact the second conductive contact layer. Further comprising, the first electrode may be formed of a transparent conductive material. At least one of the first electrode and the second electrode may be formed using an electroplating method, and the electrode formed by the electroplating method includes at least one of Ti, Au, Cu, Ni, Al, and Ag. It is preferable. The method of claim 31,

The first electrode or the second electrode may be formed by depositing NiO, NiAu, and heat-treating at a temperature of 100 ° C. or higher in an atmosphere containing oxygen, and the first electrode may be formed of In _x (Ga _y Al ₁ by VPE method. _-y ) N can be formed by growing to a thickness of 20um ~ 200um, it is preferable to form the thickness of the base substrate from 50um to 70um in the step of lapping and polishing the base substrate.

The lapping and polishing of the base substrate may be any one of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), and aluene (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) or It can be carried out by using a wet etching using a mixed solution of the combination as an etching solution, and further comprising the step of separating the base substrate for each chip, the step of separating the base substrate for each chip is wet etching and Dry etching may be performed using at least one, and the step of separating the base substrate by individual chips may include sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), and aluene (4H ₃ PO ₄ + 4CH _3). It is possible to proceed using wet etching using a mixed solution of any one of COOH + HNO ₃ + H ₂ O) or a combination thereof as an etching solution. In addition, in the forming of the via by etching the exposed portion of the base substrate and the lower buffer layer, a scribing line for separating the base substrate by individual chips may be performed together. .

The method may further include forming an etch stop layer on a portion of the base substrate on which the via is to be formed before forming the buffer layer on the base substrate.

In the present invention, the step of preparing a sapphire substrate on which a nitride-based semiconductor is grown, the sapphire substrate is sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ) and aluene (4H ₃ PO ₄ + 4CH ₃ COOH It provides a method of etching a sapphire substrate comprising the step of wet etching by immersion in a mixed solution of any one of + HNO ₃ + H ₂ O) or a combination thereof.

In this case, the method may further include dry etching the sapphire substrate by ICP / RIE technology, and the dry etching may be preceded by the wet etching. At this time, any one of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) during the wet etching or It is preferable to heat the mixed solution by these combinations to the temperature of 30 degreeC or more, and the said heating is preferably the indirect heating system using light absorption.

Further, forming a buffer layer, a first conductive type contact layer, a first conductive type clad layer, a light emitting layer, a second conductive type clad layer, a second conductive type contact layer, and a first electrode on the base substrate in order; Attaching an auxiliary substrate, polishing or etching the base substrate to remove some or all of the thickness of the base substrate, and forming a second electrode electrically connected to the first conductive type contact layer. A method of manufacturing a light emitting diode is proposed.

At this time, the thickness of the base substrate after polishing or etching is preferably between 0.1um ~ 250um.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a preferred embodiment of a light emitting diode having a vertical electrode structure according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a light emitting diode having a vertical electrode structure according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a light emitting diode chip having a vertical electrode structure according to a first embodiment of the present invention. 3 is a plan view of the light emitting diode chip having the vertical electrode structure according to the first embodiment of the present invention as viewed from the sapphire substrate side.

The light emitting diode according to the embodiment of the present invention includes a lead frame 20 and 21, a chip bonded to the lead frame 20 and 21, a conductive paste 22 to attach the chip to the lead frame 20, And a wire 24 for connecting one electrode of the chip to the lead frame 21.

The chip is formed on the sapphire substrate 17 by the buffer layer 16, the n-type contact layer 15, the n-type cladding layer 143, the light emitting layer 142, the p-type cladding layer 141, the p-type contact layer 13, The first reflective and ohmic layer 11 and the first electrode 12 are stacked in order from the bottom up, and the second reflective and ohmic layer is formed inside the via penetrating the sapphire substrate 17 and the buffer layer 16. It has a structure in which 18 and the second electrode 19 are formed.

Here, the second reflective and ohmic layer 18 covers a portion of the inner surface of the via and contacts the n-type contact layer 15, and the second electrode 19 fills the via to a predetermined depth. It is formed. At this time, it is preferable that the via has a form in which the width becomes narrower toward the bottom. In addition, the horizontal cross-sectional shape of the via may be variously modified, such as a circle or a square, and the number of vias may be formed as well as a plurality.

It is preferable that the thickness of the sapphire substrate 17 has a thickness between 40 um and 300 um, particularly preferably between 50 um and 70 um.

In addition, irregularities are formed on the surface of the sapphire substrate 17. In the unevenness, the unit length of the uneven portion and the convex portion is 1 / 4n of the wavelength of light emitted by the light emitting diode (n is the refractive index of the medium. Therefore, the refractive index of the sapphire in the case of the convex portion, and the refractive index of air in the case of the concave portion) It is desirable to have photonic crystal characteristics. This is to concentrate the light emitted by the refraction in the normal direction of the sapphire substrate 17. It is important to secure the depth of the unevenness of 1um or more, but in some cases, the diode may be designed to increase the light extraction efficiency by increasing the critical angle of the light by increasing the depth of the unevenness of 5um or more. Therefore, the depth of the unevenness is between 2um ~ 20um.

The first electrode 12 is made of any one of Ni, Cr, Rh, Pd, Au, Ti, Pt, Au, Ta, Al, or an alloy of these metals, and the buffer layer 16 and the n-type and p-type contact layers. (15, 13) consists of In _x (Al _y Ga _1-y ) N. Where x and y have a value greater than or equal to zero.

The n-type contact layer 15 is doped with a Si impurity of 10 ¹⁸ or more, and the p-type contact layer 13 is doped with a Mg impurity of 18 ¹⁸ or more.

The second electrode 19 is made of any one of Ti, Al, Rd, Pt, Ta, Ni, Cr, Au, or an alloy of these metals.

The n-type and p-type cladding layers 143 and 141 and the light emitting layer 142 are formed of In _x (Al _y Ga _1-y ) N. Where x and y have a value greater than or equal to zero. In other words, AlGaN, INGaN, can be formed as AlGaInN, etc., particularly in the case of the light-emitting layer _{(142) In x (Al y} Ga 1-y) barrier layers of N and _{In x (Al y Ga 1-} y) N well layer It can have a single quantum well structure or a multi-quantum well structure consisting of, and by adjusting the composition ratio of In, Ga, Al, from a long wavelength having an InN (~ 2.2eV) bandgap to a short wavelength having an AlN (~ 6.4eV) bandgap The light emitting diode can be manufactured freely.

The first and second reflective and ohmic layers 11 and 18 may be formed in a single layer or multiple layers. In the present embodiment, a triple layer of Rh / Au / Pt is formed. It is preferable that the light reflectance of the 1st and 2nd reflection and ohmic layers 11 and 18 is 50% or more.

In this structure, light is generated in the light emitting layer 142 and emitted through the sapphire substrate 17.

In the light emitting diode having such a structure, since the first electrode 12 and the second electrode 19 are formed on both upper and lower sides of the chip, the area of the chip can be reduced. Thus, the chip yield per wafer can be greatly improved. In addition, since the via is formed on the sapphire substrate 17 and the second electrode 19 is formed of metal, heat and static electricity are efficiently discharged through the second electrode, thereby greatly improving the reliability of the device. In addition, since the current flows uniformly through the entire area of the chip, driving is possible even at a large current, and high light output can be obtained in a single device. The characteristics of such devices satisfy the high brightness characteristic, which is an essential requirement for the backlight unit of lighting and liquid crystal display devices.

4 is a plan view of a light emitting diode chip having a vertical electrode structure according to a second embodiment of the present invention viewed from a sapphire substrate.

In the second embodiment, as shown in FIG. 4, the planar shape of the second electrode 19 is formed in a form in which branches extend from the center of the circle, thereby promoting diffusion and heat emission of current. Here, the planar shape of the second electrode 19 may be variously modified.

Next, a method of manufacturing a light emitting diode having such a structure will be described.

First, metal organic chemical vapor deposition (MOCVD), liquid epitaxial (LPE), molecular beam epitaxial (MBE), vapor liquid vapor deposition (VPE), etc. are used on the sapphire (Al ₂ O ₃ ) substrate 17. The buffer layer 16, the n-type contact layer 15, the n-type cladding layer 143, the light emitting layer 142, the p-type cladding layer 141, and the p-type contact layer 13 are sequentially stacked.

Next, the first reflective and ohmic layer 11 is formed on the p-type contact layer 13, and the first electrode 12 is formed on the first reflective and ohmic layer 11. Here, the first reflective and ohmic layer 11 and the first electrode 12 such as Rh / Au / Pt / Au may have one or more electron beam (E-Beam) deposition, thermal evaporation, sputtering, or the like. To form. After depositing the first electrode 12, the first electrode 12 and the first electrode may be heat-treated at a temperature of 300 ° C to 600 ° C (preferably about 400 ° C to 500 ° C) in a furnace of nitrogen atmosphere. By forming an ohmic contact between the reflective and ohmic layers 11, the contact resistance with the semiconductor layer is lowered.

Subsequently, any one of insulating substrates such as sapphire substrates, semiconductor substrates such as Si, GaAs, InP, InAs, conductive oxide film substrates such as indium tin oxide (ITO), ZrB, ZnO, and the like is formed on the surface of the first electrode 12. (Not shown). It is preferable to use a wax as an adhesive so that the secondary substrate can be easily separated, and in some cases, a eutectic metal such as Au, Au / Sn, and Pd / In having a low melting temperature may be used as the adhesive layer. . At this time, the attached substrate becomes a part of the chip and is not removed. At this time, almost all or part of the sapphire substrate 17 is etched and removed to expose the buffer layer.

If all of the sapphire substrate 17 is removed, the auxiliary substrate is used as a passage of the support and current flow of the chip without removing the auxiliary substrate. In this case, since the auxiliary substrate must be able to conduct electricity, p-type doped semiconductor substrates such as Si, GaAs, InP, InAs, conductive conductive films such as ITO, ZrB, ZnO, CuW, Mo, Au, Al, Au, etc. It is formed by including any one or more of the metal, and firmly bonded using a eutectic metal such as Au, AuSn, InPd when bonding the substrate. At this time, the adhesion is performed for 3 to 20 minutes at a pressure of 3MP (mega pascal) at a temperature of about 300 ℃ _rms .

Next, in order to protect the semiconductor surface during wet or dry etching, 1um of a protective film such as SiNx and SiO _{2 is} deposited, and then the sapphire substrate 17 is wrapped and scraped off, and the wrapped surface is mirror-polished to make it smooth. The lapping of the sapphire substrate 17 is performed by chemical mechanical polishing (CMP), ICP / RIE dry etching, mechanical polishing using alumina (Al2O3) powder or sulfuric acid (H2SO4), phosphoric acid (H3PO4) and aluetch (4H3PO4 +). 4CH3COOH + HNO3 + H2O) and the mixed solution by any one or a combination thereof are performed by wet etching using as an etching solution.

At this time, the thickness of the sapphire substrate 17 is preferably as thin as possible. However, if the thickness is too thin, the substrate 17 may be wheely and difficult to handle. Therefore, the sapphire substrate 17 is preferably about 40um to 300um (preferably 50um to 70um). Do. In addition, the roughness of the surface of the mirror-polished sapphire substrate 17 should be 1 um or less. This is because the roughness of the surface of the sapphire substrate 17 is transferred to the n-type contact layer 15 as it is during the etching of the sapphire substrate 17 and the buffer layer 16, thereby damaging the layer structure of the light emitting diode.

After mirror polishing, a protective film such as SiNx, SiO _2, etc. is deposited on the surface of the sapphire substrate 17, and an etching mask for forming irregularities is formed by photolithography, and then the sapphire substrate 17 is etched to form irregularities. In this case, a portion of the via is formed to leave a protective layer to protect the mirror surface of the via when the sapphire substrate 17 is subsequently etched.

The uneven object is formed by removing the protective film on the surface of the sapphire, separating the auxiliary substrate, and depositing silicon oxide on the surface of the first electrode 12 and the surface of the sapphire substrate 17, or epoxy or BCB (Benzo Cyclo Butin). It is applied to form a protective film, and the auxiliary substrate is attached again.

Subsequently, the protective film formed on the surface of the sapphire substrate 17 is photo-etched to expose a portion of the sapphire substrate 17 on which vias are to be formed. At this time, the etching of the protective film is performed using Reactive Ion Etching (RIE) or using a buffer oxide echant (BOE) solution.

The wet etching characteristics of the sapphire base substrate 17 may be utilized to form a scribing line or cleve line of the device during via formation. In other words, the cyer substrate is oriented in wet etching. Although not shown as an example of illustration, most of the sapphire-based substrate used in the growth of nitride-based semiconductor thin film is a (0001) plane, and when wet etching, the etching plane has an inclined plane of about 40 degrees from the bottom surface. This is because the (0001) plane and the etched facet have different etching speeds. In other words, the etching depth depends on the line width or the open area, and especially when etching to a certain depth, the etched cross section has a V-grooved shape, which forms a scribing line with any diamond pen. You can make everything clean. The scribing line is sufficient to have a 1um line width, and the scribing line is automatically formed to stop the etching at a certain depth during the via etching, so that the scribing line for separating the substrate 17 into individual chips without any additional process is required. Can be formed. The method proposed in the present invention is a combination of one or more of a wet or dry method to form a fine scribing line at the place where the device is to be separated, thereby easily separating the device, and to clean the cut surface. You can make a mirror.

Next, the sapphire substrate 17 is ICP / RIE or RIE to form vias to a predetermined depth, followed by sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ) and aluetch (4H _3). The sapphire substrate 17 is etched by immersion in a mixed solution by any one of PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) or a combination thereof to complete the via. As such, the application of dry and wet together is intended to prevent excessive increase in the horizontal cross-sectional area ratio of the vias. That is, the dry etching maintains a substantially constant horizontal cross-sectional area to the predetermined depth of the via, and the wet etching is performed so that the side surface of the via has a constant slope below. Preferably, the ratio of the cross-sectional area between the bottom of the via and the via is preferably about 0.9, but the cross-sectional area ratio may be reversed in fabricating the device.

Next, dry etching the buffer layer 16 using ICP / RIE or RIE techniques to form vias exposing the n-type contact layer 15.

At this time, the wet etching of the sapphire substrate 17 proceeds in the following manner.

The etching rate of the sapphire substrate 17 by the etching solution is measured and immersed in the etching solution for a time to etch sapphire having a thickness corresponding to 120% of the sapphire substrate 17. The etching solution used herein exhibits an etching rate of 1/10 or less with respect to the sapphire substrate 17 with respect to the buffer layer 16. That is, the etching selectivity of the buffer layer 16 with respect to the sapphire substrate 17 is 10 or more. Therefore, even if the etching process is performed for a time remaining even after the sapphire substrate 17 is completely etched, since the etching speed of the buffer layer 16 is slow, there is no fear of damaging the underlying layer. On the other hand, it is preferable to maintain the temperature of the etching solution at 30 ℃ or more in order to shorten the etching time. Heating for maintaining the temperature of the etching solution above 30 ℃ may be a direct heating method to put the solution on the heater or to contact the heater directly to the solution and indirect heating method using light absorption.

ICP / RIE technology may be used to etch the sapphire substrate 17. In order to quickly etch the sapphire substrate 17, it is desirable to increase the ICP and RIE power as much as possible, but care must be taken because it may damage the epi layer.

5 is a photograph of the surface of the sapphire substrate after forming a specific pattern on the sapphire substrate by the wet etching method and then etching the sapphire substrate by the wet etching method.

5, it can be seen that the etched slope and the surface of the substrate 17 are very clean. The sapphire substrate 17 was etched at 22.4um for 20 minutes, resulting in an etching rate of 1.1um / min. This etching rate is a remarkable result, and considering the mass production, there is no problem at all, and since wet etching is not limited by the productivity of the equipment, it can be said that there are many advantages in terms of mass production. When the present invention is applied to mass production, an important factor is to secure process conditions for increasing the etching selectivity between the sapphire substrate 17 and the buffer layer 16, which is a nitride semiconductor, and particularly, the sapphire etching of the buffer layer 16. It is effective to use as an etch stop layer. As the buffer layer 16, an In _x (Ga _y Al _1-y ) N (x> = 0, y> = 0) series may be used. Preferably, it is effective to increase the composition ratio of Al.

However, if necessary, before the buffer layer 16 is formed on the sapphire substrate 17, a protective film such as SiO ₂ or SiNx is locally formed only on a portion of the sapphire substrate 17 on which vias are to be formed, thereby separately forming an etch stop layer. You may.

6 is a graph showing etching rates of sapphire and GaN by ICP / RIE dry etching.

As can be seen in FIG. 6, the sapphire and nitride semiconductors have increased etching speeds as the ICP and RIE powers are increased, but the etching ratio between the sapphire and nitride semiconductors is decreasing. These results indicate that when the sapphire substrate 17 is etched by the ICP / RIE technique, which is a dry etching technique, it is difficult to stop the etching in the buffer layer 16 made of nitride-based semiconductor. In order to stop the etching in the buffer layer 16, an optical analysis is performed. Techniques such as methods or residual gas analysis methods should be used. Even with these analytical techniques, the probability of success is low. However, in the wet etching method, the buffer layer 16 may be used as an etch stop layer to secure a process margin, which is a requirement for mass production.

7 is a graph showing the etching rate when wet etching sapphire and GaN with a mixture solution of sulfuric acid and phosphoric acid.

As can be seen in Figure 7, the sapphire etching selectivity of the nitride-based semiconductor of the solution of sulfuric acid and phosphoric acid may be 50 or more. These results indicate that the buffer layer 16 can be effectively used as an etch stop layer of the sapphire substrate 17, and an etching selectivity of 20 or more was obtained even at a high temperature of 100C. In particular, since the etching rate of sapphire is 1um / min or more at a specific temperature, considering the production cost, productivity, process stabilization it can be seen that the method presented in the present invention is more advantageous than any conventional method.

However, the wet etching technique alone seems to have limitations in making vertical electrode light emitting diodes stable. As shown in FIG. 7, since the nitride semiconductor is hardly etched when the sapphire substrate 17 is etched with a mixture of sulfuric acid and phosphoric acid, it is not easy to uniformly etch the buffer layer 16 only by wet etching. Therefore, the process of etching the undoped nitride semiconductor buffer layer 16 uniformly and stably stopping the etching in the nitride semiconductor n-type contact layer 15 effectively utilizes dry etching techniques such as ICP / RIE or RIE. It is preferable. That is, by removing the sapphire substrate 17 and using a wet etching technique and a dry etching technique as a method for manufacturing a vertical electrode type nitride semiconductor light emitting device, the sapphire substrate is removed more stably and uniformly, and the nitride semiconductor buffer layer is used. By etching 16 to expose the n-type contact layer 15 uniformly, the second electrode 19 can be formed more stably.

8 is a surface photograph of a buffer layer after removing a sapphire substrate by a wet etching method.

As can be seen in FIG. 8, even after the sapphire substrate 17 was removed, almost no crack or damage of the thin film due to stress was found and the surface was also very clean.

9 is a voltage-current characteristic curve of a nitride based semiconductor layer after removing the sapphire substrate by a wet etching method.

As can be seen in Figure 9, it can be seen that no current flows until the sapphire substrate 17 is removed, and 1 pA flows at 1V after the sapphire substrate 17 is removed, but ICP / RIE or RIE After removing the nitride semiconductor buffer layer 16 by the technique, it can be seen that the current rapidly increased to 40 pA. At this time, any one of BCL ₃ , Cl ₂ , HBr, Ar, or a mixed gas thereof is used as an etching gas of ICP / RIE or RIE.

As a result, it can be seen that the wet and dry etching techniques effectively etch the sapphire substrate 17 and the nitride semiconductor buffer layer 16 to expose the n-type nitride semiconductor contact layer 15. This characteristic is a very important result that the etching process can be effectively monitored by measuring the electrical properties of the exposed surface using a probe station at each process step.

Next, any one of Ti, Al, Rd, Pt, Ta, Ni, Cr, Au, Ti / Al, Ag, or these metals is a conductive material having excellent light reflectivity and an ohmic contact on the sapphire substrate 17. The alloy and the like are deposited and photo-etched to form the second reflection and ohmic layer 18 and the second electrode 19. After depositing the second electrode 19, the second electrode 19 and the first electrode are heat-treated at a temperature of 300 ° C to 600 ° C (preferably about 400 ° C to 500 ° C) in a furnace of nitrogen atmosphere. By forming an ohmic contact between the reflective and ohmic layers 18, the contact resistance with the semiconductor layer is lowered.

In the present invention, since the sapphire substrate is removed using back grinding and dry or wet etching, productivity is greatly improved, and thermal damage that an epitaxial layer can receive in the case of a laser lift-off method can be prevented. In addition, by utilizing the etching selectivity between the sapphire substrate and the nitride semiconductor can be easily improved the reproducibility of the process, and the standardized process is possible to facilitate mass production.

FIG. 10 is a cross-sectional view of an embodiment of extracting light from a base substrate as a cross-sectional view of a light emitting diode having a vertical electrode structure according to a third embodiment of the present invention, and FIG. 11 is a vertical view according to a third embodiment of the present invention. 12 is a cross-sectional view of a light emitting diode chip having an electrode structure, and FIG. 12 is a plan view of a light emitting diode chip having a vertical electrode structure according to a third embodiment of the present invention as viewed from a sapphire substrate.

In the third embodiment of the present invention, in order to prevent the nitride-based semiconductor thin films 15, 141, 142, 143 and 11 from being damaged due to the pressure applied when bonding the wire 24 to the second electrode 19. The second reflection and ohmic layer 18 and the second electrode 19 are extended to the outside of the via to form a pad on the sapphire substrate 17. The shape or position of the pad of the second electrode 19 may be variously modified, and the shape as shown in FIG. 4 may also be applied.

On the other hand, irregularities may be formed on the surface of the sapphire substrate 17 to concentrate light emitted from the sapphire substrate 17 in the normal direction. Here, the unit length of the recessed portion and the convex portion is about 1 / 4n of the wavelength of light emitted by the light emitting diode (n is the refractive index of the medium. Therefore, the refractive index of the sapphire in the case of the convex portion, and the refractive index of air in the case of the recessed portion). It is desirable to have photonic crystal characteristics.

13 is a cross-sectional view of an embodiment in which light is extracted from a base substrate as a cross-sectional view of a light emitting diode chip having a vertical electrode structure according to a fourth embodiment of the present invention.

In the fourth embodiment, instead of the second reflective and ohmic layers, transparent conductors such as ITO, ZrB, ZnO, InO, SnO, etc. are formed as the ohmic layer 23 to cover the surface of the sapphire substrate 17 by a predetermined area. The second electrode 19 is narrowly formed only around the via. This is to narrow the area covered by the second electrode 19 as an opaque film as much as possible to widen the exit of the light. The wire may be bonded over the ohmic layer 23 and the second electrode 19. In order to secure an area for wire bonding, the ohmic layer 23 covers the surface of the sapphire substrate 17 by a predetermined area or more.

FIG. 14 is a cross-sectional view of an embodiment of a light emitting diode having a vertical electrode structure according to a fifth embodiment of the present invention for extraction from a nitride based semiconductor surface, and FIG. 15 is a vertical view of a light emitting diode according to a fifth embodiment of the present invention. FIG. 16 is a cross-sectional view of a light emitting diode chip having an electrode structure, and FIG. 16 is a plan view of a light emitting diode chip having a vertical electrode structure according to a fifth embodiment of the present invention as viewed from a first electrode side.

The chip of the light emitting diode according to the fifth embodiment of the present invention has the following structure.

The first electrode 25 is made of a metal made of any one of NiO, NiAu, Ti, Ni, Au, Pd, Rh, Pt, Al, Cr or deposited an alloy including two or more thereof, and a transparent conductor It may be deposited thinly to have characteristics, or may be heat treated in an oxygen atmosphere. When NiO or NiAu is used, an ohmic thin film having a transparent conductor property can be obtained by depositing thinly on almost the entire surface and heat-treating at a temperature of 100 ° C. or higher. In addition, the first electrode 25 may be formed of a transparent conductive material such as ITO, ZrB, ZnO, InO, SnO, In _x (Ga _y Al _1-y ) N, or the like.

In some cases, the first electrode 25 may be used as a support, and all of the sapphire substrate 17 may be removed. In particular, when In _x (Ga _y Al _1-y ) N is used as the first electrode 25, the In _x (Ga _y Al _1-y ) N layer may be 10 μm to 200 μm (VPE) using a vapor phase epitacsy (VPE) method. Preferably 50um or more) to act as a support instead of the sapphire substrate 17. At this time, it is also possible to leave the sapphire substrate 17 thin.

The first electrode pad 26 for bonding the wire 24 is formed on the first electrode 25. At this time, a through hole is formed in the first electrode 25 in the portion where the first electrode pad 26 is located, and an insulating film 27 such as SiNx, SiO ₂ , ZrO, etc. is formed in the through hole. Therefore, the portion immediately below the first electrode pad 26 is insulated from the p-type contact layer 13. This is to prevent current from concentrating directly under the first electrode pad 26.

Meanwhile, the through hole of the first electrode 25 positioned below the first electrode pad 26 may not be formed. When not forming the through hole, the first electrode pad 26 is formed by using metals such as Al, Cr, Ti, etc., which have Schottky characteristics, to prevent current from concentrating directly under the first electrode pad 26. It is for.

In addition, the first electrode pads 26 are preferably formed at positions not overlapping the vias. This is to prevent the nitride-based semiconductor thin film from being damaged at the time of bonding the wire 24.

In the foregoing first to fourth embodiments, the first reflective and ohmic layers 11 formed are omitted. This is because the first electrode 25 made of the transparent conductor forms an ohmic contact with the p-type contact layer 13.

On the lower surface of the sapphire substrate 17, a second reflection and ohmic layer 18 and a second electrode 19 are formed on the entire surface of the sapphire substrate 17 including the vias. The second reflective and ohmic layer 18 and the second electrode 19 may be formed as a single layer which is not separated or may be formed as a triple layer or more. Al, Ti / Al, Ti / Al / Au, Rh / Au, Pd / Au, Al / Pt / Au, and the like may be used as the second reflection and ohmic layer 18 and the second electrode 19.

The first electrode 19 may be formed thick in order to improve heat dissipation efficiency when the chip is mounted on the lead frame 20 or the PCB. Preferably, the first electrode 19 may be formed by electroplating Au, Cu, Ni, Al, or the like. Can be.

The method of manufacturing a light emitting diode chip having such a structure is almost similar to the method according to the first embodiment described above. However, the first electrode 25 is formed of a transparent conductive material, and in the last step, the first electrode 25 is photo-etched to expose a portion of the p-type contact layer, and the first electrode pad 26 is formed. The difference is that it goes further.

17 is a cross-sectional view of a light emitting diode chip having a vertical electrode structure according to a sixth embodiment of the present invention, Figure 18 is a first electrode of a light emitting diode chip having a vertical electrode structure according to a fifth embodiment of the present invention It is a plan view seen from the side.

In the sixth embodiment, the first electrode 28 is formed using an ohmic metal, and is directly formed on the p-type contact layer 18 in a network structure so that light can pass therethrough, and the bottom surface of the sapphire substrate 17. The fact that the edges are etched and chamfered is a distinguishing feature from the fifth embodiment. A first electrode pad 29 is formed on the first electrode 28.

In this structure, since the bottom edge of the sapphire substrate 17 is chamfered, the reflection and ohmic layer 18 is bent along the chamfered surface. This shape is effective for reflecting light leaking to the lower side to be emitted to the side toward the first electrode 28. These chamfered edges help the light exit to the side of the chip even when the second electrode 19 and the ohmic layer 18 transmit light. Light emitted to the side of the chip is reflected by the lead frame and emitted upward.

On the other hand, the method of forming the chamfer on the sapphire substrate 17 is to etch the boundary portions between the individual chips at the time of etching for the via formation. In this case, the opening width of the passivation layer used as the etch mask is narrower than the portion where the via is to be formed at the chip-to-chip boundary so that the sapphire substrate 17 is not separated from each chip.

The present invention can be applied to all nitride based semiconductors of Inx (GayAl1-y) N series grown on a sapphire base substrate as well as a blue nitride based light emitting device having a wavelength of 470 nm. When fabricating the device, since the GaN layer used as the buffer layer can be removed, the device can be very useful for devices emitting light in the ultraviolet region of 365 nm or less, which is the GaN bandgap wavelength. It is a key technology in the LED lighting field that enables the production of high brightness / high performance nitride semiconductor light emitting devices by improving reliability and brightness, reducing device size, and improving productivity and device performance.

Although the present invention has been described with reference to the embodiments shown in the accompanying drawings, this is merely exemplary, and those skilled in the art may understand that various modifications and equivalent other embodiments are possible. There will be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

As described above, in the light emitting diode according to the embodiment of the present invention, two electrodes are formed on both upper and lower sides of the chip, thereby reducing the area of the chip. Thus, the chip yield per wafer can be improved. In addition, since the via is formed on the sapphire substrate and the second electrode is formed of metal, the vertical electrode type nitride-based semiconductor light emitting diode having efficient heat emission and static discharge through the second electrode can be easily manufactured. . In addition, since the current flows uniformly through the entire area of the chip, driving is possible even at a large current. Therefore, high light output can be obtained in a single device.

In addition, in the present invention, since the sapphire substrate is removed using back grinding and dry or wet etching, productivity is greatly improved, and thermal damage that an epitaxial layer can receive in the case of a laser lift-off method can be prevented. In addition, by using an etching selectivity between the sapphire substrate and the nitride semiconductor, it is possible to easily improve the reproducibility of the process, and the standardized process is possible to facilitate mass production.

Claims (66)

A base substrate having vias, A first conductive type contact layer formed on the base substrate, A first conductivity type clad layer formed on the first conductivity type contact layer, A light emitting layer formed on the first conductive cladding layer, A second conductive clad layer formed on the light emitting layer, A second conductivity type contact layer formed on the second conductivity type clad layer, A first electrode formed on the second conductivity type contact layer, A second electrode connected to the first conductive type contact layer through the via Light emitting diode comprising a. In claim 1, A buffer layer formed between the base substrate and the first conductive type contact layer and having a via overlapping at least a portion of a via of the base substrate; A first reflective and ohmic layer formed between the first electrode and the second conductive contact layer, A second reflective and ohmic layer formed between the second electrode and the first conductive contact layer Light emitting diodes further comprising. In claim 2, And the second electrode extends out of the via to form a pad over the base substrate. In claim 2, The first electrode is composed of a single layer or a plurality of layers including at least one of Ni, Cr, Rh, Pd, Au, Ti, Pt, Au, Ta, Al, and the second electrode is Ti, Al, Rd A light emitting diode comprising a single layer or a plurality of layers comprising at least one of Pt, Ta, Ni, Cr, Au, and Ag. In claim 1, And the planar shape has a plurality of branches extending from a center point when the second electrode is viewed from above the base substrate. The method according to any one of claims 1 to 5, The buffer layer includes In _x (Ga _y Al _1-y ) N. In claim 6, The composition ratio of In _x (Ga _y Al _1-y ) N is x ≧ 0, y ≧ 0. The method according to any one of claims 1 to 5, The base substrate is a light emitting diode made of sapphire. The method according to any one of claims 1 to 5, The thickness of the base substrate is 40um to 300um and the light emitting diode is mirror-polished surface of the thin film is not formed. In claim 9, The roughness of the mirror-polished surface of the said base substrate is 1 micrometer or less. The method according to any one of claims 1 to 5, The first conductivity type is n-type, the second conductivity type p-type light emitting diode. The method according to any one of claims 1 to 5, The via of the base substrate and the buffer layer is narrower in width as the first conductive type contact layer gets closer. The method according to any one of claims 1 to 5, A light emitting diode in which unevenness is formed on a surface on which the thin film of the base substrate is not formed. In claim 13, In the concave-convex, the unit length of the concave portion and the convex portion is 1 / 4n (n is the refractive index of the medium) of the wavelength of light emitted by the light emitting diode. The method according to any one of claims 1 to 5, The first electrode is bonded through the conductive paste, the second electrode further comprises a lead frame electrically connected via wire bonding. In claim 1, A reflective and ohmic layer formed between the first electrode and the second conductive contact layer, And a transparent conductive layer formed between the second electrode and the first conductive type contact layer and extending outside the via to cover the surface of the base substrate by a predetermined area or more. The method of claim 16, The transparent conductive layer includes at least one of ITO, ZrB, ZnO, InO, SnO, In _x , (Ga _y Al _1-y ) N. In claim 1, The first electrode is a light emitting diode formed of a transparent conductive material. The method of claim 18, And a reflective and ohmic layer formed between the second electrode and the first conductive contact layer and covering the inner surface of the via as well as the underlying substrate surface. The method of claim 18, The first electrode includes at least one of ITO, ZrB, ZnO, InO, SnO, and In _x (Ga _y Al _1-y ) N. The method of claim 20, The light emitting diode having a thickness of 10 μm to 200 μm when the first electrode is formed of In _x (Ga _y Al _1-y ) N. The method according to any one of claims 18 to 21, The buffer layer includes In _x (Ga _y Al _1-y ) N. The method according to any one of claims 18 to 21, The light emitting diode further comprising a first electrode pad formed on the first electrode. The method of claim 23, The lower portion of the first electrode pad, the first electrode is partially removed, the light emitting diode further comprises an insulating film formed on the portion where the first electrode is removed. The method of claim 23, The first electrode pad is formed at a position not overlapping with the via. The method according to any one of claims 18 to 21, The second electrode is bonded through a conductive paste, the first electrode further comprises a lead frame electrically connected through wire bonding The method of claim 18, The first electrode is made of NiO, Ni / Au. In claim 1, The first electrode is formed of an ohmic metal and has a network structure to allow light to pass therethrough. In claim 1, The light emitting diode of which the edge of the surface opposite to the surface in which the buffer layer of the said base substrate is formed is chamfered. In claim 1, The first and second conductivity type contact layer, the first and second cladding layer and the light emitting layer is made of In _x (Ga _y Al _1-y ) N. Sequentially forming a buffer layer, a first conductive contact layer, a first conductive clad layer, a light emitting layer, a second conductive clad layer, a second conductive contact layer, and a first electrode on the base substrate; Lapping and polishing the base substrate, Forming a protective film on the surface of the first electrode and the surface of the base substrate; Photo-etching the passivation layer on the base substrate to partially expose the surface of the base substrate, Etching via the exposed portion of the base substrate and a buffer layer below the via to form a via; Forming a second electrode connected to the first conductive type contact layer through the via Method of manufacturing a light emitting diode comprising a. The method of claim 31, And laminating the first electrode to a heat treatment at a temperature between 500 ° C. and 700 ° C. in a furnace containing nitrogen or oxygen. The method of claim 31, Attaching an auxiliary substrate prior to lapping and polishing the base substrate. The method of claim 33, The auxiliary substrate may be an insulating substrate such as sapphire, glass, or quartz, a semiconductor substrate such as Si, GaAs, InP, or InAs, a conductive oxide film such as indium tin oxide (ITO), ZrB, or ZnO, CuW, Mo, Au, Al, Au The manufacturing method of the light emitting diode which is any one of metal substrates, such as these. The method of claim 33, The method of manufacturing the light emitting diode is performed by attaching the auxiliary substrate using wax as an adhesive. The method of claim 33, Attaching the auxiliary substrate is a manufacturing method of a light emitting diode using a eutectic metal containing at least one of Au, AuSn, InPd as an adhesive. The method of claim 31, In the lapping and polishing of the base substrate, the surface of the base substrate is mirror polished to have a roughness of 1 μm or less. The method of claim 31, In the step of photo-etching the protective film on the base substrate using a wet etching method using a BOE solution as an etchant or a RIE dry etching method of manufacturing a light emitting diode. The method of claim 31, In the forming of the via, any one of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), and aloe etch (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) or The manufacturing method of the light emitting diode which uses the mixed solution by these combination as an etching liquid. The method of claim 39, The etchant is used in the state of being heated to a temperature of 30 ℃ or more manufacturing method of the light emitting diode. The method of claim 31, In the forming of the via, any one of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), and aloe etch (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) or A method of manufacturing a light emitting diode comprising wet etching using a mixed solution of these as an etching solution and dry etching with ICP / RIE or RIE. 43. The method of claim 41 wherein The wet etching is used to etch the base substrate, and the dry etching is used to etch the buffer layer. The method of claim 42, And forming the buffer layer with In _x (Ga _y Al _1-y ) N (x> = 0, y> = 0) to use as the etch stop layer of the wet etching. 43. The method of claim 41 wherein And monitoring the electrical properties in the via with a probe to determine whether the first conductivity type contact layer is exposed. 43. The method of claim 41 wherein The dry etching method of manufacturing a light emitting diode using at least one of BCL ₃ , Cl ₂ , HBr, Ar as an etching gas. 43. The method of claim 41 wherein The method of manufacturing a light emitting diode in which the dry etching and the wet etching are performed in the etching of the base substrate. The method of claim 31, A first ohmic layer is further formed on the second conductive type contact layer before the first electrode is stacked. And forming a second ohmic layer in contact with the first conductive type contact layer prior to forming the second electrode. The method of claim 47, The first and second ohmic layer is a method of manufacturing a light emitting diode having a light reflection characteristic. The method of claim 47, The first ohmic layer has a light reflection characteristic, and the second ohmic layer is made of a transparent conductive material. The method of claim 31, In the forming of the first electrode, forming a through hole exposing the second conductive contact layer and forming a first electrode pad contacting the second conductive contact layer on the first electrode. And a first electrode formed of a light transmissive conductive material. The method of claim 31, At least one of the first electrode and the second electrode is formed by electroplating at least one metal of Ti, Au, Cu, Ni, Al, and Ag. The method of claim 31, The first electrode or the second electrode is formed by depositing NiO, NiAu, heat treatment at a temperature of 100 ℃ or more in an atmosphere containing oxygen. The method of claim 31, The first electrode is formed by growing In _x (Ga _y Al _1-y ) N to a thickness of 10um ~ 200um by VPE method. The method of claim 31, The method of manufacturing a light emitting diode to make the thickness of the base substrate 50um ~ 70um in the step of lapping and polishing the base substrate. The method of claim 31, The lapping and polishing of the base substrate may be any one of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), and aluene (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) or The manufacturing method of the light emitting diode which uses the wet etching which uses the mixed solution by these combination as an etching liquid. The method of claim 31, The method may further include separating the base substrate by individual chips, and wherein the separating the base substrate by individual chips is performed using at least one of wet etching and dry etching. The method of claim 56, Separating the base substrate by individual chips may be any one of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O). Or the manufacturing method of the light emitting diode which advances using the wet etching which uses the mixed solution by these combination as an etching liquid. The method of claim 31, And forming a via by etching the exposed portion of the base substrate and a buffer layer below the substrate to form cleavage lines for separating the base substrate by individual chips. The method of claim 31, And forming an etch stop layer on a portion of the base substrate where the via is to be formed before forming the buffer layer on the base substrate. Preparing a sapphire substrate on which a nitride based semiconductor thin film is grown, Mixing the sapphire substrate by any one or a combination of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ) and aluene (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) Method of etching a sapphire substrate comprising the step of wet etching in solution. The method of claim 60, Dry etching the sapphire substrate by ICP / RIE, RIE technology. 62. The method of claim 61, And etching the dry etch prior to the wet etching. 63. The word of any of claims 60-62, wherein During the wet etching, any one of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) or a combination thereof Etching method of the sapphire substrate in which the mixed solution is heated to a temperature of 30 ℃ or more. 66. The method of claim 63, The heating method of the sapphire substrate etching method of the indirect heating method using light absorption. Sequentially forming a buffer layer, a first conductive contact layer, a first conductive clad layer, a light emitting layer, a second conductive clad layer, a second conductive contact layer, and a first electrode on the base substrate; Attaching an auxiliary substrate to the base substrate; Polishing or etching the base substrate to remove some or all of the thickness of the base substrate, Forming a second electrode electrically connected to the first conductivity type contact layer Method of manufacturing a light emitting diode comprising a. 66. The method of claim 65, The thickness of the base substrate after polishing or etching is a method of manufacturing a light emitting diode.