KR20050010258A - Method of forming a gate in a semiconductor device - Google Patents
Method of forming a gate in a semiconductor deviceInfo
- Publication number
- KR20050010258A KR20050010258A KR1020030049292A KR20030049292A KR20050010258A KR 20050010258 A KR20050010258 A KR 20050010258A KR 1020030049292 A KR1020030049292 A KR 1020030049292A KR 20030049292 A KR20030049292 A KR 20030049292A KR 20050010258 A KR20050010258 A KR 20050010258A
- Authority
- KR
- South Korea
- Prior art keywords
- tungsten silicide
- film
- gate
- oxide film
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 42
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 239000001307 helium Substances 0.000 claims description 5
- 229910052734 helium Inorganic materials 0.000 claims description 5
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 101710162453 Replication factor A Proteins 0.000 claims 1
- 102100035729 Replication protein A 70 kDa DNA-binding subunit Human genes 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 12
- 238000007254 oxidation reaction Methods 0.000 abstract description 12
- 230000002159 abnormal effect Effects 0.000 abstract description 11
- 238000005240 physical vapour deposition Methods 0.000 description 22
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- -1 silicon ions Chemical class 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 150000001450 anions Chemical class 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Abstract
Description
본 발명은 반도체 소자의 게이트 형성 방법에 관한 것으로, 특히 폴리실리콘막, PVD 텅스텐 실리사이드막 및 산화막의 적층 게이트를 형성하기 위해 기존의CVD TEOS 산화막 대신에 PETEOS 산화막을 형성하여 PVD 텅스텐 실리사이드막의 이상 산화를 억제할 수 있고, 이로 인해 게이트 패터닝을 위한 식각 공정에서 폴리실리콘 잔류물의 발생을 억제할 수 있어 소자의 수율을 향상시킬 수 있는 반도체 소자의 게이트 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate of a semiconductor device, and in particular, to form a multilayer gate of a polysilicon film, a PVD tungsten silicide film, and an oxide film, a PETEOS oxide film is formed in place of a conventional CVD TEOS oxide film to prevent abnormal oxidation of the PVD tungsten silicide film. The present invention relates to a method for forming a gate of a semiconductor device, which can be suppressed, thereby suppressing generation of polysilicon residues in an etching process for gate patterning, thereby improving device yield.
폴리실리콘막, 텅스텐 실리사이드막 및 산화막을 적층하여 형성하는 3층 스택 게이트는 널리 사용되는 구조중의 하나이다. 여기서, 텅스텐 실리사이드막은 PVD 방법으로 형성하고, 산화막은 750℃의 고온에서 CVD TEOS 산화막으로 형성한다. PVD 텅스텐 실리사이드막은 게이트의 Qbd 특성이 CVD 텅스텐 실리사이드막에 비해 우수하다는 장점이 있어 선호되는 막이다. Qbd 특성은 플래쉬 관련 제품에서 데이터 리텐션(data retention) 특성과 직결되는 특성이라 특히 중요시된다. 그런데, 비정질(amorphous) 결정 구조의 PVD 텅스텐 실리사이드막은 헥사고날(hexagonal) 결정 구조의 CVD 텅스텐 실리사이드막에 비해 막질이 매우 약하기 때문에 외부 열공정에 의해 쉽게 산화되는 성질이 있다. 또한, 산화 막질도 매우 불균일하고 불안하며 비정상적으로 과다 산화되는데, 이를 이상 산화라고 한다. 이러한 PVD 텅스텐 실리사이드막의 성질 때문에 750℃의 고온에서 실시하는 CVD TEOS 산화막의 증착은 특히 웨이퍼 중앙부를 따라 PVD 텅스텐 실리사이드막에 심한 이상 산화 현상을 유발한다. 이러한 이상 산화 현상은 산소가 외부 열 에너지에 의해 비정상적으로 과다하게 산화되고, 텅스텐 실리사이드막으로부터 다량의 실리콘을 석출하여 텅스텐 리치를 유발할 뿐만 아니라 텅스텐 실리사이드막 내부에부분적으로 산화막을 형성하게 된다. 이렇게 부분적으로 불균일하게 발생되는 이상 산화 현상에 의해 텅스텐 실리사이드막과 폴리실리콘막의 식각이 방해됨으로써 폴리실리콘 잔류물이 발생된다. 이는 게이트 프로파일에 악영향을 미치고, 결과적으로 소자의 수율을 저하시키게 된다.The three-layer stack gate formed by laminating a polysilicon film, a tungsten silicide film and an oxide film is one of widely used structures. Here, the tungsten silicide film is formed by the PVD method, and the oxide film is formed by the CVD TEOS oxide film at a high temperature of 750 ° C. The PVD tungsten silicide film is a preferred film because the Qbd property of the gate is superior to the CVD tungsten silicide film. The Qbd feature is particularly important because it is directly related to the data retention feature in flash-related products. However, since the PVD tungsten silicide film having an amorphous crystal structure is very weak compared to the CVD tungsten silicide film having a hexagonal crystal structure, the PVD tungsten silicide film is easily oxidized by an external thermal process. In addition, the oxide film is also very heterogeneous, unstable and abnormally overoxidized, which is called abnormal oxidation. Due to the properties of the PVD tungsten silicide film, the deposition of the CVD TEOS oxide film performed at a high temperature of 750 ° C. causes severe abnormal oxidation especially on the PVD tungsten silicide film along the wafer center. This abnormal oxidation phenomenon causes oxygen to be abnormally excessively oxidized by external thermal energy, precipitates a large amount of silicon from the tungsten silicide film, causes tungsten rich, and partially forms an oxide film inside the tungsten silicide film. Due to this partial non-uniform oxidation phenomenon, the etching of the tungsten silicide film and the polysilicon film is disturbed, thereby generating polysilicon residues. This adversely affects the gate profile, resulting in lowered device yield.
본 발명의 목적은 PVD 텅스텐 실리사이드막의 이상 산화를 방지할 수 있는 반도체 소자의 게이트 형성 방법을 제공하는데 있다.An object of the present invention is to provide a method for forming a gate of a semiconductor device capable of preventing abnormal oxidation of the PVD tungsten silicide film.
본 발명의 다른 목적은 PVD 텅스텐 실리사이드막 및 산화막의 적층 구조를 형성할 때 PVD 텅스텐 실리사이드막의 이상 산화를 방지할 수 있는 반도체 소자의 게이트 형성 방법을 제공하는데 있다.Another object of the present invention is to provide a gate forming method of a semiconductor device capable of preventing abnormal oxidation of a PVD tungsten silicide film when forming a laminated structure of a PVD tungsten silicide film and an oxide film.
PVD 텅스텐 실리사이드막의 이상 산화의 원인은 산소이며, 그 반응을 일으키는 에너지는 후속 CVD TEOS 산화막을 증착하는 공정에서 웨이퍼를 퍼니스에 로딩할 때의 고온 열에너지이다. 이상 산화는 TEOS 산화막을 증착하기 위해 퍼니스에 로딩할 때 텅스텐 실리사이드막이 노출되기 때문에 발생되고, TEOS 산화막을 증착한 후에는 발생되지 않는 것이다.The cause of the abnormal oxidation of the PVD tungsten silicide film is oxygen, and the energy causing the reaction is the high temperature thermal energy when loading the wafer into the furnace in the process of depositing the subsequent CVD TEOS oxide film. Abnormal oxidation occurs because the tungsten silicide film is exposed when loading the furnace to deposit the TEOS oxide film, and does not occur after the TEOS oxide film is deposited.
PVD 텅스텐 실리사이드막의 형성 공정은 500℃의 비교적 저온에서 스퍼터링 방법으로 진행된다. 따라서, 이러한 약한 막의 이상 산화를 방지하기 위해서는 막 형성 온도 조건보다 더 낮은 온도 조건으로 후속 TEOS 산화막의 증착이 진행되어야한다. 즉, 막 형성 에너지보다 큰 에너지가 약한 PVD 텅스텐 실리사이드막에 가해지면 이미 형성된 결합력을 끊을 수 있는 조건이 된다. 이런 측면에서 볼 때, 기존 CVD TEOS 산화막의 증착 온도인 750℃는 적합하지 않다. 따라서, 열 공정이 아닌 플라즈마에 의해 저온에서 진행 가능한 PETEOS 산화막을 적용한다. 기존의 CVD TEOS막의 형성은 TEOS를 열분해하여 증착하기 때문에 매우 고온에서 진행될 수 밖에 없으나 PETEOS 공정은 저온에서 진행할 수 있다.The formation process of PVD tungsten silicide film | membrane progresses by the sputtering method at comparatively low temperature of 500 degreeC. Therefore, in order to prevent abnormal oxidation of such a weak film, deposition of the subsequent TEOS oxide film should be carried out at a temperature lower than the film forming temperature condition. That is, when an energy larger than the film formation energy is applied to the weak PVD tungsten silicide film, it becomes a condition to break the already formed bonding force. In this respect, the deposition temperature of the existing CVD TEOS oxide film 750 ℃ is not suitable. Therefore, the PETEOS oxide film that can proceed at low temperature by plasma rather than a thermal process is applied. The conventional CVD TEOS film is formed by thermally decomposing TEOS, so it can only be performed at a high temperature, but the PETEOS process can be performed at a low temperature.
도 1(a) 및 도 1(b)는 본 발명에 따른 반도체 소자의 게이트 형성 방법을 설명하기 위해 도시한 소자의 단면도.1 (a) and 1 (b) are cross-sectional views of a device for explaining the gate forming method of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 게이트 산화막11 semiconductor substrate 12 gate oxide film
13 : 폴리실리콘막 14 : PVD 텅스텐 실리사이드막13: polysilicon film 14: PVD tungsten silicide film
15 : PETEOS 산화막15: PETEOS oxide film
본 발명에 따른 반도체 소자의 게이트 형성 방법은 반도체 기판 상부에 게이트 산화막, 폴리실리콘막 및 텅스텐 실리사이드막을 형성하는 단계와, 상기 텅스텐 실리사이드막 상부에 PETEOS 산화막을 형성하는 단계와, 상기 PETEOS 산화막, 텅스텐 실리사이드막 및 폴리실리콘막의 소정 영역을 식각하여 게이트를 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.A method of forming a gate of a semiconductor device according to the present invention comprises the steps of forming a gate oxide film, a polysilicon film and a tungsten silicide film on the semiconductor substrate, a PETEOS oxide film formed on the tungsten silicide film, the PETEOS oxide film, tungsten silicide And etching the predetermined regions of the film and the polysilicon film to form a gate.
상기 PETEOS 산화막은 400℃ 정도의 온도를 유지하는 매엽식 챔버 상기 반도체 기판을 로딩한 후 상기 챔버내에 TEOS, 산소 및 헬륨 공급하고, 플라즈마 형성을 위한 적정 압력을 설정한 후 RF 파워를 인가하여 형성하는 것을 특징으로 한다.The PETEOS oxide film is formed by loading TEOS, oxygen, and helium into the chamber after loading the semiconductor substrate to maintain a temperature of about 400 ° C., setting an appropriate pressure for plasma formation, and then applying RF power. It is characterized by.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 설명함으로써 본 발명을 상세히 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시 예는 본발명의 개시가 완전하도록 하며, 이 기술 분야에서 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 또한, 도면상에서 동일 부호는 동일 요소를 지칭한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided to fully inform the scope of the invention. In addition, in the drawings, like reference numerals refer to like elements.
도 1(a) 및 도 1(b)는 본 발명에 따른 반도체 소자의 게이트 형성 방법을 설명하기 위해 도시한 소자의 단면도이다.1 (a) and 1 (b) are cross-sectional views of a device for explaining a method of forming a gate of a semiconductor device according to the present invention.
도 1(a)를 참조하면, 반도체 기판(11) 상부에 게이트 산화막(12), 폴리실리콘막(13) 및 텅스텐 실리사이드막(14)을 형성한 후 그 상부에 PETEOS 산화막(15)을 형성한다. 여기서, 폴리실리콘막(13)은 1000∼1500Å 정도의 두께로 형성한다. 그리고, 텅스텐 실리사이드막(14)은 PVD 방법을 이용하여 1000∼2000Å 정도의 두께로 형성하는데, 500℃의 온도에서 텅스텐 실리사이드 타겟에 아르곤 스퍼터링을 이용하여 형성한다. 또한, PETEOS 산화막을 형성하기 위해 400℃ 정도의 온도를 유지하는 매엽식 챔버내에 TEOS, 산소 및 헬륨 공급하고, 원하는 적정 플라즈마 형성을 위한 적정 압력을 펌프를 통해 설정한 후 RF 파워를 인가한다. 이렇게 하면, 반응 가스인 TEOS와 산소는 다양한 양이온, 음이온, 전자, 중성자들로 해리된다. 이때, 헬륨은 방전 안정화를 위해 공급되는 가스로서, RF 파워에 의해 해리되지 않는다. 해리된 플라즈마중 실리콘 이온과 산소 이온이 결합하여 산화막을 형성하는데, 1000∼2000Å 정도의 두께로 웨이퍼상에 증착되고 나머지는 펌프를 통해 외부로 배출된다.Referring to FIG. 1A, a gate oxide film 12, a polysilicon film 13, and a tungsten silicide film 14 are formed on a semiconductor substrate 11, and then a PETEOS oxide film 15 is formed thereon. . Here, the polysilicon film 13 is formed in the thickness of about 1000-1500 kPa. The tungsten silicide film 14 is formed to a thickness of about 1000 to 2000 GPa using the PVD method, and is formed by argon sputtering on a tungsten silicide target at a temperature of 500 ° C. In addition, TEOS, oxygen, and helium are supplied into a single wafer chamber maintaining a temperature of about 400 ° C. to form a PETEOS oxide film, and RF power is applied after setting an appropriate pressure through a pump to form a desired plasma. In this way, the reaction gases TEOS and oxygen are dissociated into various cations, anions, electrons and neutrons. At this time, helium is a gas supplied for discharge stabilization and is not dissociated by RF power. In the dissociated plasma, silicon ions and oxygen ions combine to form an oxide film, which is deposited on the wafer to a thickness of about 1000 to 2000 microns and the rest is discharged to the outside through a pump.
상기와 같이 매엽식 챔버를 이용하여 PETEOS 산화막을 형성할 경우 웨이퍼의 로딩이 신속할 뿐만 아니라 CVD TEOS 산화막의 TEOS의 고온 열분해 공정과는 달라고온 에너지가 필요없다. 그리고, PETEOS 산화막은 TEOS와 산소, 방전 안정을 위한 헬륨 가스를 챔버내에 주입한 후 RF 파워를 인가하여 플라즈마 상태로 만든 후 웨이퍼에 증착하게 되므로 매우 저온에서 공정 진행이 가능하다. 또한, PETEOS 산화막의 공정 온도인 400℃는 PVD 텅스텐 실리사이드막의 성장 온도인 500℃보다 낮기 때문에 정상적으로 챔버내에서 PETEOS 산화막을 형성하기 전 로딩 과정에서 PVD 텅스텐 실리사이드막이 이상 산화될 정도의 강한 열 에너지를 받지 않는다.As described above, when the PETEOS oxide film is formed by using a sheet type chamber, the loading of the wafer is not only fast, but energy required for the high temperature pyrolysis process of the TEOS of the CVD TEOS oxide film is not required. In addition, the PETEOS oxide film is injected into the chamber with TEOS, oxygen, and helium gas for stabilization of the discharge, and then applied to RF power to make a plasma state and then deposited on a wafer, so that the process can be performed at very low temperature. In addition, since the process temperature of the PETEOS oxide film is 400 ° C lower than the growth temperature of the PVD tungsten silicide film, 500 ° C., the PVD tungsten silicide film is not subjected to strong thermal energy such that the PVD tungsten silicide film is abnormally oxidized during the loading process before forming the PETEOS oxide film in the chamber. Do not.
상기와 같은 PETEOS 산화막의 증착 과정을 화학식으로 표현하면 다음과 같다.When the deposition process of the PETEOS oxide film as described above is represented by the formula.
도 1(b)를 참조하면, PETEOS 산화막(15), PVD 텅스텐 실리사이드막(14) 및 폴리실리콘막(13)의 소정 영역을 식각하여 게이트를 형성한다.Referring to FIG. 1B, predetermined regions of the PETEOS oxide film 15, the PVD tungsten silicide film 14, and the polysilicon film 13 are etched to form a gate.
상술한 바와 같이 본 발명에 의하면 폴리실리콘막, PVD 텅스텐 실리사이드막 및 산화막의 적층 게이트를 형성하기 위해 기존의 CVD TEOS 산화막 대신에 PETEOS 산화막을 형성하여 PVD 텅스텐 실리사이드막의 이상 산화를 억제할 수 있고, 이로 인해 게이트 패터닝을 위한 식각 공정에서 폴리실리콘 잔류물의 발생을 억제할 수 있어 소자의 수율을 향상시킬 수 있다.As described above, according to the present invention, a PETEOS oxide film can be formed in place of a conventional CVD TEOS oxide film to form a stacked gate of a polysilicon film, a PVD tungsten silicide film, and an oxide film, thereby preventing abnormal oxidation of the PVD tungsten silicide film. Due to this, it is possible to suppress the generation of polysilicon residues in the etching process for the gate patterning, thereby improving the yield of the device.
Claims (3)
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| KR1020030049292A KR20050010258A (en) | 2003-07-18 | 2003-07-18 | Method of forming a gate in a semiconductor device |
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