KR20040100767A - method for forming low pressure-silicon nitride layer - Google Patents
method for forming low pressure-silicon nitride layer Download PDFInfo
- Publication number
- KR20040100767A KR20040100767A KR1020030033234A KR20030033234A KR20040100767A KR 20040100767 A KR20040100767 A KR 20040100767A KR 1020030033234 A KR1020030033234 A KR 1020030033234A KR 20030033234 A KR20030033234 A KR 20030033234A KR 20040100767 A KR20040100767 A KR 20040100767A
- Authority
- KR
- South Korea
- Prior art keywords
- silicon nitride
- wafer
- low pressure
- nitride film
- nitride layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Formation Of Insulating Films (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 보다 구체적으로는 저압 실리콘 질화막 증착 시, 발생되는 결함을 억제할 수 있는 저압 실리콘 질화막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a low pressure silicon nitride film capable of suppressing defects generated during deposition of a low pressure silicon nitride film.
통상적으로, 절연막으로 사용되는 막질은 옥사이드막과 실리콘 질화막을 주로 사용하며, 이들 절연막은 전극 간의 절연과 패턴 평탄화를 위한 버퍼용도로 사용된다.In general, an oxide film and a silicon nitride film are mainly used for the film quality used as the insulating film, and these insulating films are used as buffers for insulating and pattern planarization between the electrodes.
이 중에서, 실리콘 질화막은 옥사이드막과의 우수한 식각 선택비로 가지고 있으므로, 콘택 식각이나 씨엠피 공정의 베리어로 사용되며, 절연 특성이 좋아 캐패시터 제조에 주로 사용되고 있다. 상기 실리콘 질화막은 열공정에 의해 증착하는 저압 화학기상증착(Low Pressure Chemical Vapor Deposition) 방법 또는 플라즈마를 이용하여 증착하는 플라즈마가 강화된 화학기상증착(Plasma Enhanced Chemical Vapor Deposition) 방법에 의해 형성되며, 각각의 특성이 달라 증착하는 목적에 맞게 선택하여 이용한다.Among them, since the silicon nitride film has an excellent etching selectivity with the oxide film, the silicon nitride film is used as a barrier for contact etching or CMP process, and is mainly used for capacitor production due to its good insulating properties. The silicon nitride film is formed by a Low Pressure Chemical Vapor Deposition method deposited by a thermal process or a Plasma Enhanced Chemical Vapor Deposition method deposited using a plasma, respectively. The characteristics of the different, depending on the purpose of the deposition used to select.
이중에서, 저압 화학기상증착 실리콘 질화막은 반도체 제조 증착 공정에 있어서 고려되는 특성 중 스텝커버리지와 식각비, 균일도, 결함 발생 정도 등에서 우수한 특성을 가지고 있으나, 스트레스 특성이 다른 막질에 비해 큰 값을 가지고 있어 막질 두께가 두껍거나 취약한 영역에 증착될 경우 낮은 열로도 필름 리프팅(film lifting)이나 크랙(crack)이 발생될 확률이 높다.Among them, the low pressure chemical vapor deposition silicon nitride film has excellent characteristics such as step coverage, etching ratio, uniformity and defect generation among the properties considered in the semiconductor manufacturing deposition process, but the stress property has a larger value than other film quality. If the film is deposited in a thick or vulnerable region, film lifting or cracking is likely to occur even with low heat.
도 1및 도 2는 종래 기술에 따른 저압 실리콘 질화막 형성 방법을 설명하기 위한 도면으로서, 도 1은 튜브 타입의 증착장비의 단면도이고, 도 2는 실리콘 질화막이 형성된 웨이퍼 단면도이다.1 and 2 are views for explaining a low pressure silicon nitride film forming method according to the prior art, Figure 1 is a cross-sectional view of the tube-type deposition equipment, Figure 2 is a cross-sectional view of the wafer on which the silicon nitride film is formed.
먼저, 도 1 및 도 2에 도시된 바와 같이, 튜브 타입의 증착장비(1) 내에 다수개의 웨이퍼(2)를 적재시킨 다음, 이들 웨이퍼(2) 사이로 공정가스를 흘려보냄으로써, 웨이퍼와 공정가스의 화학반응에 의해 실리콘 질화막(3)이 증착된다. 이때, 상기 웨이퍼(2)는 특정 일부분만이 슬릿(slit)(3) 등에 의해 고정된다.First, as shown in FIG. 1 and FIG. 2, a plurality of wafers 2 are loaded into a tube type deposition apparatus 1, and then a process gas is flowed between these wafers 2, thereby producing a wafer and a process gas. The silicon nitride film 3 is deposited by the chemical reaction of. At this time, only a specific portion of the wafer 2 is fixed by a slit 3 or the like.
그러나, 상기 튜브 타입의 증착장비는 구조상 웨이퍼의 타면(소자가 형성된 이면)에도 증착이 이루어짐으로써, 웨이퍼의 일면에서 웨이퍼의 타면으로 이어지는 부분에 증착된 실리콘 질화막이 후속 공정 중에 리프팅되어 웨이퍼 일면 전체에 걸쳐 결함으로 작용하고 있다.However, the tube type deposition apparatus is structurally deposited on the other side of the wafer (back side on which the element is formed), so that the silicon nitride film deposited on one side of the wafer from the one side to the other side of the wafer is lifted during the subsequent process, so that the entire surface of the wafer is lifted. It acts as a defect.
이때, 상기 웨이퍼 타면에 박혀있는 결함을 제거하기 위해, 웨이퍼 일면 전면을 감광막으로 마스킹한 다음, 상기 웨이퍼를 인산이나 불산 등과 같은 용액에 디핑시켜 제거하는 방법이 사용되고 있으나, 이러한 결함을 제거하기 위해 공정수가 4∼5공정이 추가되므로 생산성이 저하될 뿐만 아니라 신규 장비 구입에 따른 비용이 증가되는 문제점이 있었다.In this case, in order to remove the defects stuck to the other surface of the wafer, a method of masking the entire surface of one side of the wafer with a photoresist film and then dipping the wafer into a solution such as phosphoric acid or hydrofluoric acid is used. Since the number of 4 to 5 process is added, not only the productivity is lowered but also the cost of purchasing new equipment increases.
따라서, 이러한 리프팅에 의한 결함은 크기가 매우 크며, 실리콘 질화막 표면에 박혀 있는 형상을 취하기 때문에 제거가 어렵다. 또한, 저압 실리콘 질화막 표면에 결함이 박혀 있는 상태에서 그대로 후속 공정을 진행하게 되면, 제품 불량 및 장비 오염 등의 문제점이 있다.Therefore, the defects caused by such lifting are very large and difficult to remove because they take the shape of being embedded in the silicon nitride film surface. In addition, if the subsequent process proceeds as it is in the state where the defect is stuck on the surface of the low-pressure silicon nitride film, there are problems such as product defects and equipment contamination.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 저압 화학기상증착용 실리콘 질화막 형성 시, 웨이퍼의 타면에 증착이 되지 않고 웨이퍼 의 일면에만 증착 공정이 진행되도록 함으로써, 리프트성 결함 발생을 방지할 수 있는 저압 실리콘 질화막 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, and when forming a silicon nitride film for low pressure chemical vapor deposition, the deposition process is performed only on one side of the wafer without deposition on the other side of the wafer, thereby generating liftability defects. It is an object of the present invention to provide a method for forming a low pressure silicon nitride film that can be prevented.
도 1 및 도 2는 종래 기술에 따른 저압 실리콘 질화막 형성 방법을 설명하기 위한 도면.1 and 2 are views for explaining a low pressure silicon nitride film forming method according to the prior art.
도 3 및 도 4는 본 발명에 따른 저압 실리콘 질화막 형성 방법을 설명하기 위한 도면.3 and 4 are views for explaining a low pressure silicon nitride film forming method according to the present invention.
상기 목적을 달성하고자, 본 발명에 따른 저압 실리콘 질화막 형성 방법은 하나의 히터가 장착된 단일 챔버를 제공하는 단계와, 히터 위에 웨이퍼를 안착시키는 단계와, 웨이퍼에 저압 화학기상증착 공정을 진행하여 웨이퍼 일면에 실리콘 질화막을 형성하는 단계를 포함한 것을 특징으로 한다.In order to achieve the above object, the low-pressure silicon nitride film forming method according to the present invention is to provide a single chamber equipped with a heater, the step of depositing the wafer on the heater, the low-pressure chemical vapor deposition process on the wafer by the wafer It characterized in that it comprises a step of forming a silicon nitride film on one surface.
상기 단일 챔버는 400℃이상의 온도 및 1토르∼대기압 사이의 압력을 유지하고, 상기 단일 챔버 내로 NH3/SiH4 및 NH3/SiCl2h2(DCS) 중 어느 한 그룹의 식가가스를 공급하는 것이 바람직하다.The single chamber preferably maintains a temperature between 400 [deg.] C. and a pressure between 1 Torr and atmospheric pressure, and feeds the edible gas of any one group of NH3 / SiH4 and NH3 / SiCl2h2 (DCS) into the single chamber.
이때, 상기 NH3/SiH4 공정가스 공급 공정에서, 상기 NH3가스는 10∼2000sccm, 상기 SiH4가스는 10∼100sccm의 유량으로 각각 공급한다.At this time, in the NH3 / SiH4 process gas supply process, the NH3 gas is supplied at a flow rate of 10 to 2000 sccm, the SiH4 gas is 10 to 100 sccm, respectively.
도 3및 도 4는 본 발명에 따른 저압 실리콘 질화막 형성 방법을 설명하기 위한 도면으로서, 도 3은 단일 챔버의 단면도이고, 도 4는 실리콘 질화막이 형성된 웨이퍼 단면도이다.3 and 4 are views for explaining a low pressure silicon nitride film forming method according to the present invention, Figure 3 is a cross-sectional view of a single chamber, Figure 4 is a cross-sectional view of the wafer on which the silicon nitride film is formed.
본 발명에 따른 저압 실리콘 질화막 형성 방법은, 도 3 및 도 4에 도시된 바와 같이, 먼저, 단일 챔버(10) 내의 히터(11) 위에 웨이퍼(12)를 안착시킨다. 이때, 상기 단일 챔버(10)는 400℃이상의 온도 및 1토르∼대기압 사이의 압력을 유지하도록 셋팅시키고, 상기 단일 챔버(10) 내로 NH3/SiH4 및 NH3/SiCl2h2(DCS) 중 어느 한 그룹의 공정가스를 공급한다. 한편, 상기 NH3/SiH4 공정가스를 공급하는 공정에서, 상기 NH3가스는 10∼2000sccm, 상기 SiH4가스는 10∼100sccm의 유량으로 각각 공급한다. 이로써, 상기 공정가스와의 화학반응으로 인해 웨이퍼 위에 저압 실리콘 질화막(13)이 형성된다.In the method of forming a low pressure silicon nitride film according to the present invention, as shown in FIGS. 3 and 4, first, the wafer 12 is seated on the heater 11 in the single chamber 10. At this time, the single chamber 10 is set to maintain a temperature between 400 ° C or more and a pressure between 1 Torr and atmospheric pressure, and the process of any one group of NH 3 / SiH 4 and NH 3 / SiCl 2 h 2 (DCS) into the single chamber 10. Supply gas. In the process of supplying the NH 3 / SiH 4 process gas, the NH 3 gas is supplied at a flow rate of 10 to 2000 sccm, and the SiH 4 gas is 10 to 100 sccm, respectively. As a result, a low pressure silicon nitride film 13 is formed on the wafer due to the chemical reaction with the process gas.
본 발명의 저압 실리콘 질화막(13)은 게이트 측벽, 비트라인 측벽 또는 콘택의 측벽으로 이용할 수 있으며, 이외에도 식각정지막, STI(Shallow Trench Isolation) 공정에서 패드 질화막, 캐패시터의 유전막, 하드마스크 등에도 적용 가능하다.The low-pressure silicon nitride film 13 of the present invention may be used as a gate sidewall, a bitline sidewall, or a sidewall of a contact. In addition, the low pressure silicon nitride layer 13 may also be applied to a pad nitride layer, a capacitor dielectric layer, a hard mask, and the like in an etch stop layer and a shallow trench isolation (STI) process. It is possible.
본 발명에서는 단일 챔버 내로 웨이퍼를 한장 단위로 인입시킨 다음, 상기 웨이퍼에 저압 화학기상증착 공정을 진행시켜 웨이퍼 일면에만 저압 실리콘질화막을 형성함으로써, 기존의 튜브 타입의 증착장비를 사용함에 따른 웨이퍼 결함 문제를 해결할 수 있다. 즉, 기존의 퍼니스 타입의 증착장비를 사용함에 따라 웨이퍼의 일면에서 웨이퍼의 타면으로 이어지는 부분에 증착된 실리콘 질화막이 리프팅되면서 결함으로 작용하는 문제를 해결할 수 있다.In the present invention, a wafer is introduced into a single chamber by one unit, and then a low-pressure chemical vapor deposition process is performed on the wafer to form a low-pressure silicon nitride film on only one surface of the wafer, thereby using a conventional tube type deposition apparatus. Can be solved. That is, by using the existing furnace type deposition equipment, the problem that the silicon nitride film deposited on one side of the wafer leading to the other surface of the wafer is lifted, which can act as a defect can be solved.
이상에서와 같이, 본 발명은 단일 챔버 내에서 한장의 웨이퍼에 저압 화학기상증착 공정을 진행시킴으로써, 웨이퍼 일면에만 저압 실리콘 질화막을 형성할 수 있다. 또한, 후속 열공정, 즉 고온 공정인 산화 공정 또는 화학기상증착 공정을 진행하여도 리프팅을 일으킬만한 소오스가 없기 때문에 결함이 발생되지 않는다.As described above, the present invention can form a low pressure silicon nitride film on only one surface of a wafer by performing a low pressure chemical vapor deposition process on a single wafer in a single chamber. In addition, defects do not occur even after a subsequent thermal process, that is, an oxidation process or a chemical vapor deposition process, which are high temperature processes, because there is no source to cause lifting.
한편, 본 발명은 기존의 저압 실리콘 질화막 증착 공정에서, 기존의 웨이퍼 타면에 박혀있는 결함을 제거하기 위해 별도로 4∼5공정을 추가시킬 필요가 없으므로, 공정이 단순화되고 생산비가 절감될 뿐만 아니라 열공정에 의한 디바이스의 특성저하를 막을 수 있다.On the other hand, the present invention does not need to add 4 to 5 processes separately to remove the defects stuck on the other wafer surface in the conventional low pressure silicon nitride film deposition process, not only simplify the process and reduce the production cost but also thermal process It is possible to prevent the deterioration of the characteristics of the device.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030033234A KR20040100767A (en) | 2003-05-24 | 2003-05-24 | method for forming low pressure-silicon nitride layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030033234A KR20040100767A (en) | 2003-05-24 | 2003-05-24 | method for forming low pressure-silicon nitride layer |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20040100767A true KR20040100767A (en) | 2004-12-02 |
Family
ID=37378110
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020030033234A KR20040100767A (en) | 2003-05-24 | 2003-05-24 | method for forming low pressure-silicon nitride layer |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20040100767A (en) |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8841182B1 (en) | 2013-03-14 | 2014-09-23 | Asm Ip Holding B.V. | Silane and borane treatments for titanium carbide films |
US8846550B1 (en) | 2013-03-14 | 2014-09-30 | Asm Ip Holding B.V. | Silane or borane treatment of metal thin films |
US9394609B2 (en) | 2014-02-13 | 2016-07-19 | Asm Ip Holding B.V. | Atomic layer deposition of aluminum fluoride thin films |
US9704716B2 (en) | 2013-03-13 | 2017-07-11 | Asm Ip Holding B.V. | Deposition of smooth metal nitride films |
US9786492B2 (en) | 2015-11-12 | 2017-10-10 | Asm Ip Holding B.V. | Formation of SiOCN thin films |
US9786491B2 (en) | 2015-11-12 | 2017-10-10 | Asm Ip Holding B.V. | Formation of SiOCN thin films |
US9831094B2 (en) | 2005-10-27 | 2017-11-28 | Asm International N.V. | Enhanced thin film deposition |
US9941425B2 (en) | 2015-10-16 | 2018-04-10 | Asm Ip Holdings B.V. | Photoactive devices and materials |
US10002936B2 (en) | 2014-10-23 | 2018-06-19 | Asm Ip Holding B.V. | Titanium aluminum and tantalum aluminum thin films |
US10186420B2 (en) | 2016-11-29 | 2019-01-22 | Asm Ip Holding B.V. | Formation of silicon-containing thin films |
US10504901B2 (en) | 2017-04-26 | 2019-12-10 | Asm Ip Holding B.V. | Substrate processing method and device manufactured using the same |
US10600637B2 (en) | 2016-05-06 | 2020-03-24 | Asm Ip Holding B.V. | Formation of SiOC thin films |
US10643925B2 (en) | 2014-04-17 | 2020-05-05 | Asm Ip Holding B.V. | Fluorine-containing conductive films |
US10847529B2 (en) | 2017-04-13 | 2020-11-24 | Asm Ip Holding B.V. | Substrate processing method and device manufactured by the same |
US10991573B2 (en) | 2017-12-04 | 2021-04-27 | Asm Ip Holding B.V. | Uniform deposition of SiOC on dielectric and metal surfaces |
US11158500B2 (en) | 2017-05-05 | 2021-10-26 | Asm Ip Holding B.V. | Plasma enhanced deposition processes for controlled formation of oxygen containing thin films |
-
2003
- 2003-05-24 KR KR1020030033234A patent/KR20040100767A/en not_active Application Discontinuation
Cited By (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10297444B2 (en) | 2005-10-27 | 2019-05-21 | Asm International N.V. | Enhanced thin film deposition |
US9831094B2 (en) | 2005-10-27 | 2017-11-28 | Asm International N.V. | Enhanced thin film deposition |
US10964534B2 (en) | 2005-10-27 | 2021-03-30 | Asm International | Enhanced thin film deposition |
US9704716B2 (en) | 2013-03-13 | 2017-07-11 | Asm Ip Holding B.V. | Deposition of smooth metal nitride films |
US10074541B2 (en) | 2013-03-13 | 2018-09-11 | Asm Ip Holding B.V. | Deposition of smooth metal nitride films |
US9583348B2 (en) | 2013-03-14 | 2017-02-28 | Asm Ip Holding B.V. | Silane and borane treatments for titanium carbide films |
US9236247B2 (en) | 2013-03-14 | 2016-01-12 | Asm Ip Holding B.V. | Silane and borane treatments for titanium carbide films |
US9111749B2 (en) | 2013-03-14 | 2015-08-18 | Asm Ip Holdings B.V. | Silane or borane treatment of metal thin films |
US8846550B1 (en) | 2013-03-14 | 2014-09-30 | Asm Ip Holding B.V. | Silane or borane treatment of metal thin films |
US8841182B1 (en) | 2013-03-14 | 2014-09-23 | Asm Ip Holding B.V. | Silane and borane treatments for titanium carbide films |
US9394609B2 (en) | 2014-02-13 | 2016-07-19 | Asm Ip Holding B.V. | Atomic layer deposition of aluminum fluoride thin films |
US11450591B2 (en) | 2014-04-17 | 2022-09-20 | Asm Ip Holding B.V. | Fluorine-containing conductive films |
US10643925B2 (en) | 2014-04-17 | 2020-05-05 | Asm Ip Holding B.V. | Fluorine-containing conductive films |
US11823976B2 (en) | 2014-04-17 | 2023-11-21 | ASM IP Holding, B.V. | Fluorine-containing conductive films |
US11139383B2 (en) | 2014-10-23 | 2021-10-05 | Asm Ip Holding B.V. | Titanium aluminum and tantalum aluminum thin films |
US10002936B2 (en) | 2014-10-23 | 2018-06-19 | Asm Ip Holding B.V. | Titanium aluminum and tantalum aluminum thin films |
US10636889B2 (en) | 2014-10-23 | 2020-04-28 | Asm Ip Holding B.V. | Titanium aluminum and tantalum aluminum thin films |
US9941425B2 (en) | 2015-10-16 | 2018-04-10 | Asm Ip Holdings B.V. | Photoactive devices and materials |
US11362222B2 (en) | 2015-10-16 | 2022-06-14 | Asm Ip Holding B.V. | Photoactive devices and materials |
US10861986B2 (en) | 2015-10-16 | 2020-12-08 | Asm Ip Holding B.V. | Photoactive devices and materials |
US9786492B2 (en) | 2015-11-12 | 2017-10-10 | Asm Ip Holding B.V. | Formation of SiOCN thin films |
US10510529B2 (en) | 2015-11-12 | 2019-12-17 | Asm Ip Holding B.V. | Formation of SiOCN thin films |
US11996284B2 (en) | 2015-11-12 | 2024-05-28 | Asm Ip Holding B.V. | Formation of SiOCN thin films |
US11107673B2 (en) | 2015-11-12 | 2021-08-31 | Asm Ip Holding B.V. | Formation of SiOCN thin films |
US10424476B2 (en) | 2015-11-12 | 2019-09-24 | Asm Ip Holding B.V. | Formation of SiOCN thin films |
US9786491B2 (en) | 2015-11-12 | 2017-10-10 | Asm Ip Holding B.V. | Formation of SiOCN thin films |
US10600637B2 (en) | 2016-05-06 | 2020-03-24 | Asm Ip Holding B.V. | Formation of SiOC thin films |
US11562900B2 (en) | 2016-05-06 | 2023-01-24 | Asm Ip Holding B.V. | Formation of SiOC thin films |
US10186420B2 (en) | 2016-11-29 | 2019-01-22 | Asm Ip Holding B.V. | Formation of silicon-containing thin films |
US10847529B2 (en) | 2017-04-13 | 2020-11-24 | Asm Ip Holding B.V. | Substrate processing method and device manufactured by the same |
US11195845B2 (en) | 2017-04-13 | 2021-12-07 | Asm Ip Holding B.V. | Substrate processing method and device manufactured by the same |
US10504901B2 (en) | 2017-04-26 | 2019-12-10 | Asm Ip Holding B.V. | Substrate processing method and device manufactured using the same |
US11776807B2 (en) | 2017-05-05 | 2023-10-03 | ASM IP Holding, B.V. | Plasma enhanced deposition processes for controlled formation of oxygen containing thin films |
US11158500B2 (en) | 2017-05-05 | 2021-10-26 | Asm Ip Holding B.V. | Plasma enhanced deposition processes for controlled formation of oxygen containing thin films |
US10991573B2 (en) | 2017-12-04 | 2021-04-27 | Asm Ip Holding B.V. | Uniform deposition of SiOC on dielectric and metal surfaces |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2019147462A1 (en) | Treatment methods for silicon nitride thin films | |
KR20040100767A (en) | method for forming low pressure-silicon nitride layer | |
US20090250752A1 (en) | Methods of fabricating semiconductor device having a metal gate pattern | |
JP4126165B2 (en) | Multi-deposition SACVD reactor | |
KR20090119661A (en) | Protective layer to enable damage free gap fill | |
US7384486B2 (en) | Chamber cleaning method | |
US11848232B2 (en) | Method for Si gap fill by PECVD | |
JP3601988B2 (en) | Method of forming insulating film | |
KR100497474B1 (en) | Method of forming gate electrode in semiconductor device | |
JP4154471B2 (en) | Manufacturing method of semiconductor device | |
US20240175121A1 (en) | Film forming method, processing apparatus, and processing system | |
KR100670670B1 (en) | A method for fabricating semiconductor device with landing plug contact structure | |
KR100533969B1 (en) | A method for forming storage node of inner capacitor | |
JPH10256183A (en) | Manufacture of semiconductor device | |
KR100364804B1 (en) | Method for Fabricating of Semiconductor Device | |
KR20020036127A (en) | method for forming contact plug of semiconductor device | |
KR100562316B1 (en) | A method for manufacturing pre-metal dielectric layer of a semiconductor device | |
KR100472518B1 (en) | Method for depositing nitride film using single chamber type cvd device | |
JP4695158B2 (en) | Manufacturing method of semiconductor device | |
US20060234518A1 (en) | Chemical Vapor Deposition Method Preventing Particles Forming in Chamber | |
KR20050025820A (en) | Method for manufacturing inter metal dielectric of semiconductor device | |
KR100744107B1 (en) | Method for manufaturing capacitor | |
JP2004022621A (en) | Apparatus and method of manufacturing semiconductor device | |
KR19990055216A (en) | Method of forming interlayer insulating film of semiconductor device | |
KR19990000067A (en) | Method of manufacturing semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |