KR20050010229A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to simplify a process by eliminating the necessity of a deposition process for depositing a silicon oxide layer in a cell region and a wet etch process in the cell region, and to control a bridge between a gate line and a contact plug by preventing a silicon nitride layer from being attacked by a wet etch process. CONSTITUTION: A gate line is formed on a semiconductor substrate(21) in which a cell region and a peripheral region are defined. A silicon oxide layer(25a), a silicon nitride layer(25b) and an organic layer are sequentially stacked on the resultant structure including the gate line. A photoresist layer is formed on the organic layer and is patterned by an exposure/development process to form a mask layer for opening the peripheral region. The silicon oxide layer, the silicon nitride and the organic layer in the peripheral region exposed by the mask layer are etched to form a gate spacer of a triple structure on the sidewall of the gate line formed in the peripheral region. The mask layer and the organic layer remaining in the cell region are simultaneously eliminated.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a semiconductor device capable of preventing bridges between gate lines and contact plugs.

In general, when the electric field is strongly formed at the edge of the drain region, the MOSFET increases the hot carriers and deteriorates the characteristics of the transistors. gate spacer). In this case, the gate spacer serves to secure a source / drain region for ion implantation of high-concentration impurities after adopting a lightly doped drain (LDD) structure as well as for insulation between the gate electrodes.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, a gate line stacked in the order of the gate oxide film 12, the gate electrode 13, and the hard mask nitride film 14 is formed on the semiconductor substrate 11 having a cell region and a peripheral region defined therein. Thereafter, the first silicon oxide film 15a, the silicon nitride film 15b, and the second silicon oxide film 15c are sequentially formed on the entire surface including the gate line.

Next, after forming the peripheral region open mask layer 16 covering the cell region and opening the peripheral region, the first silicon oxide film 15a and silicon of the peripheral region are formed using the peripheral region open mask layer 16 as an etch mask. The nitride film 15b and the second silicon oxide film 15c are selectively etched to form gate spacers 15 on both side walls of the gate line formed in the peripheral region. In this case, the gate spacer 15 has a triple structure of the first silicon oxide film 15a, the silicon nitride film 15b, and the second silicon oxide film 15c.

Subsequently, the ion implantation process is performed with the peripheral area open mask layer 16 remaining to form the source / drain regions 17.

As shown in FIG. 1B, after removing the peripheral region open mask layer 16, the cell region is opened and a cell region open mask layer 18 is formed to cover the peripheral region. Here, the cell region open mask layer 18 and the peripheral region open mask layer 16 are formed of a photosensitive film.

Subsequently, the second silicon oxide film 15c remaining in the cell region is selectively wet-etched using the cell region open mask layer 18 as an etching mask. At this time, since the silicon nitride film 15b serves as an etching barrier during the wet etching of the second silicon oxide film 15c, the first silicon oxide film 15a is not etched.

As shown in FIG. 1C, after removing the cell region open mask layer 18, an interlayer insulating film 19 is deposited on the entire surface of the semiconductor substrate 11. Subsequently, the interlayer insulating film 19 is removed through self-aligned contact etching, and the silicon nitride film and the first silicon oxide film between the gate lines are subsequently removed to form contact holes. The self-aligned contact etching process for forming such a contact hole is performed only in the cell region.

Next, the contact plug 20 is filled in the contact hole. In this case, the contact plug 20 is a plug to which the storage node contact and the bit line contact are connected.

In the prior art as described above, a gate spacer having a double structure of the first silicon oxide film 15a and the silicon nitride film 15b is formed in the cell region, and the first silicon oxide film 15a, the silicon nitride film 15b and the first film are formed in the peripheral region. The triple spacer structure of the silicon dioxide film 15c is formed.

Here, the silicon nitride film 15b serves as a gate spacer and serves as a barrier when forming contact holes in the cell region, and the first silicon oxide film 15a forms the gate electrode 13 and the semiconductor substrate 11 when the silicon nitride film 15b is formed. It serves as a buffer for buffering the stress is applied to the second silicon oxide film (15c) is introduced to prevent the short channel effect when the ion implantation in the peripheral region.

However, the prior art has a problem that the silicon nitride film 15b is attacked from the wet etching solution during wet etching to remove the second silicon oxide film 15c in the cell region.

As a result, the first silicon oxide layer 15a is additionally etched through the attacked silicon nitride layer 15b to expose a part of the gate line, which is a bridge between the gate line and the contact plug 20 (see 'A' in FIG. 1C). ).

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and provides a method of manufacturing a semiconductor device suitable for preventing bridges between gate lines and contact plugs generated when a nitride film acting as a gate spacer is attacked. have.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 gate oxide film

23 gate electrode 24 hard mask nitride film

25a: silicon oxide film 25b: silicon nitride film

25c: organic antireflection film 25: gate spacer

26: peripheral area open mask layer 27: source / drain area

28: interlayer insulating film 29: contact plug

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a gate line on a semiconductor substrate in which a cell region and a peripheral region are defined; Stacking, applying a photoresist film on the organic layer, and patterning the photoresist layer by exposure and development to form a mask layer for opening the peripheral zero region, a silicon oxide film, a silicon nitride layer in the peripheral region exposed by the mask layer, and Etching the organic film to form a gate spacer having a triple structure on the sidewall of the gate line formed in the peripheral region, and simultaneously removing the organic layer remaining in the mask layer and the cell region, Simultaneously removing the organic layer remaining in the mask layer and the cell region; The silicon nitride film is subjected to an etching condition having a high selectivity with respect to the mask layer and the organic film, and the step of simultaneously removing the organic film remaining in the mask layer and the cell region is a downstream method It is characterized in that it proceeds by an isotropic dry etching method using a plasma, the organic film is characterized in that using an organic antireflection film of the base polymer series, crosslinker series, thermal acid generation series or solvent series.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, gate lines stacked in the order of the gate oxide layer 22, the gate electrode 23, and the hard mask nitride layer 24 are formed on the semiconductor substrate 21 having the cell region and the peripheral region defined therein. After that, the silicon oxide film 25a, the silicon nitride film 25b, and the organic antireflection film 25c are sequentially formed on the entire surface including the gate line.

Here, the organic antireflection film 25c uses a base polymer, a cross linker, a thermal acid generator, or a solvent antireflection film.

In addition, an inorganic antireflection film may be used in addition to the organic antireflection film 25c. However, the inorganic antireflection film does not have a property of being removed by oxygen plasma during stripping of the subsequent peripheral open mask layer 26, and thus remains unnecessary in the cell area. I never do that.

Next, a photoresist film is coated on the entire surface of the semiconductor substrate 21 and patterned by exposure and development to form a peripheral region open mask layer 26 covering the cell region and opening the peripheral region.

Subsequently, the organic anti-reflective film 25c, the silicon nitride film 25b, and the silicon oxide film 25a in the peripheral area are selectively etched using the peripheral area open mask layer 26 as an etching mask, and both sides of the gate line formed in the peripheral area. The gate spacer 25 is formed on the wall. In this case, the gate spacer 25 has a triple structure of the silicon oxide film 25a, the silicon nitride film 25b, and the organic antireflection film 25c.

Subsequently, the ion implantation process is performed while the peripheral region open mask layer 26 is left to form the source / drain regions 27. At this time, the organic antireflection film 25c constituting the peripheral area open mask layer 26 and the gate spacer is used as an ion implantation mask.

As shown in FIG. 2B, the peripheral area open mask layer 26 is stripped. At this time, the peripheral area open mask layer 26 is removed by an isotropic dry etching method using a plasma of the downstream (downstream) method.

At the time of stripping the peripheral area open mask layer 26 as described above, the organic anti-reflective film 25c of the cell region is also removed at the same time, and the organic anti-reflective film 25c that forms the gate spacer of the peripheral area is also removed.

The reason why the organic antireflection film 25c of the cell region is removed when the peripheral area open mask layer 26 is removed is that the photoresist film forming the peripheral area open mask layer 26 is an organic material in the same manner as the organic antireflection film. Because.

Therefore, since the peripheral area open mask layer 26 is formed of an organic photosensitive film, the peripheral area open mask layer 26 and the organic anti-reflection film 25c are simultaneously removed because there is no selection ratio due to isotropic dry etching using plasma. will be.

As described above, the gate spacer of the peripheral region remains after the removal of the peripheral region open mask layer 26 in a double structure of the silicon oxide film 25a and the silicon nitride film 25b. The organic anti-reflection film 25c is a source / drain region. (27) It may be removed after ion implantation because it was used to prevent short channel effect during formation.

Meanwhile, as the organic anti-reflective coating is removed, the silicon nitride film 24 is exposed to a dry etching process, wherein the silicon nitride film 24 has a problem of being attacked during wet etching with a low selectivity as in the prior art. The nitride film 24 is not attacked because the selectivity to isotropic dry etching using plasma is very high.

As shown in FIG. 2C, an interlayer insulating film 28 is deposited on the entire surface of the semiconductor substrate 21. Subsequently, the interlayer insulating film 28 is removed through self-aligned contact etching, and the silicon nitride film and the silicon oxide film between the gate lines are subsequently removed to form contact holes. The self-aligned contact etching process for forming such a contact hole is performed only in the cell region.

Next, the contact plug 29 is filled in the contact hole. In this case, the contact plug 29 is a plug to which the storage node contact and the bit line contact are connected.

According to the embodiment described above, the present invention does not deposit a silicon oxide film on the silicon nitride film and does not perform a wet etching process for removing the silicon oxide film from the cell region.

Further, in the present invention, since the organic antireflection film is formed under the peripheral area open mask layer in advance, the photolithography process for forming the peripheral area open mask layer proceeds very precisely.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above can omit the silicon oxide film deposition process in the cell region and the wet etching process in the cell region, there is an effect that can simplify the process.

In addition, since the silicon nitride film is not attacked by wet etching, the bridge between the gate line and the contact plug is suppressed, thereby improving the reliability of the semiconductor device.

Claims (5)

Forming a gate line on a semiconductor substrate having a cell region and a peripheral region defined therein; Sequentially depositing a silicon oxide film, a silicon nitride film, and an organic film on the entire surface including the gate line; Forming a mask layer on the organic layer by patterning the photoresist layer and patterning the photoresist layer by exposure and development; Etching a silicon oxide film, a silicon nitride film, and an organic film of the peripheral area exposed by the mask layer to form a gate spacer having a triple structure on sidewalls of the gate line formed in the peripheral area; And Simultaneously removing the organic layer remaining in the mask layer and the cell region Method for manufacturing a semiconductor device comprising a. The method of claim 1, Simultaneously removing the organic layer remaining in the mask layer and the cell region; And the silicon nitride film is subjected to a dry etching condition having a high selectivity with respect to the mask layer and the organic film. The method of claim 1, Simultaneously removing the organic layer remaining in the mask layer and the cell region; A method for manufacturing a semiconductor device, characterized in that it proceeds by an isotropic dry etching method using a downstream plasma. The method of claim 1, The organic film is formed of an organic antireflection film. The method of claim 4, wherein The organic antireflection film, A method of manufacturing a semiconductor device, comprising using an organic antireflection film of a base polymer series, a crosslinker series, a thermal acid generation series, or a solvent series.