KR20050009623A - Method of forming copper wiring in semiconductor device - Google Patents
Method of forming copper wiring in semiconductor device Download PDFInfo
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- KR20050009623A KR20050009623A KR1020030049425A KR20030049425A KR20050009623A KR 20050009623 A KR20050009623 A KR 20050009623A KR 1020030049425 A KR1020030049425 A KR 1020030049425A KR 20030049425 A KR20030049425 A KR 20030049425A KR 20050009623 A KR20050009623 A KR 20050009623A
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- Prior art keywords
- sacrificial anode
- copper
- forming
- metal pattern
- anode metal
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 63
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 63
- 239000010949 copper Substances 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 239000011229 interlayer Substances 0.000 claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 18
- 239000000126 substance Substances 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000007797 corrosion Effects 0.000 claims description 15
- 238000005260 corrosion Methods 0.000 claims description 15
- 238000007517 polishing process Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000003112 inhibitor Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 구리배선 형성방법에 관한 것으로, 특히 다마신 패턴 내에 구리배선을 형성하기 위한 화학적 기계적 연마(CMP) 공정시 발생되는 구리배선의 부식을 방지하여 구리배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 구리배선 형성방법에 관한 것이다.The present invention relates to a method for forming a copper wiring of a semiconductor device, in particular to prevent corrosion of the copper wiring generated during the chemical mechanical polishing (CMP) process for forming a copper wiring in the damascene pattern to improve the reliability of the copper wiring. The present invention relates to a copper wiring forming method of a semiconductor device.
일반적으로, 반도체 산업이 초대규모 집적 회로(Ultra Large Scale Integration; ULSI)로 옮겨가면서 소자의 지오메트리(geometry)가 서브-하프-마이크로(sub-half-micron) 영역으로 계속 줄어드는 반면, 성능 향상 및 신뢰도 측면에서 회로 밀도(circuit density)는 증가하고 있다. 이러한 요구에 부응하여, 반도체 소자의 금속 배선을 형성함에 있어서 구리는 알루미늄에 비해 녹는점이 높아 전기이동도(electro-migration; EM)에 대한 저항이 커서 소자의 신뢰성을 향상시킬 수 있고, 비저항이 낮아 신호전달 속도를 증가시킬 수 있어, 집적 회로(integration circuit)에 유용한 상호연결 재료(interconnection material)로 사용되고 있다.In general, as the semiconductor industry moves to Ultra Large Scale Integration (ULSI), the geometry of devices continues to shrink into the sub-half-micron area, while improving performance and reliability. In terms of circuit density, circuit density is increasing. In response to these demands, copper has a higher melting point than aluminum in forming metal wirings of semiconductor devices, and thus has high resistance to electro-migration (EM), thereby improving reliability of the device and having low specific resistance. The speed of signal transmission can be increased, making it a useful interconnection material for integration circuits.
현재, 사용이 가능한 구리 매립 방법으로는 물리기상증착(PVD)법/리플로우 (reflow), 화학기상증착법(CVD), 전기 도금(Electroplating)법, 무전기 도금(Electroless-plating)법 등이 있으며, 이 중에서 선호되는 방법은 구리 매립 특성이 비교적 양호한 전기 도금법과 화학기상증착법이다.Currently available copper embedding methods include physical vapor deposition (PVD) method / reflow, chemical vapor deposition (CVD), electroplating method, electroless-plating method, etc. Among these, the preferred methods are electroplating and chemical vapor deposition, which have relatively good copper embedding properties.
금속 배선의 재료로 구리를 채용하면서, 반도체 소자의 구리 배선 형성 공정에 하부층과 전기적으로 연결하면서 배선이 형성될 부분을 다마신 기법을 적용하여 형성하고 있다.While copper is used as the material of the metal wiring, the portion where the wiring is to be formed is electrically formed by applying the damascene technique to the copper wiring forming process of the semiconductor element while electrically connecting with the lower layer.
다마신 패턴에 구리 배선을 형성하기 위해서는 상기한 여러 방법으로 다마신패턴에 구리를 매립시킨 후에 매립된 구리층을 화학적 기계적 연마(CMP) 공정으로 연마하여 이웃하는 구리 배선과 격리(isolation)시킨다. 그런데, 화학적 기계적 연마 공정에서 발생되는 구리 부식을 방지하기 위하여, 일반적으로 연마 가공액인 슬러리(slurry)에 부식 방지제인 BTA를 첨가하거나, 별도의 가공 단계를 추가하여 BTA를 사용하여 부식 발생을 억제하고 있다. 그러나, 이렇게 BTA를 사용할 경우에 원하지 않는 결함(defect)이 발생되고, 구리와 BTA간의 혼합물이 형성되어 반도체 소자에 악영향을 미치게 된다. 반대로 부식 방지제인 BTA를 사용하지 않게되면 구리배선에 부식이 발생되어 배선의 저항을 증가시키거나 심할 경우 단락을 유발시키는 문제가 있다.In order to form a copper wiring on the damascene pattern, copper is embedded in the damascene pattern by various methods described above, and the embedded copper layer is polished by a chemical mechanical polishing (CMP) process to isolate the neighboring copper wiring. However, in order to prevent copper corrosion generated in the chemical mechanical polishing process, BTA, which is a corrosion inhibitor, is added to a slurry, which is generally a polishing process liquid, or a separate processing step is added to suppress corrosion by using BTA. Doing. However, in the case of using BTA in this way, unwanted defects are generated, and a mixture between copper and BTA is formed, which adversely affects the semiconductor device. On the contrary, if the BTA, which is a corrosion inhibitor, is not used, corrosion occurs in the copper wiring, which increases the resistance of the wiring or causes a short circuit when severe.
따라서, 본 발명은 다마신 패턴 내에 구리배선을 형성하기 위한 화학적 기계적 연마(CMP) 공정시 발생되는 구리배선의 부식을 방지하여 구리배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 구리배선 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention provides a method for forming a copper wiring of a semiconductor device that can improve the reliability of the copper wiring by preventing corrosion of the copper wiring generated during the chemical mechanical polishing (CMP) process for forming the copper wiring in the damascene pattern. Has its purpose.
도 1a 내지 1c는 본 발명의 실시예에 따른 반도체 소자의 구리배선 형성방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of devices for explaining a method of forming copper wirings of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 반도체 기판 12: 희생양극 접합부11: semiconductor substrate 12: sacrificial anode junction
13: 제 1 층간 절연막 14: 희생양극 콘택 플러그13: first interlayer insulating film 14: sacrificial anode contact plug
15: 희생양극 금속 패턴 16: 제 2 층간 절연막15: sacrificial anode metal pattern 16: second interlayer insulating film
17: 다마신 패턴 18: 구리확산방지 도전막17: damascene pattern 18: copper diffusion preventing conductive film
19: 구리층 189: 구리배선19: copper layer 189: copper wiring
이러한 목적을 달성하기 위한 본 발명의 실시예에 따른 반도체 소자의 구리배선 형성방법은 반도체 기판에 형성된 희생양극 접합부와 연결되는 희생양극 금속 패턴을 형성하는 단계; 상기 희생양극 금속 패턴을 포함한 전체 구조 상에 층간 절연막을 형성하는 단계; 상기 층간 절연막에 다마신 패턴을 형성하는 단계; 상기 다마신 패턴을 포함한 전체 구조상에 구리확산방지 도전막 및 구리층을 형성하는 단계; 및 화학적 기계적 연마 공정으로 상기 다마신 패턴 내에 구리배선을 형성하는 단계를 포함한다.According to an aspect of the present invention, there is provided a method of forming a copper wiring of a semiconductor device, the method including: forming a sacrificial anode metal pattern connected to a sacrificial anode junction formed on a semiconductor substrate; Forming an interlayer insulating film on the entire structure including the sacrificial anode metal pattern; Forming a damascene pattern on the interlayer insulating film; Forming a copper diffusion preventing conductive film and a copper layer on the entire structure including the damascene pattern; And forming a copper wiring in the damascene pattern by a chemical mechanical polishing process.
상기에서, 희생양극 금속 패턴은 상기 반도체 기판상에 형성된 층간 절연막을 관통하는 희생양극 콘택 플러그에 의해 상기 희생양극 접합부와 연결된다.In the above, the sacrificial anode metal pattern is connected to the sacrificial anode junction by a sacrificial anode contact plug passing through the interlayer insulating film formed on the semiconductor substrate.
상기 희생양극 접합부 및 상기 희생양극 금속 패턴은 다이와 다이 사이, 칩과 칩 사이의 경계지역인 스크라이브 레인 내에 형성한다.The sacrificial anode junction and the sacrificial anode metal pattern are formed in a scribe lane that is a boundary between the die and the die and the chip.
상기 희생양극 접합부는 P+이온주입으로 형성한다. 상기 희생양극 금속 패턴은 그 높이가 적어도 상기 층간 절연막의 증착 두께와 같거나 높도록 형성한다.The sacrificial anode junction is formed by P + ion implantation. The sacrificial anode metal pattern is formed such that its height is at least equal to or higher than the deposition thickness of the interlayer insulating film.
상기 화학적 기계적 연마 공정이 진행되어 상기 희생양극 금속 패턴이 노출되면서 희생양극 금속 패턴에만 부식이 일어난다.As the chemical mechanical polishing process proceeds to expose the sacrificial anode metal pattern, corrosion occurs only on the sacrificial anode metal pattern.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명함으로써, 본 발명을 상세하게 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예는 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, and to those skilled in the art the scope of the invention It is provided for complete information.
도 1a 내지 1c는 본 발명의 실시예에 따른 반도체 소자의 구리배선 형성방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of devices for describing a method of forming copper wirings in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(11)에 희생양극 접합부(12)를 형성한다. 희생양극 접합부(12)를 포함한 반도체 기판(11) 상에 제 1 층간 절연막(13)을 형성한다. 제 1 층간 절연막(13)의 일부분에 희생양극 접합부(12)와 연결되는 희생양극 콘택 플러그(14)를 형성한다. 금속층 증착 및 패터닝 공정으로 희생양극 콘택 플러그(14)에 연결되는 희생양극 금속 패턴(15)을 제 1 층간 절연막(13) 상에 형성한다. 희생양극 금속 패턴(15)을 포함한 제 1 층간 절연막(13) 상에 제 2 층간 절연막(16)을 형성한다. 다마신 공정으로 제 2 층간 절연막(16)에 다마신 패턴(17)을 형성한다. 다마신 패턴(17)을 포함한 전체 구조상에 구리확산방지 도전막(18) 및 구리층(19)을 형성한다.Referring to FIG. 1A, a sacrificial anode junction 12 is formed on a semiconductor substrate 11. A first interlayer insulating film 13 is formed on the semiconductor substrate 11 including the sacrificial anode junction 12. A sacrificial anode contact plug 14 connected to the sacrificial anode junction 12 is formed in a portion of the first interlayer insulating layer 13. A sacrificial anode metal pattern 15 connected to the sacrificial anode contact plug 14 is formed on the first interlayer insulating layer 13 by a metal layer deposition and patterning process. A second interlayer insulating film 16 is formed on the first interlayer insulating film 13 including the sacrificial anode metal pattern 15. A damascene pattern 17 is formed on the second interlayer insulating film 16 by a damascene process. The copper diffusion preventing conductive film 18 and the copper layer 19 are formed on the entire structure including the damascene pattern 17.
상기에서, 희생양극 접합부(12), 희생양극 콘택 플러그(14) 및 희생양극 금속 패턴(15)은 다이와 다이 사이(die to die), 칩과 칩 사이(chip to chip)의 경계지역인 스크라이브 레인(scribe lane)내에 형성된다. 희생양극 접합부(12)는 P+이온주입(P+implant)으로 형성한다. 희생양극 금속 패턴(15)은 알루미늄(Al)으로 형성하며, 그 높이가 적어도 제 2 층간 절연막(16)의 증착 두께와 같거나 높아야 한다. 제 2 층간 절연막(16)은 구리배선이 형성되는 부분으로 저유전 상수 값(low-k)을 갖는 절연물질이나, USG, TEOS, FSG, SOG, HSQ 등의 절연물질로 형성한다.In the above description, the sacrificial anode junction 12, the sacrificial anode contact plug 14, and the sacrificial anode metal pattern 15 are scribe lanes that are a die area between a die and a die and a chip to chip. (scribe lane) is formed. The sacrificial anode junction 12 is formed by P + ion implantation (P + implant). The sacrificial anode metal pattern 15 is made of aluminum (Al), and its height must be at least equal to or higher than the deposition thickness of the second interlayer insulating film 16. The second interlayer insulating film 16 is formed of an insulating material having a low dielectric constant (low-k) and an insulating material such as USG, TEOS, FSG, SOG, HSQ, and the like, in which a copper wiring is formed.
도 1b는 다마신 패턴(17) 내에 구리배선을 형성하기 위하여 화학적 기계적 연마 공정을 희생양극 금속 패턴(15)이 노출되는 시점까지 진행한 것을 도시한 것으로, 구리층(19), 구리확산방지 도전막(18) 및 희생양극 금속 패턴(15) 위의 제 2 층간 절연막(16) 순으로 연마되며, 희생양극 금속 패턴(15)이 노출되면서 구리층(19) 및 구리확산방지 도전막(18)은 부식되지 않고 희생양극 금속 패턴(15)에만 부식이 일어난다. 희생양극 금속 패턴(15)에 부식이 일어나는 원리를 간단히 설명하면 다음과 같다. 구리 다마신 공정은 구리층과 구리확산방지 도전막을 슬러리액을 사용한 연마 공정으로 평탄화를 이루어 다마신 패턴 내에 구리배선을 형성하는 공정으로 갈바니 전위(galvanic potential)가 상이한 이종의 금속막(metal film)이 수용액 중에서 발생되는 갈바니 부식(galvanic corrosion)이 발생되기 쉬운 공정이며, 일반적으로 갈바니 부식의 경우 이종의 금속 중 양극분극된 금속막에서 부식이 발생되므로, 희생양극 금속 패턴(15)이 희생양극 접합부(12)에 연결되어 있어 구리층(19)과 구리확산방지 도전막(18)에 대하여 양극분극을 형성하기 때문에 희생양극 금속 패턴(15)에 부식이 일어나게 된다.FIG. 1B illustrates that the chemical mechanical polishing process is performed until the sacrificial anode metal pattern 15 is exposed in order to form a copper wiring in the damascene pattern 17. The copper layer 19 and the copper diffusion preventing conductive layer are shown in FIG. The second interlayer insulating film 16 is polished in the order of the film 18 and the sacrificial anode metal pattern 15, and the copper layer 19 and the copper diffusion preventing conductive film 18 are exposed while the sacrificial anode metal pattern 15 is exposed. Silver does not corrode and corrosion only occurs in the sacrificial anode metal pattern 15. The principle that corrosion occurs in the sacrificial anode metal pattern 15 is briefly described as follows. The copper damascene process is a process in which a copper layer and a copper diffusion preventing conductive film are planarized using a slurry solution to form a copper wiring in a damascene pattern, and a different metal film having different galvanic potentials. Galvanic corrosion generated in this aqueous solution is a process that is easy to occur, and in general, galvanic corrosion occurs in the anodized metal film of different metals, so that the sacrificial anode metal pattern 15 is a sacrificial anode junction. Corrosion occurs in the sacrificial anode metal pattern 15 because the anode polarization is formed on the copper layer 19 and the copper diffusion preventing conductive film 18.
도 1c를 참조하면, 화학적 기계적 연마 공정을 계속 진행하여 다마신 패턴(17) 내에 구리배선(189)을 형성한다. 화학적 기계적 연마 공정이 진행되는 동안 희생양극 금속 패턴(15)에만 부식이 일어나고 구리배선(189)에는 부식이 일어나지 않는다.Referring to FIG. 1C, the chemical mechanical polishing process is continued to form the copper wiring 189 in the damascene pattern 17. During the chemical mechanical polishing process, only the sacrificial anode metal pattern 15 is corroded and the copper wiring 189 is not corroded.
상기한 본 발명의 실시예는 단층 배선 구조의 경우를 설명하였으나, 다층 배선 구조일 경우에도 본 발명의 원리를 그대로 적용할 수 있다. 간단히 설명하면, 희생양극 금속 패턴(15)에 연결되는 제 2의 희생양극 금속 패턴을 형성하는 공정부터 시작하여 다마신 기법으로 제 2의 구리배선을 형성하는 공정 순서로 진행하면된다.Although the embodiment of the present invention described above has been described in the case of a single layer wiring structure, the principle of the present invention can be applied as it is even in the case of a multilayer wiring structure. In brief, the process of forming the second copper wiring by the damascene technique may be performed starting with the process of forming the second sacrificial anode metal pattern connected to the sacrificial anode metal pattern 15.
상술한 바와 같이, 본 발명은 희생양극 금속 패턴을 이용한 구리층 및 구리확산방지 도전막의 부식을 방지할 수 있어, 기존의 BTA를 사용하지 않음에 따른 비용절감, BTA에 의한 결함(defect) 방지 등의 이점이 있으며, 구리배선의 신뢰성을 향상시킬 수 있다.As described above, the present invention can prevent corrosion of the copper layer and the copper diffusion preventing conductive film using the sacrificial anode metal pattern, thereby reducing the cost of not using the existing BTA, preventing defects due to the BTA, and the like. There is an advantage, and it is possible to improve the reliability of the copper wiring.
Claims (6)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100900227B1 (en) * | 2006-12-07 | 2009-05-29 | 주식회사 하이닉스반도체 | Method for forming metal interconnection layer of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100900227B1 (en) * | 2006-12-07 | 2009-05-29 | 주식회사 하이닉스반도체 | Method for forming metal interconnection layer of semiconductor device |
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