KR20050008884A - Method for manufacturing nmosfet - Google Patents
Method for manufacturing nmosfet Download PDFInfo
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- KR20050008884A KR20050008884A KR1020030047763A KR20030047763A KR20050008884A KR 20050008884 A KR20050008884 A KR 20050008884A KR 1020030047763 A KR1020030047763 A KR 1020030047763A KR 20030047763 A KR20030047763 A KR 20030047763A KR 20050008884 A KR20050008884 A KR 20050008884A
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- Prior art keywords
- manufacturing
- film
- nmos transistor
- ion implantation
- ions
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title claims description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 3
- -1 arsenic ions Chemical class 0.000 claims description 23
- 238000005468 ion implantation Methods 0.000 claims description 21
- 229910052698 phosphorus Inorganic materials 0.000 claims description 14
- 239000011574 phosphorus Substances 0.000 claims description 14
- 229910052785 arsenic Inorganic materials 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 9
- 230000003213 activating effect Effects 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229910052721 tungsten Inorganic materials 0.000 description 9
- 239000010937 tungsten Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- 229910052719 titanium Inorganic materials 0.000 description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- CTNCAPKYOBYQCX-UHFFFAOYSA-N [P].[As] Chemical compound [P].[As] CTNCAPKYOBYQCX-UHFFFAOYSA-N 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 콘택저항을 개선시킨 엔모스 트랜지스터의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method of manufacturing an NMOS transistor with improved contact resistance.
소자의 디멘젼(dimension)이 점점 감소함에 따라 트랜지스터의 채널길이(channel length)는 점점 짧아지고 소스/드레인 콘택의 크기는 점점 작아지고 있다. 그에 따라 숏채널효과(short channel effect)가 심화되어 소스/드레인간 펀치쓰루(punchthrough)가 발생하여 오프상태(off-state)에서도 전류가 흐르는 오프누설(off-leakage)이 발생하는 문제가 있으며, 콘택크기 감소로 콘택저항이 증가되는 문제가 발생하고 있다.As the dimension of the device decreases, the channel length of the transistor becomes shorter and the source / drain contact size becomes smaller. As a result, short channel effects are intensified to cause punchthrough between sources and drains, resulting in off-leakage in which current flows even in the off-state. There is a problem that the contact resistance is increased by reducing the contact size.
그리고, 채널길이가 감소하여 채널저항은 감소하지만 소스/드레인 콘택의 크기 감소로로 콘택저항은 증가하므로 트랜지스터의 총저항성분중 콘택저항이 차지하는 비중이 더욱 증가하고 있는 실정이며, 이러한 문제는 pMOSFET뿐만 아니라 nMOSFET에서도 치명적인 문제로 작용한다.In addition, as the channel length decreases, the channel resistance decreases, but the contact resistance increases due to the decrease in the size of the source / drain contacts. Therefore, the contact resistance portion of the total resistance components of the transistor is increasing. It is also a fatal problem for nMOSFETs.
따라서, 콘택홀의 크기가 매우 작아짐에 따라 소스/드레인영역 형성 및 콘택홀 형성후 추가 이온주입과정을 수행하여 콘택저항을 낮춘다. 이와 같은 추가 이온주입과정을 플러그 이온 주입(plug implantation) 공정이라고도 일컬으며, 일반적으로 반도체 소자의 금속 콘택 형성 공정에서 소스/드레인영역에 콘택홀을 형성한 후 금속 배선을 형성하기 전에 콘택 저항을 개선하기 위하여 소스/드레인영역과 동일한 형태의 도펀트로 추가 이온 주입 공정을 실시한다. 전술한 플러그 이온주입은 pMOSFET 제조시 주로 적용되고 있다.Therefore, as the size of the contact hole becomes very small, the contact resistance is lowered by performing additional ion implantation processes after forming the source / drain regions and forming the contact hole. This additional ion implantation process is also called a plug implantation process. In general, in the metal contact formation process of a semiconductor device, after forming contact holes in the source / drain regions, the contact resistance is improved before the metal wiring is formed. To do this, an additional ion implantation process is performed with the same type of dopant as the source / drain region. The above plug ion implantation is mainly applied in the manufacture of pMOSFETs.
한편, nMOSFET 제조시에는 소스/드레인영역을 형성할 때 비소(Asenic, As)와인(Phosphorous, P)을 혼합이온주입하여 콘택저항을 낮추었다.In the manufacture of nMOSFETs, contact resistance was lowered by implanting mixed ions with arsenic (Asenic, As) and (Phosphorous, P) when forming source / drain regions.
도 1은 종래 기술에 따른 엔모스 트랜지스터의 제조 방법을 개략적으로 도시한 도면이다.1 is a view schematically showing a manufacturing method of the NMOS transistor according to the prior art.
도 1을 참조하면, 반도체 기판(11) 상에 게이트산화막(12)과 게이트전극(13)을 패터닝을 통해 형성한 후, 게이트전극(13) 및 게이트산화막(12)의 양측벽에 스페이서(14)를 형성한다. 그리고 나서, 비소(As) 이온과 인(P) 이온을 혼합하여 스페이서 외측의 반도체 기판에 이온주입하므로써 n+소스/드레인영역(15)을 형성한다.Referring to FIG. 1, after the gate oxide film 12 and the gate electrode 13 are formed on the semiconductor substrate 11 by patterning, spacers 14 are formed on both sidewalls of the gate electrode 13 and the gate oxide film 12. ). Then, arsenic (As) ions and phosphorus (P) ions are mixed and ion implanted into the semiconductor substrate outside the spacer to form the n + source / drain region 15.
전술한 종래 기술은 콘택저항 감소에는 탁월한 효과를 발휘하나, 중량이 가벼운 인(P)이 후속 열처리중에 급속히 확산하여 게이트전극(13) 아래의 채널로 침투하기 쉽다. 이처럼 인(P)이 채널로 침투하게 되면, 펀치쓰루를 억제하기위한 전압 감소, 오프누설 증가, GIDL(Gate Induced Drain leakage) 증가 등의 숏채널효과 마진이 감소하는 문제가 발생한다.The above-mentioned prior art has an excellent effect on reducing contact resistance, but lighter phosphorus (P) is easily diffused during the subsequent heat treatment and easily penetrates into the channel under the gate electrode 13. As such, when the in (P) penetrates into the channel, short channel effect margins such as voltage reduction, off leakage, and GIDL (Gate Induced Drain Leakage) to reduce punch through occur.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 안출한 것으로, 콘택홀 크기가 작아짐에 따른 콘택저항 증가를 억제하면서 숏채널효과 마진 저하를 방지하는데 적합한 엔모스 트랜지스터의 제조 방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above-mentioned problems of the prior art, and provides a method of manufacturing an NMOS transistor suitable for preventing a short channel effect margin from falling while suppressing an increase in contact resistance due to a decrease in contact hole size. There is this.
도 1은 종래 기술에 따른 엔모스 트랜지스터의 제조 방법을 개략적으로 도시한 도면,1 is a view schematically showing a manufacturing method of an NMOS transistor according to the prior art;
도 2a 내지 도 2c는 본 발명의 실시예에 따른 엔모스 트랜지스터의 제조 방법을 도시한 공정 단면도.2A to 2C are cross-sectional views illustrating a method of manufacturing an NMOS transistor according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : p형 웰21 semiconductor substrate 22 p-type well
23 : 게이트산화막 24 : 게이트전극23: gate oxide film 24: gate electrode
25 : 스페이서 26 : n+소스/드레인영역25: spacer 26: n + source / drain region
27 : 층간절연막 28 : 감광막패턴27 interlayer insulating film 28 photosensitive film pattern
29 : 콘택홀 30 : 비소-인 혼합영역29 contact hole 30 arsenic-in mixed region
상기 목적을 달성하기 위한 본 발명의 엔모스 트랜지스터의 제조 방법은 반도체 기판 상에 게이트산화막과 게이트전극을 차례로 형성하는 단계, 상기 게이트전극의 양측벽에 스페이서를 형성하는 단계, 상기 스페이서 외측의 상기 반도체 기판에 비소 이온을 이온주입하여 고농도 소스/드레인영역을 형성하는 단계, 상기 반도체 기판의 전면에 층간절연막을 형성하는 단계, 상기 소스/드레인영역의 일부 표면을 노출시키도록 상기 층간절연막을 식각하여 콘택홀을 형성하는 단계, 상기 콘택홀내에 노출된 상기 소스/드레인영역의 일부 표면에 인 이온을 이온주입하는 단계, 및 상기 콘택홀을 채우는 플러그를 형성하는 단계를 포함하는 것을 특징으로 하고, 상기 비소 이온의 이온 주입시, 도즈는 1E15ions/cm2∼4E15ions/cm2이고 이온주입에너지는 10keV∼30keV 범위인 것을 특징으로 하며, 상기 인 이온의 이온 주입시, 도즈는 1E15ions/cm2∼4E15ions/cm2이고 이온주입에너지는 10keV∼30keV 범위인 것을 특징으로 한다.In the method of manufacturing the NMOS transistor of the present invention for achieving the above object, the step of sequentially forming a gate oxide film and a gate electrode on a semiconductor substrate, forming a spacer on both side walls of the gate electrode, the semiconductor outside the spacer Implanting arsenic ions into the substrate to form a high concentration source / drain region, forming an interlayer insulating film on the entire surface of the semiconductor substrate, and etching the interlayer insulating film to expose a part of the surface of the source / drain region. Forming a hole, implanting phosphorus ions into a portion of the source / drain region exposed in the contact hole, and forming a plug filling the contact hole; When implanting ions, the dose is 1E15ions / cm 2 to 4E15ions / cm 2 and the ion implantation energy is 10 keV to 30 ke It is characterized in that the V range, the ion implantation of the phosphorus ion, the dose is 1E15ions / cm 2 ~ 4E15ions / cm 2 and the ion implantation energy is characterized in that the range of 10keV ~ 30keV.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2c는 본 발명의 실시예에 따른 엔모스 트랜지스터(nMOSFET)의 제조 방법을 도시한 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing an nMOSFET according to an embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체 기판(21)에 붕소(Boron) 이온 또는 붕소 이온을 포함하는 붕소화합물 이온(BF2)을 이온주입하여 p형 웰(22)을 형성한 후, 반도체 기판(21) 상에 게이트산화막(23)과 게이트전극(24)을 형성한다.As illustrated in FIG. 2A, boron ions or boron ions (BF 2 ) containing boron ions are ion-implanted into the semiconductor substrate 21 to form a p-type well 22, and then a semiconductor substrate ( A gate oxide film 23 and a gate electrode 24 are formed on 21.
이때, 게이트산화막(23)으로는 열산화막, 질화산화막(oxynitride), 고유전막 또는 산화막/고유전막의 적층막중에서 하나를 선택하여 사용한다. 그리고, 게이트전극(24)은 폴리실리콘막, 폴리실리콘막과 실리사이드의 적층막, 폴리실리콘막과 금속막의 적층막, 실리콘게르마늄막, 실리콘게르마늄막과 금속막의 적층막 또는 금속막중에서 하나를 선택하여 사용하며, 실리콘질화막과 같은 하드마스크(hard mask)를 최상부에 포함할 수 있다.At this time, the gate oxide film 23 is selected from a thermal oxide film, an oxynitride film, a high dielectric film, or a laminated film of an oxide film / high dielectric film. The gate electrode 24 is selected from among a polysilicon film, a polysilicon film and a silicide lamination film, a polysilicon film and a metal film lamination film, a silicon germanium film, a silicon germanium film and a metal film lamination film, or a metal film. In this case, a hard mask such as a silicon nitride film may be included on the top.
다음으로, 반도체 기판(21) 상부에 절연층을 증착한 후, 전면식각을 진행하여 게이트전극(24)의 양측벽에 스페이서(25)를 형성한다. 이때, 스페이서(25)를 형성하는 절연층은 실리콘질화막, 실리콘산화막 또는 실리콘질화막과 실리콘산화막의 조합을 이용한다.Next, after the insulating layer is deposited on the semiconductor substrate 21, the entire surface is etched to form spacers 25 on both sidewalls of the gate electrode 24. At this time, the insulating layer forming the spacer 25 uses a silicon nitride film, a silicon oxide film or a combination of a silicon nitride film and a silicon oxide film.
한편, 스페이서(25)를 형성하기 전에 통상 LDD(Lightly Doped Drain) 영역이라고 일컫는 저농도 소스/드레인영역을 형성할 수 있다.Before forming the spacer 25, a low concentration source / drain region, commonly referred to as a lightly doped drain (LDD) region, may be formed.
그 다음, 스페이서(25) 외측의 반도체 기판(21)에 비소 이온(71As)을 이온주입하여 n+소스/드레인영역(26)을 형성한 후, 어닐링하여 n+소스/드레인영역(26) 내에 주입된 비소 이온을 전기적으로 활성화시킨다.Next, arsenic ions 71As are implanted into the semiconductor substrate 21 outside the spacer 25 to form n + source / drain regions 26, and then annealed to form n + source / drain regions 26. The implanted arsenic ions are electrically activated.
여기서, 비소 이온 주입시, 도즈(dose)는 1E15ions/cm2∼4E15ions/cm2이고 이온주입에너지는 10keV∼30keV 범위이며, 활성화를 위한 어닐링은 RTP(Rapid Thermal Process)를 이용한다. 여기서, RTP는 실리콘의 용융점인 1414℃보다 낮으면서 비소-인 혼합 영역(30)에 주입된 도펀트를 활성화시키는 온도, 예컨대 750℃∼1100℃의 범위에서 진행한다.Here, in arsenic ion implantation, the dose is 1E15ions / cm 2 to 4E15ions / cm 2, and the ion implantation energy is in the range of 10 keV to 30 keV, and annealing for activation uses RTP (Rapid Thermal Process). Here, RTP proceeds at a temperature for activating the dopant injected into the arsenic-phosphorus mixing region 30 while being lower than 1414 ° C, which is the melting point of silicon, for example, in the range of 750 ° C to 1100 ° C.
도 2b에 도시된 바와 같이, 반도체 기판(21) 상부에 층간절연막(27)을 증착한다. 이때, 층간절연막(27)은 실리콘산화막 또는 실리콘질화막 상부에 갭필(Gapfill)용 BPSG(Boro Phospho Silicate Glass), HDP CVD(High Density Plasma Chemical Vapor Deposition)막 또는 저유전율막 등이 적층된 막이다.As shown in FIG. 2B, an interlayer insulating film 27 is deposited on the semiconductor substrate 21. In this case, the interlayer insulating layer 27 is a layer in which a BPSG (Bap Phospho Silicate Glass) for gap fill, a High Density Plasma Chemical Vapor Deposition (HDP CVD) film, or a low dielectric constant film is stacked on the silicon oxide film or the silicon nitride film.
다음에, 층간절연막(27) 상에 n+소스/드레인영역(26)을 노출시키기 위한 감광막 패턴(28)을 공지의 포토리소그래피 방식에 의하여 형성한다.Next, a photosensitive film pattern 28 for exposing the n + source / drain regions 26 is formed on the interlayer insulating film 27 by a known photolithography method.
다음으로, 감광막 패턴(28)을 식각마스크로 층간절연막(27)을 식각하여 콘택홀(29)을 형성한다.Next, the interlayer insulating layer 27 is etched using the photoresist pattern 28 as an etch mask to form the contact hole 29.
이어서, 감광막패턴(28)을 잔류시킨 상태에서 인(31P) 이온을 이온주입하여 n+소스/드레인 영역(26) 내에 국부적으로 이온주입영역(30)을 형성한 후, 이온주입영역(30)에 주입된 인 이온을 전기적으로 활성화시키기 위한 어닐링을 진행한다. 이때, 이온주입영역(30)은 비소이온과 인이온이 혼합된 영역이므로, 이하 비소-인 혼합영역(30)이라고 약칭한다.Subsequently, phosphorus (31P) ions are ion implanted while the photoresist pattern 28 is left to form the ion implantation region 30 locally in the n + source / drain region 26, followed by ion implantation region 30. The annealing is performed to electrically activate the phosphorus ions implanted in the. At this time, since the ion implantation region 30 is a region in which arsenic ions and phosphorus ions are mixed, hereinafter referred to as arsenic-phosphorus mixing region 30.
전술한 인이온의 이온주입이 n+소스/드레인영역(26) 상부를 오픈시키는 콘택홀(29) 지역에만 국부적으로 진행되므로 n+소스/드레인영역(26)의 전영역에 걸쳐 비소-인 혼합영역(30)이 형성되지 않는다. 따라서, 비소-인 혼합영역(30)은 콘택저항 감소의 효과를 구현한다.Over the entire region of the ion implantation of phosphorus ions the above-described n + source / drain region contact hole 29, so only the process proceeds to a local area n + source / drain region 26 to 26 is open to an upper non-small-mix The region 30 is not formed. Thus, the arsenic-in mixed region 30 realizes the effect of reducing contact resistance.
한편, 인 이온 주입시, 도즈(dose)는 1E15ions/cm2∼4E15ions/cm2이고 이온주입에너지는 10keV∼30keV 범위이며, 활성화를 위한 어닐링은 RTP(Rapid Thermal Process)를 이용한다. 여기서, RTP는 실리콘의 용융점인 1414℃보다 낮으면서 비소-인 혼합 영역(30)에 주입된 도펀트를 활성화시키는 온도, 예컨대 750℃∼1100℃의 범위에서 진행한다.On the other hand, during phosphorus ion implantation, the dose is 1E15ions / cm 2 to 4E15ions / cm 2, and the ion implantation energy is in the range of 10 keV to 30 keV, and annealing for activation uses a rapid thermal process (RTP). Here, RTP proceeds at a temperature for activating the dopant injected into the arsenic-phosphorus mixing region 30 while being lower than 1414 ° C, which is the melting point of silicon, for example, in the range of 750 ° C to 1100 ° C.
도 2c에 도시된 바와 같이, 감광막패턴(28)을 제거한 후 콘택홀(29)의 프로파일을 따라 배리어막을 증착한다. 이때, 배리어막은 티타늄막(31)과 티타늄나이트라이드막(32)을 차례로 형성한 것으로, 티타늄막(31)은 오믹콘택(ohmic contact)을 형성해주기 위한 것이고, 티타늄나이트라이드막(32)은 후속 플러그와 n형 소스/드레인영역간 상호확산을 방지하기 위한 확산방지막이다.As illustrated in FIG. 2C, the barrier layer is deposited along the profile of the contact hole 29 after removing the photoresist pattern 28. At this time, the barrier film is formed by sequentially forming the titanium film 31 and the titanium nitride film 32, the titanium film 31 is for forming an ohmic contact, the titanium nitride film 32 is subsequently Diffusion barrier to prevent interdiffusion between plug and n-type source / drain regions.
여기서, 배리어막으로 사용된 티타늄막(31)외에도 코발트막(Co) 또는 니켈막(Ni)을 이용하고, 티타늄나이트라이드막(32)외에 텅스텐나이트라이드막(WN)을 이용할 수 있다.Here, a cobalt film Co or a nickel film Ni may be used in addition to the titanium film 31 used as the barrier film, and a tungsten nitride film WN may be used in addition to the titanium nitride film 32.
한편, 티타늄나이트라이드막(32)은 티타늄막(31)이 대기 중에 노출되는 것을 방지하여 장기간 노출에 따른 자연 산화막의 형성 및 오염원의 발생으로부터 티타늄막(30)을 보호하는 역할도 한다.On the other hand, the titanium nitride film 32 prevents the titanium film 31 from being exposed to the atmosphere, thereby protecting the titanium film 30 from the formation of a natural oxide film and the generation of pollutants due to prolonged exposure.
다음으로, 어닐링 공정을 진행하여 티타늄막(31)과 비소-인 혼합영역(30)의 실리콘원자가 반응하여 티타늄실리사이드막(33)을 형성한다. 전술한 바와 같은 어닐링 공정은, 500℃∼1100℃에서 NH3, Ar, N2또는 N2O 분위기로 5초∼1000초동안 실시한다. 위와 같은 티타늄실리사이드막(33)을 형성하므로써 오믹콘택을 형성한다.Next, an annealing process is performed to form a titanium silicide layer 33 by reacting the silicon atoms of the titanium layer 31 and the arsenic-phosphorus mixed region 30 with each other. The annealing process as described above is performed at 500 ° C to 1100 ° C for 5 seconds to 1000 seconds in an NH 3 , Ar, N 2 or N 2 O atmosphere. The ohmic contact is formed by forming the titanium silicide layer 33 as described above.
다음으로, 티타늄나이트라이드막(32) 상에 콘택홀을 채울때까지 텅스텐막을 증착한 후, 콘택홀을 제외한 부분의 텅스텐막과 티타늄나이트라이드막(32) 및 티타늄막(31)을 제거하여 콘택홀에 매립되는 텅스텐플러그(34)를 형성한다.Next, after the tungsten film is deposited on the titanium nitride film 32 until the contact hole is filled, the tungsten film, the titanium nitride film 32 and the titanium film 31 except the contact hole are removed, and the contact is removed. A tungsten plug 34 embedded in the hole is formed.
텅스텐플러그(34)를 형성하기 위한 다양한 방법을 설명하면 다음과 같다. 제1방법은 에치백을 통해 텅스텐막과 배리어메탈을 한번의 에치백 공정을 통해 형성하거나, 텅스텐막을 화학적기계적연마(CMP)를 통해 평탄화한 후 에치백을 통해 배리어메탈을 제거하여 형성하거나, 텅스텐막과 배리어메탈을 한번에 화학적기계적연마하여 형성할 수 있다.Hereinafter, various methods for forming the tungsten plug 34 will be described. In the first method, the tungsten film and the barrier metal are formed through an etch back through a single etch back process, or the tungsten film is planarized through chemical mechanical polishing (CMP) and then the barrier metal is removed through the etch back. The film and barrier metal can be formed by chemical mechanical polishing at once.
전술한 실시예에서는 텅스텐플러그(34)를 예로 들었으나, 콘택물질로 알루미늄(Al), 알루미늄합금, 구리(Cu) 또는 구리합금 등의 금속막을 이용할 수도 있다.In the above embodiment, the tungsten plug 34 is taken as an example, but a metal film such as aluminum (Al), aluminum alloy, copper (Cu), or copper alloy may be used as the contact material.
전술한 실시예에 따르면, n+소스/드레인영역(26)을 비소 이온만을 이온주입하여 형성하므로 숏채널효과 마진이 우수하고, 텅스텐플러그(34)와 접하는 콘택지역에 국부적으로 인 이온을 주입하여 비소-인 혼합영역(30)을 형성하므로써 콘택저항을 현저히 감소시킨다.According to the above embodiment, since the n + source / drain region 26 is formed by ion implantation of only arsenic ions, the short channel effect margin is excellent, and phosphorus ions are locally injected into the contact region in contact with the tungsten plug 34. By forming the arsenic-phosphorus mixed region 30, the contact resistance is significantly reduced.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 콘택지역에만 비소-인 혼합영역을 형성하므로써 숏채널효과 마진의 저하없이 콘택저항을 감소시켜 소자의 전기적 특성을 향상시킬 수 있는 효과가 있다.The present invention described above has the effect of improving the electrical characteristics of the device by reducing the contact resistance without reducing the short channel effect margin by forming the arsenic-phosphorous mixed region only in the contact region.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100854892B1 (en) * | 2006-10-31 | 2008-08-28 | 주식회사 하이닉스반도체 | Method of manufacturing a high voltage device |
| CN103367148A (en) * | 2012-03-29 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Transistor and manufacturing method thereof |
| CN103378149A (en) * | 2012-04-20 | 2013-10-30 | 中国科学院微电子研究所 | Mosfet and manufacturing method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100854892B1 (en) * | 2006-10-31 | 2008-08-28 | 주식회사 하이닉스반도체 | Method of manufacturing a high voltage device |
| CN103367148A (en) * | 2012-03-29 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Transistor and manufacturing method thereof |
| CN103367148B (en) * | 2012-03-29 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | Transistor and manufacture method thereof |
| CN103378149A (en) * | 2012-04-20 | 2013-10-30 | 中国科学院微电子研究所 | Mosfet and manufacturing method thereof |
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