KR20050007631A - Method for forming a dual damascene pattern in semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a dual damascene pattern of a semiconductor device is provided to improve reliability of a metal interconnection by controlling a sidewall fence generated in a process for forming a dual damascene pattern. CONSTITUTION: An interlayer dielectric is formed on a semiconductor substrate(10) having an underlying layer. A capping layer is formed on the interlayer dielectric. The capping layer and the interlayer dielectric are patterned to form a via hole by an etch process using an etch mask for forming a via hole. An organic BARC(bottom anti-reflective coating) is deposited on the resultant structure to fill the via hole. The organic BARC and the capping layer are etched to expose the interlayer dielectric formed between adjacent via holes by an etch process using an etch mask for forming a trench(30). An etch process is performed at least twice by using the etch mask for forming the trench, so as to recess the organic BARC and the interlayer dielectric formed between the via holes. The remaining organic BARC is eliminated to form the trench.

Description

Method for forming a dual damascene pattern in semiconductor device

The present invention relates to a method for forming a dual damascene pattern of a semiconductor device, and in particular, to control the sidewall fence generated in a pre-via dual damascene process to improve the reliability of metal wiring. It relates to a method of forming a drank pattern.

In a semiconductor device or an electronic device, a conductor film such as aluminum (Al) or tungsten (W) is deposited on an insulating film as a metal wiring forming technique, and then the conductor film is subjected to a conventional photolithography process and dry etching ( The technique of forming metal wiring by patterning through dry etching process has been established and widely used in this field. In particular, recently, a method of using a low-resistance metal such as copper (Cu) instead of aluminum or tungsten as wiring to reduce the RC delay centering on logic devices requiring high integration and high performance among semiconductor devices has recently been used. Is being studied. In RC, 'R' represents wiring resistance, and 'C' represents dielectric constant of the insulating film.

In the metallization process using copper, the patterning process is more difficult than aluminum or tungsten. Accordingly, a so-called 'damascene' process is used in which a trench is first formed and a metal wiring is formed to fill the trench. Currently commonly used processes include the single damascene process and the dual damascene process. The single damascene process is a method of forming a via hole and then filling the via hole with a conductive material, forming a wiring trench on the upper portion thereof, and then filling the trench with a wiring material to form a metal wiring. The dual damascene process is a method for forming metal vias by forming via holes and wiring trenches and then filling the wiring material with via holes and wiring trenches at the same time. Based on the damascene process, various metal wire forming methods have been proposed.

However, in the metal wiring forming processes using the damascene process described above, many problems arise due to the limitation of the overlay capability of the exposure apparatus. In particular, there is a limit in lamination capability in the metallization formation process of a high-performance semiconductor device of 0.13 μm or less. For example, in the case of via mask patterning after the etching process for forming the trench, a large number of problems may occur, such as the formation of the via mask becomes very difficult due to the diffuse reflection at the edge of the trench. In addition, a facet phenomenon is generated as shown in FIG. 9 due to the use of a film having a low dielectric constant as the interlayer insulating film, and the use of an etch stopping layer.

In order to overcome these problems, a pre-via method is used. However, as in the sidewall fence (see 'A') shown in FIGS. 10A to 10C, a via hole after dry etching to form a trench is shown. The organic BARC (Bottom AntiReflection Coating) filled on the surface remains as spacers are formed. Here, FIG. 10A is a SEM photograph showing the sidewall fence generated when the trench is completely etched. FIG. 10B is a SEM photograph illustrating a sidewall fence generated when the trench is partially etched. FIG. FIG. 10C is a SEM photograph illustrating sidewall fences generated after removing the photoresist pattern, which is an etching mask for forming trenches, after the trench is formed in FIG. 10A or 10B.

The sidewall fence is not removed well after the process such as RF sputter, which is a subsequent process, and thus causes instability in the barrier film / seed layer forming process and the copper electroplating process when forming the metal wiring. This reduces the reliability of the copper wiring. The side wall fence 1 may be removed through an etching process using a mixed gas including O ₂ gas or the like. However, when the etching process is performed using a mixed gas containing O ₂ gas or the like, sidewalls of a photoresist pattern, which is a trench forming mask, are also lost. Sidewall loss of such photoresist patterns eventually leads to damage of the tops of the trenches and, in severe cases, to bridges with the tops of adjacent trenches.

Therefore, a preferred embodiment of the present invention is to improve the reliability of the metal wiring by controlling the side wall fence generated in the sun via dual damascene process.

1 to 8 are cross-sectional views illustrating a method for forming a dual damascene pattern of a semiconductor device according to an exemplary embodiment of the present invention.

9 is a transmission electron microscope (TEM) photograph in which a facet phenomenon is generated by a dual damascene pattern forming process according to the related art.

10A to 10C are scanning electron microscope (SEM) photographs showing sidewall fences generated by a dual damascene pattern forming process according to the prior art.

<Explanation of symbols for main parts of drawing>

10 semiconductor substrate 12 semiconductor structure layer

14: first interlayer insulating film 16: lower metal wiring

18 diffusion barrier film 20 second interlayer insulating film

22: capping layer 24: via hole

26: photoresist pattern 28: organic BARC

30: trench

According to an aspect of the present invention, the cap is formed by forming an interlayer insulating film on a semiconductor substrate on which an underlayer is formed, forming a capping layer on the interlayer insulating film, and an etching process using a via hole forming etching mask. Forming a via hole by patterning the ping layer and the interlayer insulating layer, depositing an organic BARC on the entire structure to fill the via hole, and etching the trench forming mask to expose the interlayer insulating layer formed between the adjacent via holes. Etching the organic BARC and the capping layer through an etching process, and performing an etching process at least twice using an etching mask for forming the trench to remove the interlayer insulating layer formed between the organic BARC and the via hole. A trench that is recessed and the organic BARC remaining in the step is removed The dual damascene patterning method of a semiconductor device including a step to be formed is provided.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1 to 8 are cross-sectional views illustrating a method for forming a dual damascene pattern of a semiconductor device according to an exemplary embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 1 to 8 are the same components having the same function.

Referring to FIG. 1, a semiconductor substrate 10 having a predetermined semiconductor structure layer 12 formed thereon is provided. The semiconductor structure layer 12 may include a transistor, a memory cell, a capacitor, a junction layer, a conductive layer, and the like. Subsequently, on the semiconductor structure layer 12, as a low dielectric material, for example, PLAEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate), USG (Un-doped Silicate Glass), FSG (Fluorinated Silicate Glass), silicon oxide, fluorine-containing silicon oxide Alternatively, an insulating film (hereinafter referred to as 'first interlayer insulating film') 14 is deposited using fluorine-containing oxide or the like. In general, fluorine-containing silicon oxide has a lower dielectric constant than silicon oxide, and the dielectric constant can be controlled by adjusting the fluorine content.

Subsequently, a lithography process is performed to form contact holes (not shown) in the first interlayer insulating layer 14, and lower metal wirings 16 are sequentially formed to fill the contact holes. At this time, the lower metal wiring 16 is any one of copper, tungsten, Al, Pt (Platinum), Pd (Palladium), Ru (Rubidium), St (Strontium), Rh (Rhadium) and Co. Meanwhile, a barrier film may be formed on an inner surface of the contact hole before the lower metal wiring 16 is deposited. In this case, the barrier film may include Ta, TaN, TaAlN, TaSiN, TaSi ₂ , Ti, TiN, TiSiN, WN, Co. And CoSi ₂ .

Referring to FIG. 2, after the lower metal wiring 16 is formed in FIG. 1, the diffusion barrier 18 is formed on the entire structure. At this time, the diffusion barrier 18 is formed to a thickness of 300 Å to 1000 Å. Thereafter, a second interlayer insulating film 20 is formed on the diffusion barrier film 18. The second interlayer insulating film 20 may be formed of a PETEOS, USG, FSG, or a film in which fluorine, hydrogen, boron, phosphorus, or the like is locally bonded or interstitial to SiO or SiO ₂ . Thereafter, the first interlayer insulating film 20 may be planarized through a CMP process. Afterwards, a capping layer 22 is formed on the first interlayer insulating layer 20. In this case, the capping layer 22 may include at least a single layer or a composite structure of a carbon-containing carbon film such as a nitride film (eg, silicon nitride film), a nitride oxide film (eg, silicon nitride oxide film), or SiC. In this case, the capping layer 22 is formed of 50 kPa to 1000 kPa. Here, when the capping layer 22 is formed of silicon nitride (SiN) or silicon oxynitride (SiON), the antireflection effect is incidentally obtained to reduce the thickness of the organic BARC 26 (see FIG. 4) formed through a subsequent process. You can.

Referring to FIG. 3, after the capping layer 22 is formed in FIG. 2, a dual damascene process is performed by a sun via method. First, a photoresist is coated on the entire structure, and then an exposure process and a development process using a photomask are sequentially performed to form a via hole forming etching mask in which a part of the capping layer 22 is exposed. A photoresist pattern (not shown) is formed. Next, the via hole 24 is formed by sequentially etching the capping layer 22 and the second interlayer insulating layer 20 exposed by performing an etching process using the photoresist pattern as an etching mask. The etching process uses C _x H _y F _z (x, y, z is 0 or natural water) gas as the main etching gas, and inert gas atoms or molecules such as O ₂ , N ₂ , Ar or He It is carried out using as an additive gas. In this case, increasing the ratio of 'x' in the main etching gas C _x H _y F _z , or decreasing the ratio of the additive gas increases the selectivity to the capping layer 22, for example, SiC. In addition, by increasing the ratio of the additive gas or increasing the ratio of 'y', 'z' in the main etching gas C _x H _y F _z can lower the selectivity for the capping layer 22, for example, SiC, In SiC dry etching, the selectivity to the second interlayer insulating film 20, for example, SiOC, may increase the selectivity.

4 and 5, after the via hole 24 is formed in FIG. 3, the organic BARC 26 is deposited on the entire structure such that the via hole 24 is embedded. Then, after the photoresist is completely coated on the entire structure, the photoresist pattern 26 for forming a trench is formed by sequentially performing an exposure process and a development process using a photomask. Then, the organic BARC 28 exposed by performing the etching process using the photoresist pattern 26 as an etching mask by dry etching is etched. In this case, the etching process uses O ₂ , N ₂ or He as the main etching gas. Then, as a primary etching process for forming the trench 30 (see FIG. 8), C _x H _y F _z (x, y, z is 0 or natural water) gas is used as the main etching gas, O ₂ , It is carried out using an inert gas atom or molecule such as N ₂ , Ar or He as an additive gas. At this time, the primary etching process is preferably performed to be 10% to 90% of the depth of the target trench (30). As a result, the organic BARC 28 is recessed. Through this process, a profile as shown in FIG. 5 is obtained.

Referring to FIG. 6, after the primary etching process is completed in FIG. 5, the organic BARC 28 is partially recessed through the etching process to prevent the formation of the sidewall fence. In this case, the etching process uses O ₂ , N ₂ or He as the main etching gas. Accordingly, the top and sidewalls of the photoresist pattern 26 are also partially etched. Through this process, a profile as shown in FIG. 6 is obtained.

Referring to FIG. 7, a second etching process is then performed. In the secondary etching process, C _x H _y F _z (x, y, z is 0 or natural water) gas is used as the main etching gas, and an inert gas atom or molecule such as O ₂ , N ₂ , Ar or He is added. It is carried out using gas. Through this process, a profile as shown in FIG. 7 is obtained.

Referring to FIG. 8, after the secondary etching process is completed in FIG. 7, the organic BARC 28 remaining in the via hole 24 and the diffusion barrier layer 18 formed under the remaining organic BARC 28 through the etching process. ) Is removed. At this time, the capping layer 22 is partially or completely removed. As a result, the upper metal wiring (not shown) and the lower metal wiring 16 formed through a subsequent process are connected.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, it is possible to suppress the occurrence of sidewall fences generated in the sun via method during the dual damascene pattern forming process, thereby improving the reliability of the metal wiring.

Claims (7)

(a) forming an interlayer insulating film on the semiconductor substrate on which the underlayer is formed; (b) forming a capping layer on the interlayer insulating film; (c) forming a via hole by patterning the capping layer and the interlayer insulating layer through an etching process using a via hole forming etching mask; (d) depositing an organic BARC over the entire structure to fill the via holes; (e) etching the organic BARC and the capping layer through an etching process using an etching mask for forming a trench to expose the interlayer insulating layer formed between the adjacent via holes; (f) recessing the interlayer insulating layer formed between the organic BARC and the via hole by performing an etching process at least twice using the trench forming etching mask; And (g) forming a trench by removing the organic BARC remaining in the step (f) to form a trench. The method of claim 1, The capping layer is a method of forming a dual damascene pattern of a semiconductor device in which a nitride film, a nitride oxide film or a carbon containing carbon film is formed in a single layer or a composite structure in which these layers are stacked. The method of claim 1, In the step (c), the etching process uses C _x H _y F _z (x, y, z is 0 or natural water) gas as the main etching gas, and an inert gas atom of O ₂ , N ₂ , Ar or He or A method of forming a dual damascene pattern of a semiconductor device by using a molecule as an additive gas. The method of claim 1, In the step (e), the etching process is a dual damascene pattern forming method of a semiconductor device using O ₂ , N ₂ or He as the main etching gas. The method of claim 1, In the step (f), the etching process uses C _x H _y F _z (x, y, z is 0 or natural water) gas as the main etching gas, and an inert gas atom of O ₂ , N ₂ , Ar, or He or A method of forming a dual damascene pattern of a semiconductor device by using a molecule as an additive gas. The method of claim 1, The first etching process of the etching step in the step (f) is a dual damascene pattern forming method of the semiconductor device is carried out to be 10% to 90% of the depth of the trench target value. The method of claim 1, In the step (f), the etching process further comprises the step of partially etching the organic BARC using O ₂ , N ₂ or He as the main etching gas.