KR20050002565A - Method of construction of line number on pad for liquid crystal display device - Google Patents

Abstract

PURPOSE: An array substrate for a COG(Chip On Glass) type LCD(Liquid Crystal Display) and a method for forming line numbers are provided to easily differentiate respective gate lines and respective data lines by engraving respective numbers on respective gate pads and respective data pads. CONSTITUTION: A plurality of gate lines(114) are formed on a substrate, and a plurality of gate pads(110) are respectively connected to the respective gate lines. Respective numbers(120) of the gate lines are respectively engraved on respective gate pads. A plurality of data pads are respectively connected to the respective data lines. Respective numbers of the data lines are respectively engraved on respective data pads. A plurality of thin film transistors are formed at the cross points of the gate lines and the data lines. Drivers are electrically connected to respective gate pads and data pads.

Description

Method of construction of line number on pad for liquid crystal display device

The present invention relates to a liquid crystal display device, and more particularly, to a method of forming a wiring number on a gate pad and a data pad of a COG mounting structure liquid crystal display device.

Recently, with the rapid development of the information society, there is a need for a flat panel display having excellent characteristics such as thinness, light weight, and low power consumption. It is excellent in color display and image quality, and is actively applied to notebooks and desktop monitors.

In general, a liquid crystal display device arranges two substrates on which electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injects a liquid crystal material between the two substrates, and applies a voltage to the two electrodes to generate an electric field. By moving the liquid crystal molecules, the image is expressed by the transmittance of light that varies accordingly.

The liquid crystal display includes a liquid crystal panel in which liquid crystal is injected between two substrates, a backlight disposed under the liquid crystal panel and used as a light source, and a driving unit for driving the liquid crystal panel, which is located outside the liquid crystal panel.

Here, the driving unit includes a driving circuit (hereinafter referred to as a drive integrated circuit (IC)) for applying a signal to the wiring of the liquid crystal panel. According to a method of packaging the drive IC on the liquid crystal panel, the chip on glass (COG: chip on glass), tape carrier package (TCP), chip on film (COF).

The COG method is a method of directly attaching a driver IC to an array substrate of a liquid crystal display device and directly connecting an output electrode of the driver IC to a wiring pad on the array substrate. The COG method is simple in structure and simple in manufacturing. There is an advantage.

An array substrate structure of a liquid crystal display device formed by such a COG method is briefly shown in FIG. 1.

As shown, the array substrate 10 of the liquid crystal display device is divided into a display area 12 inside the dotted line on which an image is displayed and a non-display area 15 outside the dotted line.

First, a plurality of gate wirings 17 and data wirings 25 are formed in the display area 12. The gate wirings 17 and the data wirings 25 cross each other to define the pixel region P. As shown in FIG. Although not shown, a thin film transistor is positioned at the intersection of the gate wiring 17 and the data wiring 25, and the thin film transistor displays an image by switching a signal to the pixel electrode in the pixel region.

Next, gate and data link lines 30 and 33 connected to the gate line 17 and the data line 25 are formed in the non-display area 15, and the gate and data link lines 30 and 33 are formed. One end is connected to the gate pad 40 and the data pad 45, respectively, and the gate pad 40 and the data pad 45 are the gate driver IC 50 and the data mounted on the array substrate 10. It is connected to the drive IC 60, respectively. The gate driver IC 50 and the data driver IC 60 are connected to an external printed circuit board (PCB) (not shown), respectively, through FPCs 70 and 72. have. In the printed circuit board (PCB), a plurality of elements such as integrated circuits are formed on the substrate 10 to generate various control signals and data signals for driving the liquid crystal display. In this case, the printed circuit board (PCB) may be formed of a gate portion and a data portion, respectively, which are connected to each other by the FPCs 70 and 72 so that the gate signal and the data signal are organically connected to supply a signal.

In the above-described liquid crystal display, the gate and data pads 40 and 45 connected to the gate driver IC 50 and the data driver IC 60 cause defects during the defect inspection performed after the completion of the liquid crystal panel or during the manufacturing process. In order to easily check the wirings, the pads 40 and 45 are assigned with respective wiring numbers.

FIG. 2 illustrates a pad forming unit PA in a liquid crystal display device having a drive IC mounting structure using a tape carrier package (TCP) method, and FIG. 3 is an array in which the TCP mounting structure liquid crystal display device of FIG. The gate pad part PA is illustrated when the substrate is placed on the top surface, that is, when the substrate is turned over.

As shown in the drawing, the liquid crystal display device having the drive IC mounting structure using the TCP method has a sufficiently wide spacing WP between the pads 82 formed on the array substrate of the liquid crystal panel 80. And a wiring number 84 are formed in the region WP between the gate pad 82 and the gate pad 82. In this case, when the liquid crystal panel 80 is placed on the upper side of the color filter substrate, the wiring number 84 can be normally checked. On the contrary, even when the lower substrate is placed on the upper side of the array substrate, Although turned upside down, the wiring number (84 in FIG. 3) can be confirmed without a problem. This is because the wiring number 84 is formed in the region WP between the gate pad 82 and the pad 82 at the outer portion of the transparent substrate.

On the other hand, in the gate pad portion PA of the liquid crystal display device having the COG structure shown in FIG. 4, the gate pad spacing A is the gate pad of the above-described TCP structure on the array substrate of the liquid crystal panel 90 due to the characteristic of the COG structure. It is formed narrower than the interval (WP of Figs. 2 and 3). Therefore, the gate pad (A) interval is too narrow, there is a difficulty in forming the wiring number, the size is too small, there is an inconvenience to confirm.

Accordingly, to solve this problem, a metal layer forming an amorphous silicon layer (not shown) or a data line (not shown), which is a process after the gate line 92 is formed, is formed on the gate pad 92 connected to the gate line 97. By patterning to form a gate wiring number (95).

However, in the gate pad part PA of the liquid crystal display device having the COG structure described above, the gate pad metal constituting the gate pad 92 has an opaque non-transparent property, so that the liquid crystal panel 90 is used as the lower substrate. When viewed from the upper side, as shown in FIG. 5, the wiring number 95 written on the gate pad 92 is not visible. Therefore, when observing the liquid crystal panel 90 with the lower substrate as the upper side, the wiring number 95 is not visible, so it is difficult to perform the defect analysis work that needs to be performed by checking the wiring number 95.

Although the gate pad has been described as an example, the same problem occurs in the data pad as well.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to write a negative wiring number on an opaque pad metal layer forming a pad in a liquid crystal panel having a COG structure forming a driving IC on a substrate. By doing so, during the process or during the inspection of the defect, the wiring number can be easily observed when the panel is viewed with the upper substrate upward, or when the panel is turned over, that is, the lower substrate is upward.

1 is a plan view showing a schematic structure of an array substrate for a COG mounting structure liquid crystal display device;

2 is a plan view showing a pad portion in a tape carrier package (TCP) mounting structure liquid crystal display device;

FIG. 3 is a plan view illustrating the gate pad unit when the TCP mounting structure liquid crystal display of FIG. 2 is placed on an upper surface of an array substrate.

4 is a plan view showing a gate pad unit in a conventional COG-mounted liquid crystal display device;

FIG. 5 is a plan view illustrating the gate pad unit when the array substrate serving as the lower substrate is placed on the top surface of the COG mounting structure liquid crystal display of FIG. 4; FIG.

6 is a plan view illustrating a gate pad unit in a COG mounting structure liquid crystal display device according to an embodiment of the present invention;

Fig. 7 is a plan view showing the gate pad portion when the array substrate as the lower substrate is placed on the top surface of the COG mounting structure liquid crystal display device of 6;

8A to 8C are cross-sectional views illustrating a method of forming wiring numbers on gate pads and data pads of a COG mounted structure liquid crystal display device according to an embodiment of the present invention;

<Description of Major Symbols in Drawing>

100: liquid crystal panel 110: gate pad

114: gate wiring 116: data wiring

120: engraved wiring number PA: gate pad part

In order to achieve the above object, an array substrate for a COG mounting structure liquid crystal display device according to an embodiment of the present invention includes a substrate; A gate wiring formed on the substrate; A gate pad formed at one end of the gate wiring; A negative gate wiring number formed in a portion of the gate pad; A data line formed to cross the gate line; A data pad at one end of the data line; A negative data line number formed in a portion of the data pad; A thin film transistor formed in an area where the gate line and the data line cross each other; And a driving IC formed on the gate pad and the data pad.

In this case, the gate wiring number has a unique number that does not overlap with the numbers of other gate wirings except itself, and the data wiring number does not overlap with the numbers of other data wirings except itself. It is characterized by having a number of.

In addition, the intaglio gate wiring number is etched by the metal forming the opaque gate pad is formed transparent, so that both the upper and lower surfaces of the substrate can be confirmed the number, the intaglio data wiring number is the metal forming the opaque data pad It is characterized by being etched and formed transparently so that the number can be confirmed on both the upper and lower surfaces of the substrate.

According to an embodiment of the present invention, there is provided a method for forming a wiring number of an array substrate for a liquid crystal display device having a COG mounting structure; Forming a photoresist layer on the metal layer; Positioning a mask having a blocking region in the metal wiring forming portion and a wiring number forming region in the metal wiring forming portion over the photoresist layer; Exposing and developing the substrate on which the mask is located to form a photoresist pattern in which the photoresist of the wiring number forming portion of the metal wiring forming region is removed from the metal wiring forming region on the metal layer; The metal layer exposed to the outside of the photoresist pattern is etched to remove metal wiring and a portion of the metal layer therein to form a negative wiring number.

In this case, the wiring number forming region is a part of the pad region at one end of the metal wiring, the metal wiring is a gate wiring or a data wiring, the pad is characterized in that the gate pad or a data pad.

Hereinafter, a method of forming a pad number in a liquid crystal display device having a COG structure according to an embodiment of the present invention will be described.

FIG. 6 is a plan view illustrating a gate pad portion of a liquid crystal display device having a COG structure according to a sealing example of the present invention, and illustrates a portion of the gate pad portion in a liquid crystal panel state before the driving IC is formed on the substrate.

As shown in the drawing, the gate pads 110 are arranged on the array substrate of the liquid crystal panel 100 at regular intervals, and are connected to the gate pads 110 and link wires 112 are formed. The wiring 112 is connected to the gate wiring 114 of the display portion AA of the liquid crystal display device. Although not shown, a gate driver IC (not shown) overlaps with a portion of the pad link wiring 112 on the gate pad 110, and bumps (not shown) of the gate driver IC are formed on the gate pad 110. Connected with

In the state of the liquid crystal panel 100 before attaching a gate driving IC (not shown) on the gate pad 110, various colors such as red, green, and blue are input to the display unit AA where a screen is displayed. The defect inspection of the panel 100 is performed, and the apparatus used at this time is an auto probe. In order to inspect the liquid crystal panel 100 using the auto probe, a voltage is applied to the liquid crystal panel 100 and an image signal is applied to the display unit AA where each screen is displayed. To this end, an image signal must be applied to the gate line 114 and the data line 116 forming the display unit AA, and the gate pad 110 and the data pad (not shown) may be applied to an auto probe device. Needles are formed in contact with each of the data wires 116 and the gate wires 114. The needle contacts the gate pad 110 and the data pad (not shown), respectively, and inputs a signal to each of the gate line 114 and the data line 116 to drive the liquid crystal panel 100 so that the display unit AA is defective. Check it.

In order to contact the needle of the auto probe, the gate pad 110 and the data pad (not shown) of the liquid crystal panel 100 are in contact with a bump of a driving IC (not shown). In addition to the time) is formed long including the area for the needle contact of the auto probe (auto probe).

In addition, the gate pad 110 and the data pad (not shown) are assigned unique numbers that do not overlap each of the wirings 114 and 116, in order to obtain information easily and quickly in the failure analysis. For example, if the location of the defective pixel is identified, if there is no number of each of the wirings 114 and 116, it is cumbersome to count from the beginning, and a huge amount of time is required for the failure analysis. Accordingly, in order to solve the above problem, each wiring number is assigned to a portion of the pad 110 (not shown) connected to each of the wirings 114 and 116 formed in the non-display area.

In the COG structure of the liquid crystal panel 100, since the interval between the pads 110 (not shown) is narrow, numbers are formed on the pads 110 (not shown). In the manufacture of the array substrate of the liquid crystal panel 110, a metal material is deposited on the entire surface of the substrate when the gate wiring 114 is formed, a photoresist is applied on the deposited metal material layer, and a photoresist pattern is formed using a photolithography method. do. Next, the exposed metal layer is etched using the photoresist pattern as a mask, and the remaining photoresist pattern is removed to form the gate wiring 116 connected to the gate pad 110. In the exemplary embodiment of the present invention, when the gate wiring 114 is formed, each gate wiring number 120 is etched in a partial region of the gate pad 110 by etching the gate wiring metal layer corresponding to the wiring number 120 to remove the wiring. To form the number 120. The gate line 114 is formed of an opaque metal layer. Therefore, it is easy to check the wiring number by removing part of the wiring to allow light to pass through.

In addition, when the wiring number 120 is formed in an intaglio, the wiring number 120 may be sufficiently observed even when the liquid crystal panel 110 is turned upside down. As shown in FIG. 7, when the liquid crystal panel 120 is inverted, the wiring number 120 is also inverted so that the numbers are reversed as if the letters are engraved on the painting, but not sufficiently recognized.

Also in the data pad 116, the negative data wiring number (not shown) is formed when the data wiring 116 is formed in the same manner as the negative wiring number 120 is formed on the gate pad 110. When formed in some areas.

A method of forming a wiring number on a gate pad and a data pad will be described with reference to FIGS. 8A through 8C with reference to the drawings.

First, as shown, a metal material is deposited on the substrate 130 to form a metal layer 132. A photoresist is coated on the entire surface of the metal layer 132 and a mask 140 having a light transmitting area TA1 and a blocking area BA is positioned on the photoresist-coated substrate 100. Depending on the characteristics of the photoresist, but in the case of a positive type photoresist, the light-receiving part is removed during development, so that the blocking area BA is located in the part GLA where the gate wiring including the gate electrode is to be formed. In addition, the other area may correspond to the transmission area TA of the mask 140. At this time, in the gate pad forming portion GPA at one end of the gate wiring forming portion GLA, a unique number assigned to the gate wiring is transmitted on the mask 140 of the blocking region BA corresponding to a part of the gate pad region. The part formed to be the area TA is made to correspond.

Next, as shown in FIG. 8B, the photoresist pattern 145 is formed by performing an exposure and development process on the substrate 130 on which the photoresist layer 135 (FIG. 8A) on which the mask 140 is located is formed. In this case, a photoresist pattern 145 is formed on a portion where the gate wiring is to be formed on the substrate 130, and the photoresist is developed in numerical form on a portion of the region corresponding to the gate pad in the photoresist pattern 145. Removed.

Next, as shown in FIG. 8C, the metal layer (132 of FIG. 8B) exposed to the outside of the photoresist pattern (145 of FIG. 8B) is etched and removed to form a gate wiring 150, and the gate wiring 150 In the gate pad 152 at one end, a metal layer in the form of a number in which the photoresist pattern (145 in FIG. 8B) is not formed is etched to form a negative wiring number 160.

Next, although not shown in the drawings, a gate insulating film (not shown) is formed on the gate wiring 150 and the gate pad 152, and an inorganic insulating material constituting the gate insulating film is an end pad 152 of the gate wiring 150. It is filled in the etched metal layer of. In addition, a protective layer is formed on the gate insulating layer. At this time, since the gate insulating film and the protective layer pass light through a transparent material, it is not a problem to check the wiring number.

Also in the data pad, the wiring number is formed in a recessed shape on a part of the data pad when the data wiring is formed in the same manner as the intaglio wiring number is formed on the gate pad.

The present invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

In the present invention, in the liquid crystal display of the COG structure in which the driving IC is formed on the substrate, defect inspection or failure analysis is formed by forming gate wiring and data wiring numbers on the gate pad and the data pad at one end of the gate wiring and data wiring. The gate wiring and the data wiring number can be easily identified on either the top surface of the color filter substrate or the top surface of the array substrate of the liquid crystal panel.

In addition, the failure analysis can be facilitated, and by reducing the time to check the wiring number, the failure analysis time can be shortened.

Claims (9)

A substrate; A gate wiring formed on the substrate; A gate pad formed at one end of the gate wiring; A negative gate wiring number formed in a portion of the gate pad; A data line formed to cross the gate line; A data pad at one end of the data line; A negative data line number formed in a portion of the data pad; A thin film transistor formed in an area where the gate line and the data line cross each other; A driving IC formed on the gate pad and the data pad Array substrate for a COG mounting structure liquid crystal display device comprising a. The method of claim 1, And the gate wiring number has a unique number which does not overlap with a number of other gate wirings except itself. The method of claim 1, And the data line number has a unique number which does not overlap with a number of other data lines except itself. The method of claim 1, The intaglio gate wiring number is a transparent substrate formed by etching the metal forming the opaque gate pad is a COG mounting structure liquid crystal display device array substrate that can be identified on both the upper and lower surfaces of the substrate. The method of claim 1, The intaglio data wiring number is a transparent substrate formed by etching the metal constituting the opaque data pad is a COG mounting structure liquid crystal display device array substrate that can be identified on both the upper and lower surfaces of the substrate. Forming a metal layer on the substrate; Forming a photoresist layer on the metal layer; Positioning a mask having a blocking region in the metal wiring forming portion and a wiring number forming region in the metal wiring forming portion over the photoresist layer; Exposing and developing the substrate on which the mask is located to form a photoresist pattern in which the photoresist of the wiring number forming portion of the metal wiring forming region is removed from the metal wiring forming region on the metal layer; And etching the metal layer exposed to the outside of the photoresist pattern to form a negative wiring number by partially removing the metal wiring and the metal layer therein. The method of claim 6, And wherein the wiring number forming region is a portion of a pad region at one end of a metal wiring. The method of claim 7, wherein And the metal wiring is a gate wiring or a data wiring. The method of claim 7, wherein And the pad is a gate pad or a data pad.