KR20050002326A - Low power source driver for liquid crystal display - Google Patents

Abstract

PURPOSE: A low power source driver for a liquid crystal display device is provided to reduce fabrication cost and power consumption, to obtain accurate source driver output and to reduce charging charge loss. CONSTITUTION: According to the source driver for a liquid crystal display device driving a data line by generating an output voltage, a ground voltage is applied to a ground port and a power supply voltage higher than the ground voltage is applied to a power supply port. An input port inputs an input voltage, and an output port generates an output voltage. The first PMOS transistor(PT1) has a gate connected to its drain. The second PMOS transistor(PT2) has a gate connected to the drain of the first PMOS transistor and a source connected to the output port. The first NMOS transistor(NT1) has a gate connected to its drain. The second NMOS transistor(NT2) has a gate connected to the drain of the first NMOS transistor and a source connected to the output port. The third NMOS transistor(NT3) has a gate connected to the input port and a source connected to the source of the first PMOS transistor. The third PMOS transistor(PT3) has a drain connected to the power supply port and a gate connected to its source. The source driver also includes switches(S1-S6) and the first capacitor(C1).

Description

LOW POWER SOURCE DRIVER FOR LIQUID CRYSTAL DISPLAY}

The present invention relates to an apparatus for driving a liquid crystal display (LCD), and more particularly, to a low power source driver for an LCD driving apparatus.

LCD panels are used in personal computers, word processors and color televisions because they are thinner and consume less power than cathode ray tube (CRT) panels. Specifically, active matrix liquid crystal displays have high demands because of their high response speed, high-density screen, and multi-gradation display.

In general, an active matrix liquid crystal display device includes a semiconductor substrate, an opposing substrate, and a liquid crystal inserted between the semiconductor substrate and the opposing substrate. The semiconductor substrate includes thin metal wires, transparent pixel electrodes, and thin-film transistors, and the opposing substrate includes a transparent common electrode. A gradation voltage is applied to each of the pixel electrodes by controlling the thin film transistor to perform a switching action. The transmittance of the liquid crystal is changed by the voltage difference between each pixel electrode and the transparent common electrode, and as a result, an image is displayed.

The semiconductor substrate is provided with a data line for applying a gray voltage to the pixel electrodes and a scan line for applying switching control signals (or scan signals) to the thin film transistors. When the scan signal of the scan line is in a high level state, all the thin film transistors connected to the scan line are turned on, and a gray voltage sent to the data line is applied to the pixel electrodes through the thin film transistors. If the scan signal is low enough to turn off the thin film transistor, the voltage difference between the pixel electrode and the common electrode is maintained until the next gray voltage is applied to the pixel electrode. Thus, when scan signals are sequentially applied to the respective scan lines, the gradation voltage is applied to all the pixel electrodes, so that the display screen is updated every frame period.

The LCD driving apparatus for driving the data lines should be able to charge and discharge a large load of each data line having liquid crystal capacitance, wiring resistance and wiring capacitance.

The LCD driving device includes a voltage divider, a decoder, and a driver connected to a data line. Conventional drivers are implemented with operational amplifiers (see S. Saito et al., “A 6-bit Digital Data Printer for Color TFT-LCDs”, SID 95 Digest, pages 257-260, 1995). Because op amps have a large current supply capability, they can drive data lines with large capacitance values at high speed. In addition, even when the threshold voltage of the transistor in the operational amplifier varies little by little, the variation in the output voltage of the operational amplifier is relatively small. In addition, the output voltage is very accurate.

However, in the conventional driver, as the number of data lines increases, the number of operational amplifiers composed of a plurality of components increases. Thus, if the LCD driver with the conventional driver is implemented in the form of a single integrated circuit, the integrated circuit should be increased to have a sufficient size to accommodate the increased operational amplifier, resulting in integration The manufacturing cost of the circuit increases. In addition, op amps require a steady current, resulting in increased power consumption. The structure of the op amp is not suitable for low power consumption. A specific technique employing the operational amplifier in an LCD driving device is disclosed in US Pat. No. 6,075,524 (Patent Holder Ruta, titled “Integrated Analog Source Driver For Active Matrix Liquid Crystal Display”). U.S. Patent No. 6,127,997 (patent owner Tsuchi, entitled "Driver For Liquid Crystal Display Apparatus With No operational Amplifier") discloses an LCD drive without an operational amplifier. However, even in an LCD driving apparatus that does not employ an operational amplifier, there is still a problem of increasing channel precharge charge loss because of the large swing width during charge or discharge operation.

An object of the present invention for solving the above problems is to reduce the manufacturing cost, to reduce the power consumption, to obtain an accurate source driver output, the source for the LCD driving device that can reduce the charge charge loss To provide a driver.

1 is a block diagram showing a circuit of a conventional LCD driving apparatus.

2 is a circuit diagram of a source driver according to a first embodiment of the present invention.

3A to 3H are timing diagrams for describing an operation of the source driver of FIGS. 2 and 4.

4 is a circuit diagram modified from the source driver of FIG. 2.

FIG. 5 is a table for describing an operation of the source driver of FIG. 2.

6 is a circuit diagram of a source driver according to a second embodiment of the present invention.

7A to 7I are timing diagrams for describing a first operation of the source driver of FIG. 6.

8A to 8I are timing diagrams for describing a second operation of the source driver of FIG. 6.

9A to 9I are timing diagrams for describing a third operation of the source driver of FIG. 6.

FIG. 10 is a circuit diagram of a modified source driver of FIG. 6.

FIG. 11 is a table for describing an operation of the source driver of FIG. 6.

Explanation of symbols on the main parts of the drawings

101: voltage divider 102: decoder

103: driver

In order to achieve the above object, the present invention provides a source driver that receives an input voltage and generates an output voltage to drive a data line of a liquid crystal display. According to the source driver, first and second PMOS transistors are used as the first source follower to follow the input voltage and eliminate body effect in the n-well process and to maintain a constant loading load loss. do. The first and second PMOS transistors have a common gate coupled to the drain of the first PMOS transistor. The source of the second PMOS transistor is coupled to the output terminal. The first and second NMOS transistors have a common gate coupled to the drain of the first NMOS transistor, and the source of the second NMOS transistor is coupled to the output terminal. The gate of the third NMOS transistor is coupled to the input terminal and the source is coupled to the source of the first PMOS transistor. The gate of the third NMOS transistor is coupled to the input terminal and the source is coupled to the source of the first PMOS transistor. A source of a third PMOS transistor is coupled to the power supply terminal and a gate is coupled to the drain of the third PMOS transistor. A first switch is coupled between the drain of the third PMOS transistor and the drain of the first NMOS transistor. A second switch is coupled between the ground terminal and the drain of the first PMOS transistor. The third switch is coupled between the power supply voltage terminal and the drain of the third NMOS transistor. A fourth switch is coupled between the input terminal and the source of the first NMOS transistor. A fifth switch is coupled between the power supply terminal and the drain of the second NMOS transistor. A sixth switch is coupled between the ground terminal and the drain of the second PMOS transistor. The first capacitor receives a control signal and operates to raise the drain voltage of the first NMOS transistor to a voltage level of at least the input voltage plus the threshold voltage of the NMOS transistors. The first capacitor is coupled between ground and the drain of the first NMOS transistor.

According to an aspect of the present invention, the source driver further includes a fourth PMOS transistor and a seventh switch. The gate of the fourth PMOS transistor is coupled to the input terminal, and the source is coupled to the source of the first NMOS transistor. The seventh switch is coupled to the ground terminal and the drain of the fourth PMOS transistor.

According to one aspect of the invention, the source driver further comprises a ninth switch coupled between the input terminal and the source of the third NMOS transistor.

According to another aspect of the invention, the source driver further comprises a fourth NMOS transistor having a gate coupled to a low voltage, a source coupled to the drain of the second PMOS transistor, and a drain coupled to the output terminal.

According to another aspect of the invention, the source driver further comprises an eighth switch coupled between the input terminal and the output terminal. The eighth switch is turned on after the second PMOS transistor or the second NMOS transistor operates as a source follower.

The LCD driving apparatus according to the present invention does not use an operational amplifier and can reduce a problem of a large precharge charge loss of a channel.

Hereinafter, embodiments of the LCD driving apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

First, a general LCD driving apparatus will be described with reference to FIG. 1 before describing embodiments of the LCD driving apparatus according to the present invention. As shown in FIG. 1, the LCD driver generally includes a voltage divider 101, a decoder 102, and a driver 103 connected to a data line DL. The data line DL is connected to the pixel electrodes through the thin film transistors TFTs. The voltage divider 101 is made up of resistors R1, R2, ..., R64 that generate a multi-gradation voltage. In addition, the decoder 102 may include the first lines connected to the resistors R1, R2,..., And R64 and the second lines receiving the video data signals D0, D1,..., And D5. Complementary metal oxide semiconductor (CMOS) switches located at the intersection of

2 is a circuit diagram of a source driver according to a first embodiment of the present invention.

The first PMOS transistor and the second PMOS transistor of the source driver according to the first embodiment of the present invention can remove the body effect in the n-well process by following the input voltage, and the loading charge loss (loading charge loss) can be kept constant. The first and second PMOS transistors PT1 and PT2 have a common gate connected to a drain of the first PMOS transistor MP1, respectively, and a source of the second PMOS transistor is connected to an output terminal.

Each of the first and second NMOS transistors NT1 and NT2 has a common gate connected to the drain of the first NMOS transistor MN1, and a source of the second NMOS transistor is connected to an output terminal. A gate of the third NMOS transistor is connected to the input terminal, and a source is connected to the source of the first PMOS transistor PT1. A drain of the third PMOS transistor PT3 is connected to a power supply terminal and a gate is connected to a source of the third PMOS transistor PT3. The first switch S1 is connected between the source of the third PMOS transistor PT3 and the drain of the first NMOS transistor NT1. The second switch S2 is connected between the ground terminal and the drain of the first PMOS transistor PT1. The third switch S3 is connected between the power supply terminal and the drain of the third NMOS transistor NT3. The fourth switch S4 is connected between the input terminal and the source of the first NMOS transistor NT1. The fifth switch S5 is connected between the power supply terminal and the drain of the second NMOS transistor NT2. The sixth switch S6 is connected between the ground terminal and the drain of the second PMOS transistor NP2. The first capacitor C1 is connected between the control signal terminal and the drain of the first NMOS transistor NT1. The first capacitor C1 receives the control signal NP and raises the drain voltage of the first NMOS transistor NT1 to a voltage level of at least the input voltage plus the threshold voltage value of the NMOS transistor. Any kind of capacitor (for example, a capacitor in the form of a metal-insulation layer-metal or a capacitor in the form of a pore) may be used as the first capacitor C1.

The third NMOS transistor NT3 and the third and second switches S2 and S3 may include a gate voltage of the second PMOS transistor PT2, the input voltage, a threshold voltage of the first PMOS transistor PT1, and the third voltage. 3 to bias the voltage level shifted by the threshold voltage of the NMOS transistor NT3. The third PMOS transistor PT3, the fourth and first switches S4 and S1 may have a gate voltage of the second NMOS transistor NT2 as the input voltage and a threshold voltage of the first NMOS transistor NT1. Bias to the shifted voltage level. The sixth switch S6 operates the second PMOS transistor PT2 as a source follower. Therefore, a voltage level obtained by shifting the common gate voltages of the first and second PMOS transistors PT1 and PT2 by the threshold voltage of the second PMOS transistor PT2 is output to the output terminal as an output voltage. The fifth switch S5 allows the second NMOS transistor NT2 to operate as a source follower. Therefore, a voltage level obtained by shifting the common gate voltages of the first and second NMOS transistors NPT1 and NPT2 by the threshold voltage of the second NMOS transistor NPT2 is output to the output terminal as an output voltage.

The source driver according to the present invention further includes a fourth PMOS transistor PT4 and a seventh switch S7. The gate of the fourth PMOS transistor PT4 is connected to the input terminal, and the source is connected to the source of the first NMOS transistor NT1. The seventh switch S7 is connected between the ground terminal and the drain of the fourth PMOS transistor PT4. In addition, the source driver may further include a fourth NMOS transistor NT4. A gate of the fourth NMOS transistor NT4 is connected to a low voltage, a source is connected to a drain of the second PMOS transistor PT2, and a drain is connected to the output terminal.

3A to 3H are timing diagrams for describing an operation of the source driver of FIGS. 2 and 4. Hereinafter, the operation of the source driver of FIG. 2 will be described with reference to FIGS. 3A to 3H showing two data output periods.

First, as shown in FIG. 3B, both switches S1 and S2 are turned on at time t0. The bias voltage V1 of the transistors PT1 and PT2 is 0 volts. The bias voltage V2 at the gates of the transistors NT1 and NT2 is VDD-Vthp4 volts.

Next, as shown in FIGS. 3B and 3C, the switches S1 and S2 are turned off at a time t1, and the control signal NP is turned on to turn the drain voltage of the first NMOS transistor NT1 to the NMOS. The threshold voltage of the transistor is added to a voltage level higher than the voltage level obtained by adding a predetermined gamma voltage. At the same time, the switches S3 and S7 and the transistors PT4 (or PT4 and S7) are turned on, so that the bias voltages V1 and V2 become the following equations (1) and (2).

V1 = Vin-Vthn3 + Vthp1

V2 = Vin + Vthn1 + Vthp4

(Vthp1 is the threshold voltage of transistor PT1, Vthn3 is the threshold voltage of transistor NT3, Vthn1 is the threshold voltage of transistor NT1, and Vthp4 is the threshold voltage of transistor PT4.)

3D and 3E, the switches S4 and S6 are turned on at time t2, and as a result, the bias voltage V2 satisfies the following expression (3).

V2 = Vin + Vthn1

In this case, since the transistor PT2 operates as a source follower, the output voltage Vout satisfies the following expression (4).

Vout = Vin-Vthn3 + Vthp1-Vthp2

Where Vthp2 is the threshold voltage of transistor PT2.

Here, the PMOS transistor PT4 and the switch S7 are not essential elements in the present invention. If there is no PMOS transistor PT4 and switch S7, the operation at times t1 and t2 may be slightly different as follows.

Next, as shown in FIGS. 3C and 3F, the switch S3 is turned on at the time t1, and as a result, the bias voltage V1 has a value of V1 = Vin − Vthn3 + Vthp1 according to Equation 1 above.

Next, as shown in FIGS. 3D and 3E, the switches S4 and S6 are turned on at the time t2, and as a result, the bias voltage V2 has a value of V2 = Vin + Vthn1 + Vthp4 according to Equation 3 above.

In this case, since the transistor PT2 operates as a source follower, the output voltage Vout has a value of Vout = Vin-Vthn3 + Vthp1-Vthp2 according to Equation 4 above.

The bias voltage V2 has the same value at the time t2 when the PMOS transistor PT4 and the switch S7 are not present or present. However, when the source driver according to the present invention does not have the PMOS transistor PT4 and the switch S7, a large current flows through the input terminal. Therefore, if Vthp1 has a value similar to Vthp2, the output voltage Vout has a value according to the following equation (5).

Vout ≒ Vin-Vthn3

Here, when the transistors PT1 and PT2 are formed adjacent to each other and have almost the same size, the threshold voltage Vthp1 becomes approximately equal to the threshold voltage Vthp2.

Next, as shown in Fig. 3G, the switch S5 is turned on at time t3. In this state, since the transistor NT2 operates as a source follower, the output voltage Vout satisfies the following expression (6).

Vout = Vin + Vthn1-Vthn2

(Vthn2 is the threshold voltage of transistor NT2.)

Therefore, if Vthn1 has a value similar to Vthn2 (Vthn1 ≒ Vthn2), the output voltage satisfies Equation 7 below.

Vout ≒ Vin

Thus, in the first embodiment, the output voltage Vout can have the same value as the input voltage Vin, and transistor PT2 as source follower provides a high precision voltage buffer with transistor NT2.

In addition, since the source follower of the PMOS transistor cannot follow the ultra-low gamma voltage, when the video data selects the gamma voltage of the ultra-low voltage in a general N-well process It is desirable to use an NMOS transistor to pull down the output voltage to ground. When the input voltage is less than the threshold voltage of the transistor PT2, the NMOS transistor NT4 is used to pull down the output voltage to the ground voltage.

The operation at times t5 to t8 repeats the operation at times t0 to t3.

4 is a circuit diagram modified from the source driver of FIG. 2.

The source driver of FIG. 4 further includes an eighth switch S8 connected between the input terminal and the output terminal. As illustrated in FIG. 3H, the eighth switch S8 is turned on after the second PMOS transistor PT2 or the second NMOS transistor NT2 is terminated as a source follower. When the output voltage Vout is close to Vin, the driving capability of the source follower becomes very weak, and thus, an accurate optimum value (target value) can be obtained by using the eighth switch S8. Another reason for using the eighth switch S8 is to compensate for the difference between Vout and the optimum value due to the difference in the threshold voltage between the transistors NT1 and NT2.

For example, the operation of the source driver of FIG. 4 is as shown in FIGS. 3A-3H. The output voltage Vout during the t2 to t4 time may be represented by Vout = Vin + Vthn1-Vthn2 of Equation 6.

In this case, when there is a difference between Vthn1 and Vthn2, the output voltage Vout has a deviation of ΔV from the optimum value (that is, Vin). Next, at time t4, switches S5 and S6 are both turned off and switch S8 is turned on. As a result, the output voltage Vout will be averaged by the source outputs (outputs of the source drivers) with the same gray output voltage, and if the time is long enough, the output voltage Vout will be small since ΔV will be small. Will ultimately equal the input voltage Vin. Even if the switch S8 turn-on time is not long, each source driver output with the same gray output voltage will still be averaged, and the source driver output at the opposite polarity will have the same offset from the optimum value and thus from the optimum value. The ΔV value may be canceled by the opposite polarity. Therefore, in FIG. 4, the accuracy of the output voltage Vout is increased by turning on the switch S8.

The source driver further includes a fifth NMOS transistor NT5 and a fifth PMOS transistor PT5. A source of the fifth NMOS transistor NT5 is connected to the output terminal, a drain is connected to the power supply terminal, and a gate is connected to the input terminal. The fifth NMOS transistor NT5 and the fifth PMOS transistor PT5 are used to discharge or charge the output of the source driver to reach a target value. The output of the source driver may have a more accurate value by the fifth NMOS transistor NT5 and the fifth PMOS transistor PT5.

FIG. 5 is a table for describing an operation of the source driver of FIG. 2.

As shown in FIG. 5, the source driver can be easily implemented by logic circuits.

6 is a circuit diagram of a source driver according to a second embodiment of the present invention. The source driver circuit structure of FIG. 6 is substantially the same as the source driver circuit structure of FIG. The main differences are as follows. The source driver according to the second embodiment of the present invention requires the fourth PMOS transistor PT4 and the seventh switch S7. Furthermore, an eighth switch S8 is connected between the input terminal and the first PMOS transistor PT1.

Since the source follower of the PMOS transistor cannot follow the low level gamma voltage, a source follower composed of the NMOS transistor is required to follow the low level gamma voltage. For example, assume that V0 is the highest gamma voltage and V63 is the lowest gamma voltage. Gamma voltages V1, V2, ..., V62 decrease sequentially. The source driver according to the second embodiment of the present invention divides the gamma voltage into three parts. The gamma voltage of the first portion is V0 to V7, the gamma voltage of the second portion is V8 to V55, and the gamma voltage of the third portion is V56 to V63.

7A to 7F are timing diagrams for explaining, in part I, a first operation indicating two data output cycles of the source driver of FIG. The switch S4 is always turned off in the first part and the second part.

First, as shown in FIG. 7B, both switches S1 and S2 are turned on at time t0. The bias voltage V1 at the gates of the transistors PT1 and PT2 is 0 volts. The bias voltage V2 at the gates of the transistors NT1 and NT2 is VDD-Vthp3 volts.

Next, as shown in Figs. 7B, 7C, and 7E, at the time t1, the switches S1 and S2 are turned off, and the switches S3 and S7 are turned on. In addition, the control signal NP is turned on to raise the drain voltage of the first NMOS transistor NT1 to a voltage level obtained by adding the threshold voltage of the NMOS transistor and the threshold voltage of the PMOS transistor to the input voltage. At the same time, the bias voltage V2 becomes V2 = Vin + Vthn1 + Vthp4 as shown in Equation 2 below.

Next, as shown in FIG. 7F, at the time t2, the switches S3 and S7 are turned off and the switch S9 is turned on so that the bias voltage V1 satisfies Equation 8 below.

V2 = Vin + Vthp1

When the switch S5 is turned on, in this state, the transistor NT2 operates as a source follower, so the output voltage Vout satisfies the following expression (9).

Vout = Vin + Vthn1 + Vthp4-Vthn2

Therefore, if Vthn1 is similar to the Vthn2 value, the output voltage satisfies the following equation (10).

Vout ≒ Vin + Vthp4

The maximum possible voltage level of (Vin + Vthp4) is the power supply voltage level.

Next, as shown in FIGS. 7D and 7G, at time t3, switch S5 is turned off and switch S6 is turned on. In this state, since the transistor PT2 operates as a source follower, the output voltage Vout satisfies the following expression (11).

Vout = Vin + Vthp1-Vthp2

Where Vthp2 is the threshold voltage of transistor PT2.

Therefore, if Vthp1 has a value similar to Vthp2 (Vthp1? Vthp2), the output voltage becomes Vout? Vin according to Equation 7 above.

Here, if the transistors PT1 and PT2 are formed adjacent to each other and have substantially the same size as each other, the threshold voltage Vthp1 becomes approximately equal to the threshold voltage Vthp2.

In addition, since the source follower of the PMOS transistor cannot follow the ultra-low gamma voltage, when the video data selects the gamma voltage of the ultra-low voltage in a general N-well process It is desirable to use an NMOS transistor to pull down the output voltage to ground. When the input voltage is less than the threshold voltage of the transistor PT2, the NMOS transistor NT4 is used to pull down the output voltage to the ground voltage.

The operation at times t5 to t8 repeats the operation at times t0 to t3.

8A through 8F are timing diagrams for describing a second operation of the source driver of FIG. 6 in part II. The second operation of the source driver according to Part II, according to the first embodiment of the present invention, except that the relationship of (Vin + Vthp4) is maintained during the period in which S5 is turned on, as shown in FIGS. 7A and 8A. Similar to the source driver according to the example.

9A to 9I are timing diagrams for describing a third operation of the source driver of FIG. 6 in part III. Since the gamma voltage between V56 and V63 of part III has a low value, the source follower of the PMOS transistor cannot exactly follow the low gamma voltage, and the source follower of the NMOS transistor follows the low gamma voltage. Used. Switch S9 is always turned off in part III.

First, as shown in Fig. 9B, both switches S1 and S2 are turned on at time t0. The bias voltage V1 at the gates of the transistors PT1 and PT2 is 0 volts. The bias voltage V2 at the gates of the transistors NT1 and NT2 is VDD-Vthp3 volts.

Next, as shown in Figs. 9B and 9C, at the time t1, the switches S1 and S2 are turned off, and the switches S3 and S7 are turned on. In addition, the control signal NP is in an ON state, and the drain voltage of the first NMOS transistor NT1 is set to a voltage level obtained by adding the threshold voltage of the NMOS transistor NT1 and the threshold voltage of the PMOS transistor PT4 to the input voltage. Raise it.

Next, at time t2, as shown in FIGS. 9D and 9F, the switch S4 is turned on, the bias voltage V1 satisfies V1 = Vin + Vthp1-Vthn3 of Equation 1, and the bias voltage V2 is the above equation. V2 = Vin + Vthn1 of Equation 3 is satisfied.

At the same time, switch S6 is turned on. In this state, the transistor PT2 operates as a source follower, and the output voltage Vout satisfies Vout = Vin + Vthp1-Vthn3-Vthp2 of Equation 4 above. Where Vthp2 is the threshold voltage of transistor PT2. Therefore, if Vthp1 has a value similar to Vthp2, the output voltage Vout satisfies Vout? Vin-Vthn3 in Equation 5 above.

Here, when the transistors PT1 and PT2 are formed adjacent to each other and have almost the same size, the threshold voltage Vthp1 becomes approximately equal to the threshold voltage Vthp2.

Next, as shown in Fig. 9G, the switch S5 is turned on at time t3. In this state, since the transistor NT2 operates as a source follower, the output voltage Vout satisfies Vout = Vin + Vthn1-Vthn2 in Equation 6 above. Where Vthn2 is the threshold voltage of transistor NT2. Therefore, if Vthn1 has a value similar to Vthn2 (Vthn1? Vthn2), the output voltage satisfies Vout? Vin of Equation 7 above.

FIG. 10 is a circuit diagram of a modified source driver of FIG. 6. The source driver further includes an eighth switch S8 connected between the input terminal and the output terminal. As shown in FIGS. 7H, 8H, and 9H, the eighth switch S8 is turned on after the source follower operation of the second PMOS transistor PT2 or the second NMOS transistor NT2. When the output voltage Vout is close to Vin, the driving capability of the source follower becomes very weak, and thus, an accurate optimum value (target value) can be obtained by using the eighth switch S8. Another reason for using the eighth switch S8 is to compensate for the difference between Vout and the optimum value due to the difference in the threshold voltage between the transistors NT1 and NT2 as described in the description of FIG. 4.

The source driver further includes a fifth NMOS transistor NT5 and a fifth PMOS transistor PT5. A source of the fifth NMOS transistor NT5 is connected to the output terminal, a drain is connected to the power supply terminal, and a gate is connected to the input terminal. A source of the fifth PMOS transistor PT5 is connected to the output terminal, a drain is connected to the ground terminal, and a gate is connected to the input terminal. The fifth NMOS transistor NT5 and the fifth PMOS transistor PT5 are used to obtain a more accurate output voltage.

FIG. 11 is a table for describing an operation of the source driver of FIG. 6. Although the operation of the source driver is different in part I, part II, and part III, the operation of the source driver is not shown in the logic circuit (not shown) as shown in FIGS. 7 to 9. Can still be implemented. That is, the switches S5 and S6 or the switches S4 and S8 of the parts I, II, and III may be easily implemented by the multiplexer.

Thus, in the second embodiment of the present invention, the output voltage Vout may be equal to the input voltage Vin, and high current supply capability is provided by the transistor PT2 as the source follower coupled to the transistor NT2 as the source follower. Can be provided.

In the above-described embodiments of the present invention, the PMOS transistors may be other P-channel transistors having an insulated gate, and the NMOS transistors may be other N-channel transistors having an insulated gate.

As described above, according to the present invention, the source driver does not use an operational amplifier composed of many circuit constituent enzymes, and the novel driver configuration of the source driver circuit applied to the LCD device appropriately uses a semiconductor wafer IC process. As a result, the chip size of the source driver can be reduced, and as a result, the power consumption as well as the manufacturing cost can be reduced.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (20)

In the source driver for driving a data line by receiving an input voltage to generate an output voltage, A ground terminal to which a ground voltage is applied; A power supply terminal to which a power supply voltage higher than the ground voltage is applied; An input terminal for receiving an input voltage; An output terminal for generating an output voltage; A first PMOS transistor whose gate is coupled with the drain; A second PMOS transistor having a gate coupled to the drain of the first PMOS transistor and a source coupled to the output terminal; A first NMOS transistor having a gate coupled to the drain; A second NMOS transistor having a gate coupled to the drain of the first NMOS transistor and a source coupled to the output terminal; A third NMOS transistor having a gate coupled to the input terminal and a source coupled to the source of the first PMOS transistor; A third PMOS transistor having a drain coupled to the power supply terminal and a gate coupled to a source; A first switch coupled between the source of the third PMOS transistor and the drain of the first NMOS transistor; A second switch coupled between the ground terminal and the drain of the first PMOS transistor; A third switch coupled between the power supply terminal and a drain of the third NMOS transistor; A fourth switch coupled between the input terminal and the source of the first NMOS transistor; A fifth switch coupled between the power supply terminal and a drain of the second NMOS transistor; A sixth switch coupled between the ground terminal and the drain of the second PMOS transistor; And And a first capacitor coupled between the control signal terminal and the drain of the first NMOS transistor. 2. The method of claim 1, wherein the first capacitor is operable to raise the drain voltage of the first NMOS transistor to a voltage level of at least the input voltage plus the threshold voltage of the NMOS transistors for a predetermined time. Source drivers. The gate of the second PMOS transistor (Vin + Vthp1 + Vthn3), wherein the third and the second switch (Vin + Vthp1 + Vthn3) for a predetermined time, wherein Vin is the input voltage, Vthp1 is the threshold of the first PMOS transistor Voltage, and Vthn3 is a threshold voltage of the third NMOS transistor, the source driver operative to bias the voltage. The gate of the second NMOS transistor (Vin + Vthn1)-wherein the fourth and the first switch are the predetermined voltage for a predetermined time, where Vin is the input voltage and Vthn1 is the threshold voltage of the first NMOS transistor. A source driver operative to bias with a voltage. The source driver of claim 1, wherein the sixth switch operates the second PMOS transistor as a source follower. The source driver of claim 1, wherein the fifth switch operates the second NMOS transistor as a source follower. The method of claim 1, wherein the source driver A fourth NMOS transistor having a source coupled to the drain of the second PMOS transistor, a drain coupled to the output terminal, and substantially grounding the output voltage for a predetermined time when the input voltage is less than the threshold voltage of the transistor Source driver, characterized in that it further comprises. The method of claim 1, wherein the source driver A fourth PMMOS transistor having a gate coupled to the input terminal and a source coupled to the source of the first NMOS transistor; And And a seventh switch coupled between the ground terminal and the drain of the fourth PMOS transistor. The method of claim 8, wherein the source driver And a ninth switch coupled between the input terminal and the source of the third NMOS transistor. 10. The method of claim 9, wherein the fourth switch is turned off and the ninth switch is turned on, then the fifth switch is turned on and the sixth switch is turned off to source the second NMOS transistor. Source driver, characterized by operating in a follower. 11. The method of claim 10, wherein the fifth switch is turned on and the sixth switch is turned off and kept on for a predetermined time, then the fifth switch is turned off and the sixth switch is turned on to the second A source driver for operating a PMOS transistor as a source follower. 10. The method of claim 9, wherein the fourth switch is turned on and the ninth switch is turned off, then the fifth switch is turned off and the sixth switch is turned on to source the second PMOS transistor. Source driver, characterized by operating in a follower. 13. The method of claim 12, wherein the fifth switch is turned off and the sixth switch is turned on, then the fifth switch is turned on and the sixth switch is turned off to operate the second NMOS transistor as a source follower. Source driver, characterized in that. The method of claim 9, wherein the source driver is And an eighth switch coupled between the input terminal and the output terminal and turned on after operation as a source follower of the second PMOS transistor or the second NMOS transistor. The method of claim 9, wherein the source driver is A fourth NMOS transistor having a source coupled to the drain of the second PMOS transistor, a drain coupled to the output terminal, and substantially grounding the output voltage for a predetermined time when the input voltage is less than the threshold voltage of the transistor Source driver, characterized in that it further comprises. The method of claim 9, wherein the source driver is A fifth NMOS transistor having a source coupled to the output terminal, a drain coupled to the power supply terminal, and a gate coupled to the input terminal; And And a fifth PMOS transistor having a source coupled to the output terminal, a drain coupled to the ground terminal, and a gate coupled to the input terminal. The method of claim 1, wherein the gate of the second PMOS transistor is (Vin-Vthn3 + Vthp1)-where Vin is the input voltage, Vthp1 is the threshold voltage of the first PMOS transistor, Vthn3 is the third NMOS transistor After being biased to a threshold voltage-voltage, the sixth switch is turned on and the fifth switch is turned off to operate the second PMOS transistor as a source follower. The sixth switch of claim 1, wherein the gate of the second NMOS transistor is (Vin + Vthn1), where Vin is the input voltage, and Vthn1 is the threshold voltage of the first NMOS transistor. Is turned off and the fifth switch is turned on to operate the second NMOS transistor as a source follower. The method of claim 1, wherein the source driver And an eighth switch coupled between the input terminal and the output terminal and turned on after operation as a source follower of the second PMOS transistor or the second NMOS transistor. The method of claim 1, wherein the source driver A fifth NMOS transistor having a source coupled to the output terminal, a drain coupled to the power supply terminal, and a gate coupled to the input terminal; And And a fifth PMOS transistor having a source coupled to the output terminal, a drain coupled to the ground terminal, and a gate coupled to the input terminal.