KR20050112610A - The analog buffer and the liquid crystal display device using the same - Google Patents

Abstract

The present invention relates to an analog buffer capable of maintaining a constant drain-source voltage of an output transistor without a separate current power supply, and a liquid crystal display device using the same, wherein an input voltage is applied to a gate and a first supply voltage is applied to a drain. And a first capacitor for outputting a voltage obtained by subtracting a threshold voltage from the input voltage to a source, and a first capacitor connected between a gate and a source of the first switching device to charge the threshold voltage of the first switching device. A buffer unit; And a voltage variable part for changing a first supply voltage applied to a drain of the first switching device according to the magnitude of the input voltage.

Description

The analog buffer and the liquid crystal display device using the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to an analog buffer capable of maintaining a constant drain-source voltage of an output transistor without a separate current power source, and a liquid crystal display using the same.

In general, a liquid crystal display may be classified into a liquid crystal panel displaying a video signal and a driving circuit applying a driving signal to the liquid crystal panel from the outside.

Although not shown in the drawing, the liquid crystal panel is a display device in which liquid crystal is injected between two transparent substrates (glass substrates) bonded to each other with a predetermined space, and a plurality of liquid crystal panels arranged at regular intervals on one of the two transparent substrates. The gate lines, the plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, and the plurality of thin film transistors formed in each pixel area of the matrix form defined by the gate lines and the data lines are each The gate line and the data line intersect each other.

In addition, pixel electrodes and a common electrode for applying an electric field to each of the pixel areas are provided. The pixel electrodes are connected to one of the data lines via the source and drain terminals of the thin film transistor, and the gate terminal of the thin film transistor is connected to one of the gate lines.

Therefore, when the turn-on signal is sequentially applied to the gate line, an image is displayed because the data signal is applied to the pixel electrode of the corresponding line.

As a thin film transistor element used in such a liquid crystal display device, hydrogenated amorphous silicon (amorphous silicon (H), hereinafter referred to as 'amorphous silicon (a-Si)') is mainly used. This is because a glass substrate (hereinafter, referred to as a "substrate") can be used.

However, because hydrogenated amorphous silicon has a disordered atomic arrangement, weak Si-Si bonds and dangling bonds exist, and thus, the Si-Si is changed into a quasi-stable state when irradiated with light or applied with an electric field to be used as a thin film transistor device. Stability is a problem.

In particular, amorphous silicon has a problem of deterioration in characteristics due to light irradiation, and is difficult to use in driving circuits due to electrical characteristics (low field effect mobility: 0.1 to 1.0 cm 2 / V · s) and reliability deterioration of display pixel driving elements.

That is, the amorphous silicon thin film transistor substrate connects the substrate and the printed circuit board (PCB) using a tape carrier package (TCP) driving IC (Integrated Circuit), so that the driving IC and the actual equipment occupy a large part of the cost.

In addition, when the resolution of the liquid crystal panel of the liquid crystal display device is increased, the pad pitch outside the substrate connecting the gate line and the data line of the thin film transistor substrate with the TCP becomes short, which makes TCP bonding itself difficult.

However, since polycrystalline silicon has a greater field effect mobility than amorphous silicon, a driving circuit can be made on a substrate. If the polycrystalline silicon is used as a substrate, a driving circuit can be made directly on the substrate, thereby reducing driving IC costs and mounting. Also becomes simpler.

That is, the polycrystalline silicon thin film transistor has higher electron or hole mobility than the amorphous silicon thin film transistor and can be implemented as a complementary (CMOS) thin film transistor.

Therefore, instead of connecting the driving circuit IC by bonding, a large portion of the driving circuit can be formed by TFT to be manufactured simultaneously with the thin film transistor formed on the pixel portion. Recently, due to the development of crystallization technology using a laser, it can be manufactured on a large glass substrate because it can be manufactured at a temperature similar to that of an amorphous silicon thin film transistor.

Accordingly, in a liquid crystal display device using a polycrystalline silicon glass substrate, driving circuits such as a data driver and a gate driver mounted externally can be formed on the same glass substrate.

As the performance of the liquid crystal display device using the polycrystalline silicon glass substrate is improved to increase the operation speed of the circuit, it is essential to implement an analog buffer capable of driving data lines on the liquid crystal panel.

In general, an amorphous silicon circuit uses an op amp as an analog buffer, but an op amp using a polycrystalline silicon thin film transistor with a large characteristic change is difficult to match, causing a large offset voltage and high power consumption due to a static current. Therefore, it is difficult to use an operational amplifier using the polycrystalline silicon thin film transistor as an analog buffer.

Accordingly, there is a need for an analog buffer which is insensitive to changes in the characteristics of polycrystalline silicon thin film transistors and has a simple structure, thereby reducing the area occupied and reducing power consumption.

However, when the polysilicon thin film transistor is used as an analog buffer instead of using the operational amplifier, the output voltage according to the input voltage generates a DC voltage error equal to the threshold voltage.

 The proposed analog buffer to remove this DC voltage error is shown in FIG.

1 is a schematic circuit diagram of a conventional analog buffer.

In the conventional analog buffer, as shown in FIG. 1, the first switch SW1 conducts the input voltage Vin to the first node P1 and the second switch conducts the second input voltage Vin. A gate is connected to the second switch SW2 applied to the node P2, the capacitor C connected between the first node P1 and the second node P2, and the first node P1. And is turned on by the input voltage Vin applied to the first node P1 to correspond to a value obtained by subtracting the threshold voltage Vth from the input voltage Vin of the first supply voltage VDD. An output transistor NT for applying a voltage to the third node P3 and a third switch connected between a source (third node P3) and the second node P2 of the output transistor NT. And a current power supply NC connected between the source (third node P3) of the output transistor NT and the second supply voltage VSS.

Referring to the operation of the conventional analog buffer configured as described in detail as follows.

First, the first and third switches SW1 and SW3 are turned on in the first period, and the second switch SW2 is turned off.

Therefore, the input voltage Vin is applied to the first node P1 via the turned-on first switch SW1 and the output of the input voltage Vin of the first node P1 is applied to the gate. Transistor NT is turned on.

Here, as the output transistor NT is turned on, the output transistor NT applies the first supply voltage VDD to the third node P3 (source of the output transistor NT). The first supply voltage VDD is not fully charged to the third node P3.

That is, since the source of the output transistor NT is connected to the load (data line) of the liquid crystal panel through an output line, the first supply voltage VDD is not fully charged to the source of the output transistor NT, Some are charged.

Specifically, the output transistor NT is turned off at the moment when the gate-source voltage Vgs of the output transistor NT becomes lower than the threshold voltage Vth of the output transistor NT. The first supply voltage VDD applied to the source of NT is determined as a voltage obtained by subtracting the threshold voltage Vth from the gate voltage Vg of the output transistor NT.

Here, the gate voltage Vg of the output transistor NT is equal to the input voltage Vin applied to the gate of the output transistor NT, so that the voltage applied to the source of the output transistor NT is It is equal to the voltage Vin-Vth obtained by subtracting the threshold voltage Vth of the output transistor NT from the input voltage Vin.

Accordingly, the capacitor C connected between the first node P1 and the third node P3 (the source of the output transistor NT) is connected to the first node P1 from the input voltage Vin applied to the first node P1. The voltage Vth obtained by subtracting the voltage Vin-Vth applied to the third node P3 is charged.

That is, the capacitor C is charged with the threshold voltage Vth of the output transistor NT.

Subsequently, the first and third switches SW1 and SW3 are turned off in the second period, and the second switch SW2 is turned on.

Then, the input voltage Vin is applied to the second node P2 via the turned-on second switch SW2 to convert the voltage of the second node P2 into the input voltage Vin. Raise.

In this case, as the voltage of the second node P2 is increased to the input voltage Vin, the first node is connected by the capacitor C connected between the second node P2 and the second node P2. The voltage of the node P1 also rises.

That is, the voltage of the first node P1 is increased to the voltage Vin + Vth, which is the sum of the input voltage Vin and the threshold voltage Vth charged in the capacitor C.

This may be explained as a characteristic in which the capacitor C maintains the voltage difference between both ends by the capacity charged in the capacitor C.

Here, the voltage Vin + Vth input to the first node P1 is applied to the gate of the output transistor NT to turn on the output transistor NT.

In this case, as described above, the turned-on output transistor NT does not completely charge the first supply voltage VDD to the source (third node P3) of the output transistor NT.

That is, the output transistor NT subtracts the voltage Vth obtained by subtracting the threshold voltage Vth of the output transistor NT from the voltage Vin + Vth input to the gate of the output transistor NT. It is applied to the source (third node P3) of (NT).

As a result, a voltage Vin + Vth obtained by adding the threshold voltage Vth stored in the capacitor C and the input voltage Vin is input to the gate of the output transistor NT, so that the source of the output transistor NT The output voltage Vout applied to becomes equal to the original input voltage Vin from which the threshold voltage Vth is subtracted.

The output voltage Vout applied to the source of the output transistor NT is applied to the data line of the liquid crystal panel through the output line 40.

As described above, the conventional analog buffer adds the threshold voltage Vth to be subtracted from the input voltage Vin in advance, thereby outputting the original input voltage Vin from which the threshold voltage Vth is removed in the final output stage. Done.

On the other hand, between the source of the output transistor (NT) and the second supply voltage (VSS) is provided with a current power supply (NC) for supplying a constant source current, the current power supply (NC) of the output transistor (NT) The drain-source voltage Vds is kept constant so as not to change.

If this is explained in more detail as follows.

If it is assumed that there is no current power source NC, since the first supply voltage VDD is applied to the drain of the output transistor NT, the drain voltage Vd of the drain is the first supply voltage VDD. Although always kept constant, the source voltage Vs applied to the source of the output transistor NT is always changed according to the magnitude of the input voltage Vin applied to the gate.

As a result, the drain voltage of the output transistor NT is fixed, and since the source voltage Vs always changes according to the magnitude of the input voltage Vin (gate voltage), the drain- of the output transistor NT is reduced. The source-to-source voltage Vds also changes according to the magnitude of the input voltage Vin.

Variation of the drain-source voltage Vds of the output transistor NT affects the input voltage Vin applied to the source of the output transistor NT, that is, the third node P3, so that the input voltage It will distort Vin.

Accordingly, the source voltage is supplied by supplying a constant source current to the source of the output transistor NT by connecting the same current power supply NC between the source of the output transistor NT and the second supply voltage VSS. (Vs) can be kept constant.

That is, the current power source NC supplies a current having a constant magnitude from the first supply voltage VDD to the second supply voltage VSS (from the drain to the source) to maintain the source voltage constant.

As a result, the drain-source voltage Vds of the output transistor NT is stabilized, and the output voltage Vout applied to the source of the output transistor NT is also stabilized.

However, the conventional analog buffer has the following problems.

First, since the current power source must always be driven to prevent distortion of the input voltage, power consumption according to the driving of the current power source increases.

Second, distortion of the input voltage may occur according to the device characteristics of the current power supply.

The present invention has been made to solve the above problems, by cascading the switching device to the drain of the output transistor, the drain voltage of the output transistor to change according to the size of the input voltage, output without a separate current power supply It is an object of the present invention to provide an analog buffer and a liquid crystal display device using the same which can maintain a constant drain-source voltage of a transistor at all times.

The analog buffer according to the present invention for achieving the above object, the input voltage is applied to the gate, the first supply voltage is applied to the drain, and outputs a voltage obtained by subtracting the threshold voltage from the input voltage to the source A buffer unit including a first switching device and a first capacitor connected between a gate and a source of the first switching device to charge a threshold voltage of the first switching device; And a voltage variable part for changing a first supply voltage applied to a drain of the first switching device according to the magnitude of the input voltage.

The buffer unit may further include a second switching device to which a first clock signal is applied to a gate, a drain is connected to a source of the first switching device, and a drain is connected to a first capacitor.

The voltage variable part includes a third switching device connected between the first supply voltage and the drain of the first switching device, the input voltage is applied to a gate of the third switching device, and the first supply is supplied to a drain. A voltage is input, and the source is connected to the drain of the first switching element.

A fourth switching device to which a second clock signal is applied to a gate, a first reference voltage is applied to a drain, and a source is connected to the gate of the third switching device; A fifth switching device to which a second clock signal is applied to a gate, a second reference voltage is applied to a drain, and a source is connected to a common connection terminal of the first switching device and the first capacitor; And a second capacitor connected between the gate of the first switching device and the gate of the third switching device.

The second reference voltage is smaller than the input voltage.

A sixth switching element to which the first clock signal is applied to a gate, the input voltage is applied to a drain, and a source is connected to a source of the fifth switching element; A third clock signal is applied to a gate, the input signal is applied to a drain, and a seventh switching device having a source connected to a common connection terminal of the first capacitor and the second switching device. .

And an output line connected to a common connection terminal between the source of the first switching element and the drain of the second switching element, and further comprising a discharge unit configured to discharge the remaining voltage of the output line.

The discharge unit may include an eighth switching device to which a fourth clock signal is applied to a gate, a reset signal is applied to a drain, and a source is connected to the output line.

And a current power source connected between the source of the first switching element and the second supply power source for supplying the second supply voltage.

In addition, the liquid crystal display device using the analog buffer according to the present invention configured as described above comprises: a liquid crystal panel having a plurality of gate lines and data lines perpendicular to each other; A data driver to output a data signal for driving a data line of the liquid crystal panel; The data signal is applied to a gate, a first supply voltage is applied to a drain, and a first switching device for outputting a voltage obtained by subtracting a threshold voltage from the data signal to a source, and between the gate and the source of the first switching device. A buffer unit connected to the first capacitor to charge the threshold voltage of the first switching device; And a voltage variable part for changing a first supply voltage applied to a drain of the first switching device according to the magnitude of the data signal.

Hereinafter, an analog buffer according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a circuit diagram of an analog buffer according to a first embodiment of the present invention, and FIG. 3 is a timing diagram for a clock signal and a waveform diagram for an output voltage.

4 is a circuit diagram of an analog buffer according to a second embodiment of the present invention, and FIG. 5 is a block diagram of a liquid crystal display using an analog buffer according to an embodiment of the present invention.

In the analog buffer according to the embodiment of the present invention, as shown in FIG. 2, the voltage varying part is turned on by the first clock signal S1 to set the first reference voltage Vref1 to the first node P1. The first NMOS transistor NT1 applied to the first NMOS transistor NT1 and the second NMOS transistor NT2 turned on by the first clock signal S1 to apply a second reference voltage Vref2 to the second node P2. And a first reference voltage Vref1 of the first node P1 and a second reference voltage Vref2 of the second node P2 connected between the first node P1 and the second node P2. Is turned on by the first capacitor C1 charging the difference Vref1-Vref2, and the first reference voltage Vref1 applied to the first node P1, and is turned off from the first reference voltage Vref1. A third NMOS transistor NT3 that applies a first supply voltage VDD corresponding to a magnitude obtained by subtracting the threshold voltage Vth to the third node P3, and a second applied to the second node P2. To the reference voltage (Vref2) And a first supply voltage VDD of the third node P3 corresponding to a magnitude obtained by subtracting the threshold voltage Vth from the second reference voltage Vref2 to the fourth node P4. A second reference of the second node P2 is applied by turning on the fourth NMOS transistor NT4 and the second clock signal S2 to apply an input voltage Vin to the second node P2. The voltage Vref2 is raised to the input voltage Vin, and the first node P1 is summed up with the input voltage Vin and the voltages Vref1-Vref2 charged in the first capacitor C1. The fifth NMOS transistor NT5 rising to the voltage Vin + (Vref1-Vref2) and the voltage Vin-Vth applied to the fourth node P4 by being turned on by the second clock signal S2. ) Is connected between the sixth NMOS transistor NT6 and the fifth node P5 and the second node P2 to apply the threshold voltage of the fourth NMOS transistor NT4. To charge (Vth) The second capacitor C2 and the third clock signal S3 are turned on to apply the input voltage Vin to the fifth node P5 so that the voltage Vin- of the fifth node P6 is applied. While raising Vth to the input voltage Vin, at the same time, the threshold voltage Vth (fourth NMOS transistor) charged in the second node P2 fmf the input voltage Vin and the second capacitor C2. A seventh NMOS transistor NT7 for raising the threshold voltage Vth of NT4 to the sum voltage Vin + Vth is included.

Here, the fourth node P4 is provided with an output line 140 through which the voltage applied to the fourth node P4 is transmitted.

In addition, the analog buffer configured as described above includes an eighth NMOS transistor NT8 that is turned on by the fourth clock signal S4 and applies a reset signal Reset to the output line 140.

The eighth NMOS transistor NT8 discharges the residual voltage existing in the output line 140 by applying the reset signal Reset to the output line 140 before the circuit configured as described above operates. Do it.

Meanwhile, the third node P3 is a source of the third NMOS transistor NT3 and a drain of the fourth NMOS transistor NT4.

The fourth node P4 is a source of the fourth NMOS transistor NT4, and when the sixth NMOS transistor is turned on, the fourth node P4 has the same potential as that of the fifth node P5. Has

In addition, the fourth NMOS transistor NT4 is a conventional output transistor. The third NMOS transistor NT3 is cascaded to the fourth NMOS transistor NT4, and the drain voltage of the fourth NMOS transistor NT4 is provided. To change (Vd).

In the analog buffer circuit of the present invention configured as described above, as shown in FIG. 2, an input voltage is applied to a gate, a first supply voltage VDD is applied to a drain, and a threshold from the input voltage Vin as a source. The threshold voltage Vth of the fourth NMOS transistor NT4 is connected between the fourth NMOS transistor NT4 and the gate and the source of the fourth NMOS transistor NT4 that output a voltage obtained by subtracting the voltage Vth. The buffer unit 500 including the second capacitor C2 to charge and the first supply voltage VDD applied to the drain of the fourth NMOS transistor NT4 are changed according to the magnitude of the input voltage Vin. A voltage variable unit 400 including the first, second, third, fifth, and seventh NMOS transistors NT1, NT2, NT3, NT5, NT7 and a first capacitor C1, and the output line To a discharge unit 600 configured of an eighth NMOS transistor NT8 for discharging the remaining voltage of 140. It is composed.

Referring to the operation of the analog buffer according to an embodiment of the present invention configured as described above in detail.

First, as shown in FIG. 3, only the fourth clock signal S4 has high logic in the first period T1.

Accordingly, an eighth NMOS transistor NT8 to which the fourth clock signal S4 is applied to the gate is turned on, so that a reset signal Reset is reset through the eighth NMOS transistor NT8 turned on. Is applied to line 140.

The remaining voltage of the output line 140 is discharged by the reset signal Reset, so that the output line 140 has a potential lower than the input voltage Vin to be applied to the input line.

Subsequently, as shown in FIG. 3, only the first clock signal S1 has high logic in the second period T2.

Accordingly, the first and second NMOS transistors NT1 and NT2 to which the first clock signal S1 is applied to the gate are turned on and the first reference voltage Vref1 is turned on. It is applied to the first node P1 via NT1, and the second reference voltage Vref2 is applied to the second node P2 via the turned-on second NMOS transistor NT2.

In this case, since the first node P1 is connected to the gate of the third NMOS transistor NT3, the resistance value of the first node P1 is near infinity so that the first node P1 is in a floating state. The first reference voltage Vref1 through the turned-on first NMOS transistor NT1 is thereby supplied to the first node P1 with little loss.

Therefore, it can be seen that the first reference voltage Vref1 is completely applied to the first node P1 while the first NMOS transistor NT1 is turned on.

Similarly, since the second node P2 is connected to the gate of the fourth NMOS transistor NT4, the second reference voltage Vref2 is generated when the second NMOS transistor NT2 is turned on. Fully applied to the second node P2.

In this case, the difference between the first reference voltage Vref1 and the second reference voltage Vref2 Vref1-Vref2 is connected to the first capacitor C1 connected between the first node P1 and the second node P2. ) Is charged.

Meanwhile, as described above, a first reference voltage Vref1 is applied to the first node P1, and a second reference voltage Vref2 is applied to the second node P2, so that the first node P1 is applied. The third NMOS transistor NT3 connected to the gate is turned on, and the fourth NMOS transistor NT4 connected to the second node P2 is turned on.

Accordingly, the first supply voltage VDD is applied to the third node P3 via the turned-on third NMOS transistor NT3, and the first supply voltage V3 is applied to the third node P3. VDD is again applied to the fourth node P4 via the turned-on fourth NMOS transistor NT4.

Here, the voltages applied to the third node P3 and the fourth node P4 will be described in more detail as follows.

That is, the third node P3 connected between the source of the third NMOS transistor NT3 and the drain of the fourth NMOS transistor NT4 and the fourth node P4 which is the source of the fourth NMOS transistor NT4. ) Is not floating because it is connected to the load (data line of the liquid crystal panel) through the output line 140.

Therefore, neither the first supply voltage VDD is applied to the third node P3 and the fourth node P4.

In other words, as described above, in order for the third NMOS transistor NT3 to be turned on, the gate-source voltage Vgs of the third NMOS transistor NT3 is changed to that of the third NMOS transistor NT3. When the gate-source voltage Vgs of the third NMOS transistor NT3 becomes lower than the threshold voltage Vth of the third NMOS transistor NT3, the third NMOS must be higher than the threshold voltage Vth. Transistor NT3 is turned off.

Therefore, the first supply voltage VDD is applied to the third node P3 only until the third NMOS transistor NT3 is turned off in the turn-on state.

Specifically, as the third NMOS transistor NT3 is turned on, the first supply voltage VDD is gradually charged to the third node P3.

Here, since the third node P3 is eventually the source of the third NMOS transistor NT3, it can be seen that the source voltage Vs of the third NMOS transistor gradually increases.

Here, the gate voltage Vg of the third NMOS transistor NT3 is fixed, and as the voltage Vs of the third node P3 (source of the third NMOS transistor NT3) continues to increase, The gate-source voltage Vgs of the third NMOS transistor NT3 continuously decreases.

The third NMOS transistor NT3 is instantaneously decreased so that the gate-source voltage Vgs is continuously equal to the threshold voltage Vth of the third NMOS transistor NT3. ) Is turned off.

As a result, the third node P3 subtracts the threshold voltage Vth of the third NMOS transistor NT3 from the gate voltage Vg of the third NMOS transistor NT3 among the first supply voltage VDD. One voltage Vg-Vth is applied.

As an example, assume that the first supply voltage VDD is 10V, the gate voltage Vg of the third NMOS transistor NT3 is 5V, and the threshold voltage Vth of the third NMOS transistor NT3 is 1V. .

When 5V is applied to the gate of the third NMOS transistor NT3, the gate-source voltage Vgs of the third NMOS transistor NT3 may be viewed as 5V, and the gate-source voltage Vgs Since the threshold voltage Vth is greater than 1V, the third NMOS transistor NT3 is turned on.

As the third NMOS transistor NT3 is turned on, the first supply voltage VDD; 10V is applied from a drain of the turned-on third NMOS transistor NT3 to a source (third node P3). As applied, the source voltage Vs gradually increases.

That is, as the source voltage Vs increases linearly from 1 V-> 2 V-> 3 V, the gate-source voltage Vgs decreases linearly from 4 V-> 3 V-> 2 V. Done.

Then, as soon as the source voltage Vs becomes 4V, the gate-source voltage Vgs becomes 1V, and the gate-source voltage Vgs becomes equal to the threshold voltage Vth.

Accordingly, the third NMOS transistor NT3 is turned off to maintain the source voltage Vs at 4V.

As a result, it can be seen that only 4V of the first supply voltage VDD 10V of 10V is applied to the third node P3.

In general terms, the voltage Vg− is obtained by subtracting the threshold voltage Vth of the third NMOS transistor NT3 from the gate voltage Vg applied to the third NMOS transistor NT3 at the third node P3. Vth) may be applied.

Here, the gate voltage Vg of the third NMOS transistor NT3 is a voltage applied to the gate of the third NMOS transistor NT3, and thus, the gate voltage Vg of the third NMOS transistor NT3 is It is equal to the first reference voltage Vref1 applied to the gate of the third NMOS transistor NT3.

Accordingly, the magnitude of the first supply voltage VDD applied to the third node P3 is a voltage obtained by subtracting the threshold voltage Vth of the third NMOS transistor NT3 from the first reference voltage Vref1. Vref1-Vth).

Similarly, the magnitude of the first supply voltage VDD applied to the fourth node P4 is equal to that of the fourth NMOS transistor NT4 from the second reference voltage Vref2 applied to the second node P2. The voltage Vref2-Vth is obtained by subtracting the threshold voltage Vth.

Next, as shown in FIG. 3, only the second clock signal S2 has a high logic in the third period T3.

Accordingly, the fifth and sixth NMOS transistors NT5 and NT6 to which the second clock signal S2 is applied to the gate are turned on.

Then, the input voltage Vin is applied to the second node P2 via the turned-on fifth NMOS transistor NT5 to convert the voltage Vref1 of the second node P2 to the input voltage Vin. To increase).

The elevated voltage Vin of the second node P2 is used as the gate voltage Vg of the fourth NMOS transistor NT4.

Accordingly, the magnitude of the first supply voltage VDD applied to the fourth node P4, which is the source of the fourth NMOS transistor NT4, is determined from the input voltage Vin applied to the second node P2. The voltage Vin-Vth is increased by subtracting the threshold voltage Vth of the fourth NMOS transistor NT4.

In addition, the voltage Vin-Vth applied to the fourth node P4 is transferred to the fifth node P5 via the sixth NMOS transistor NT6 turned on by the second clock signal S2. Is approved.

At this time, a voltage Vin of the second node P2 and a voltage of the fifth node P5 are connected to the second capacitor C2 connected between the second node P2 and the fifth node P5. The difference Vth4 of (Vin-Vth) is charged.

That is, the second capacitor C2 is charged with the threshold voltage Vth of the fourth NMOS transistor NT4.

On the other hand, since the second node P2 has risen to the input voltage Vin, the first capacitor C1 is connected between the second node P2 and the first node P1. The voltage at the node P1 also rises.

That is, the voltage Vref1 of the first node P1 is the voltage Vin + (summing up of the voltage Vin of the second node P2 and the voltages Vref1 -Vref2 charged in the first capacitor C1. Vref1-Vref2), and the elevated voltage Vin + (Vref1-Vref2) is used as the gate voltage Vg of the third NMOS transistor NT3.

Accordingly, the third node P3, which is the source of the third NMOS transistor NT3, is also thresholded by the third NMOS transistor NT3 from the voltage Vin + (Vref1 -Vref2) of the first node P1. It rises to the voltage Vin + (Vref1-Vref2) -Vth which subtracted the voltage Vth.

As described above, the potentials of the fourth node P4 are raised by the first and second capacitors C1 and C2, and the potentials of the third node P3 are raised to the fourth node P4. By rising higher than the potential of, the first supply voltage VDD applied to the drain of the third NMOS transistor NT3 can be smoothly supplied from the third node P3 to the fourth node P4.

Subsequently, as shown in FIG. 3, only the third clock signal S3 has high logic in the fourth period T4.

Therefore, the seventh NMOS transistor NT7 to which the third clock signal S3 is applied to the gate is turned on.

Then, the input voltage Vin is applied to the fifth node P5 via the turned-on seventh NMOS transistor NT7 to input the voltage Vin-Vth of the fifth node P5. Raise to voltage Vin.

Therefore, the voltage Vin of the second node P2 is also increased by the second capacitor C2 connected between the fifth node P5 and the second node P2.

That is, the voltage Vin of the second node P2 is the voltage Vin + Vth, which is the sum of the voltage Vin of the fifth node P5 and the voltage Vth charged in the second capacitor C2. Is raised.

The elevated voltage Vin + Vth is used as the gate voltage Vg of the fourth NMOS transistor.

Therefore, the voltage Vin-Vth of the fourth node P4 is obtained by subtracting the threshold voltage Vth of the fourth NMOS transistor NT4 from the voltage Vin + Vin of the second node P2. Rise to (Vin).

As a result, as shown in FIG. 3, in the fourth period T4, the fourth node P4 has the same voltage Vin as the input voltage Vin and is applied to the fourth node P4. The voltage Vin is supplied to the output line 140 as the output voltage Vout.

Herein, operations of the third NMOS transistor NT3 and the fourth NMOS transistor NT4 will be described in more detail as follows.

The fourth NMOS transistor NT4 serves as an output transistor for supplying an input voltage Vin to an output line, and the third NMOS transistor NT3 is cascaded to the fourth NMOS transistor NT4 to form the fourth transistor. By varying the drain voltage Vd of the 4 NMOS transistor NT4, the drain-source voltage Vds of the fourth NMOS transistor NT4 is kept constant regardless of the magnitude of the input voltage Vin. Do it.

That is, as described above, the drain voltage Vd of the conventional output transistor is fixed at a constant value, and the source voltage Vs changes according to the magnitude of the input voltage Vin (gate voltage Vg), As a result, although the drain-source voltage Vds of the output transistor has a problem of changing according to the magnitude of the input voltage Vin, the present invention has a drain voltage Vd of the output transistor, that is, the fourth NMOS transistor NT4. ) Is changed at the same rate as the source voltage according to the magnitude of the input voltage Vin, thereby keeping the drain-source voltage Vds of the fourth NMOS transistor NT4 constant.

If this is described with a specific example as follows.

First, the first supply voltage VDD is 10V, the first reference voltage Vref1 is 5V, the second reference voltage Vref2 is 3V, the input voltage Vin is 4V, and the first to eighth NMOS transistors NT1. Suppose that the threshold voltages (Vth) of NT2, NT3, ..., NT8) are all 1V.

In the second period T2, the first NMOS transistor NT1 is turned on, and a first reference voltage Vref1; 5V is applied to the first node P1, and a first node is applied to the second node P2. 2 reference voltages Vref2; 3V are applied.

That is, 5V is applied to the first node P1 and 3V is applied to the second node P2.

Then, the voltage 5V− is obtained by subtracting the threshold voltage Vth of the third NMOS transistor NT3 from the first reference voltage Vref1; 5V of the first node P1 to the third node P3. 1V = 4V is applied, and the threshold voltage Vth of the fourth NMOS transistor NT4 is applied to the fourth node P4 from the second reference voltage Vref2; 3V of the second node P2. Subtracted voltage (3V-1V = 2V) is applied.

That is, 4V of the first supply voltage VDD; 10V is applied to the third node P3, and 2V of 4V applied to the third node P3 is applied to the fourth node P4. .

At this time, the drain-source voltage Vds of the fourth NMOS transistor NT4, that is, the voltage difference between the third node P3 and the fourth node P4 is 2V.

In addition, the first capacitor C1 connected between the first node P1 and the second node P2 is connected to the second node (5V) from the first reference voltage Vref1; 5V of the first node P1. The voltage (5V-3V = 2V) obtained by subtracting the second reference voltage Vref2 (3V) of P2 is charged.

That is, 2V is charged in the first capacitor C1.

Next, in the third period T3, the fifth and sixth NMOS transistors NT5 and NT6 are turned on so that the input voltage Vin 4V is applied to the second node P2, and The fourth NMOS transistor is connected to the second capacitor C2 connected between the second node P2 and the fifth node P5, in which the fifth node P5 has the same potential as the fourth node P4. The threshold voltage Vth of NT4 is stored.

That is, the voltage of the second node P2 increases from 3V to 4V, and the voltage of the first node P1 increases to 6V by adding 2V charged to the first capacitor C1.

Therefore, the voltage of the third node P3 is the voltage 6V− which is obtained by subtracting the threshold voltage Vth of the third NMOS transistor NT3 from the increased voltage of the first node P1 6V. 1V = 5V), and the voltage of the fourth node P4 is changed from the voltage Vin of the raised second node P2 to 4V and the threshold voltage Vth of the fourth NMOS transistor NT4 is 1V. The voltage is increased to 4V-1V = 3V.

That is, the voltage of the third node P3 increases from 4V to 5V, and the voltage of the fourth node P4 increases from 2V to 3V.

At this time, the drain-source voltage Vds of the fourth NMOS transistor NT4, that is, the voltage difference between the third node P3 and the fourth node P4 is 2V.

That is, the drain-source voltage Vds; 2V of the fourth NMOS transistor NT4 in the second period T2 and the drain of the fourth NMOS transistor NT4 in the third period T3. The source-to-source voltage Vds (2V) remains the same at 2V.

Here, although not separately described, the drain-source voltage Vds of the fourth NMOS transistor NT4 is always constant at 2V even if the input voltage Vin is not 4V and has a value greater than or less than 4V. It can be seen that it is maintained.

However, the difference between the first reference voltage Vref1 and the second reference voltage Vref2 must be kept constant, and the second reference voltage Vref2 must be smaller than the input voltage Vin.

The reason for keeping the difference between the first reference voltage Vref1 and the second reference voltage Vref2 constant is because the voltage difference between the third node P3 and the fourth node P4 is kept constant. The reason for setting the second reference voltage Vref2 smaller than the input voltage Vin is to prevent the change of the drain-source voltage Vds of the NMOS transistor NT4 in the third period T3. This is to prevent the voltage applied to the second node P2 from being discharged to the input line to which the input voltage Vin is applied when the input voltage Vin is applied to the second node P2.

Here, a PMOS transistor may be used instead of the NMOS transistor as the switching element.

As described above, the analog buffer of the present invention does not require a separate current power source to maintain the drain-source voltage Vds of the output transistor as in the related art.

Of course, as shown in FIG. 4, the current power supply NC is further connected between the source of the fourth NMOS transistor NT4 and the second supply voltage VSS to connect the current power source NC to the fourth NMOS transistor NT4. The drain-source voltage Vds can be more effectively stabilized.

In addition, the liquid crystal display using the analog buffer according to the embodiment of the present invention configured as described above, as shown in Figure 5, so as to be perpendicular to the plurality of gate lines (G0) and the gate lines (G) arranged in one direction. A liquid crystal panel having a plurality of data lines D arranged therein, a thin film transistor (not shown) formed at a portion where each of the gate lines G and the data lines D intersect, and the gate lines A gate driver 150 for supplying gate driving pulses to (G) sequentially, a data driver 160 for supplying a data signal to the data lines D, a data driver 160, A plurality of analog buffers 200 are respectively provided between the data lines D to buffer data signals of the data driver 160.

Here, each of the analog buffers 200 may have a circuit configuration as shown in FIG. 2 and may also have a circuit configuration as shown in FIG. 4.

In this case, the data signal is input to the input voltage Vin of the analog buffer.

The data signal is stabilized as described above via the analog buffer 200 and output to each data line D.

The analog buffer 200 may be built in the data driver 160.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The analog buffer and the liquid crystal display using the same according to the present invention have the following effects.

First, since a separate current power source for stabilizing the drain-source voltage of the output transistor is not required, power consumption according to driving of the current power source can be reduced.

Second, since the fluctuation of the drain-source voltage according to the device characteristics of the current power source can be reduced, it provides a more accurate output than before.

1 is a circuit diagram of a conventional analog buffer

2 is a circuit diagram of an analog buffer according to a first embodiment of the present invention.

3 is a timing diagram of a clock signal and a waveform diagram of an output voltage.

4 is a circuit diagram of an analog buffer according to a second embodiment of the present invention.

5 is a configuration diagram of a liquid crystal display using an analog buffer according to an embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings

S1: first clock signal S2: second clock signal

S3: third clock signal S4: fourth clock signal

NT1: first NMOS transistor NT2: second NMOS transistor

NT3: third NMOS transistor NT4: fourth NMOS transistor

NT5: fifth NMOS transistor NT6: sixth NMOS transistor

NT7: Seventh NMOS Transistor NT8: Eighth NMOS Transistor

C1: first capacitor C2: second capacitor

P1: first node P2: second node

P4: third node P4: fourth node

P5: fifth node Vin: input voltage

Vout: Output Voltage 140: Output Line

Reset: Reset signal VDD: First supply voltage

Claims (10)

An input voltage is applied to a gate, a first supply voltage is applied to a drain, and is connected between a gate and a source of the first switching element and a first switching element which outputs a voltage obtained by subtracting a threshold voltage from the input voltage as a source. A buffer unit including a first capacitor configured to charge the threshold voltage of the first switching device; And a voltage variable unit configured to change a first supply voltage applied to a drain of the first switching device according to the magnitude of the input voltage. The method of claim 1, The buffer unit further comprises a second switching device, the first clock signal is applied to the gate, the drain is connected to the source of the first switching device, the drain is connected to the first capacitor. The method of claim 1, The voltage variable part includes a third switching device connected between the first supply voltage and the drain of the first switching device, the input voltage is applied to a gate of the third switching device, and the first supply is supplied to a drain. A voltage is input, and a source is connected to the drain of the first switching element. The method of claim 1, A fourth switching device to which a second clock signal is applied to a gate, a first reference voltage is applied to a drain, and a source is connected to the gate of the third switching device; A fifth switching device to which a second clock signal is applied to a gate, a second reference voltage is applied to a drain, and a source is connected to a common connection terminal of the first switching device and the first capacitor; And a second capacitor connected between the gate of the first switching element and the gate of the third switching element. The method of claim 4, wherein And the second reference voltage is smaller than the input voltage. The method of claim 1, A sixth switching element to which the first clock signal is applied to a gate, the input voltage is applied to a drain, and a source is connected to a source of the fifth switching element; A third clock signal is applied to a gate, the input signal is applied to a drain, and a seventh switching device having a source connected to a common connection terminal of the first capacitor and the second switching device. Analog buffer. The method of claim 1, And an output line connected to a common connection terminal of the source of the first switching element and the drain of the second switching element, and further comprising a discharge unit for discharging the remaining voltage of the output line. The method of claim 6, And the discharge part comprises an eighth switching element to which a fourth clock signal is applied to a gate, a reset signal is applied to a drain, and a source is connected to the output line. The method of claim 1, And a current power supply connected between the source of the first switching element and the second supply power supply for supplying the second supply voltage. A liquid crystal panel having a plurality of gate lines and data lines perpendicular to each other; A data driver to output a data signal for driving a data line of the liquid crystal panel; The data signal is applied to a gate, a first supply voltage is applied to a drain, and a first switching device for outputting a voltage obtained by subtracting a threshold voltage from the data signal to a source, and between the gate and the source of the first switching device. A buffer unit connected to the first capacitor to charge the threshold voltage of the first switching device; And a voltage variable unit configured to change a first supply voltage applied to a drain of the first switching device according to the magnitude of the data signal.