KR20050002051A - Method for forming capacitor having mps grain with improved doping efficiency - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of MPS(Meta-stable Poly-Silicon) structure is provided to improve the doping efficiency by previously crystallizing a storage node before doping. CONSTITUTION: A doped first amorphous silicon layer and an undoped second amorphous silicon layer are sequentially formed on a storage node oxide layer having a groove by in-situ. A storage node(27) is formed by patterning the second and first amorphous silicon layers. MPS grains are grown on the storage node. The storage node is then crystallized. PH3 is doped in the storage node to secure conductivity. A dielectric film(28) and a plate electrode(29) are sequentially formed on the doped storage node.

Description

METHODS FOR FORMING CAPACITOR HAVING MPS GRAIN WITH IMPROVED DOPING EFFICIENCY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method of manufacturing a capacitor.

As the minimum line width of semiconductor devices decreases and the degree of integration increases, the area in which capacitors are formed is gradually narrowing. Even if the area where the capacitor is formed is narrowed, the capacitor in the cell must secure a capacitance of at least about 25 fF required per cell. In order to form a capacitor having a high capacitance on such a small area, a high dielectric constant such as Ta ₂ O ₅ , Al ₂ O _3, or HfO ₂ is substituted for the silicon oxide film (ε = 3.8) and the nitride film (ε = 7). It is possible to increase the effective surface area of a storage node by using a material having a dielectric film as a dielectric film, or dimensionalizing the storage node into a cylinder type or a concave type, or by growing a meta stable-poly silicon (MPS) on the storage node surface. The method of increasing by about 2 times etc. was proposed.

Recently, a technique for a capacitor which has grown the MPS on the surface of a dual storage node to increase the effective surface area of the storage node has been mainly studied. Currently, an inner capacitor structure in which MPS technology is applied only to the inner wall of the capacitor structure is applied to the extent that the cells can be separated from each other.

In order to apply the MPS process in a capacitor structure of a cylinder or concave type, the storage node silicon film is deposited in situ by dividing the storage node silicon film into a doped silicon film serving as a support of the capacitor and an undoped silicon film in which the MPS grain is actually grown.

As design rules become smaller, optimization of MPS grain size and phosphorous doping of grown MPS grains must be optimized to secure capacitance in the same capacitor structure. Moreover, in order for MPS grains to act as lower electrodes, depletion inevitably occurs during operation of the device. In order to do so, MPS grains directly contacting the capacitor dielectric material must be doped in sufficient concentration.

As described above, a method of strengthening externally applied PH ₃ doping conditions, that is, a chamber plasma PH ₃ doping method and a furnace PH ₃ doping method, has been proposed as a conventional technique of phosphorus doping MPS grain in a sufficient concentration. As the aspect ratio increases and the contact size decreases, there is a need for a method to further improve doping efficiency.

1 is a view briefly showing a method of manufacturing a capacitor according to the prior art.

Referring to FIG. 1, an interlayer insulating layer 11 is formed on a substrate (not shown) on which a substructure such as a transistor is formed, and a contact plug 12 is buried in a contact hole formed by etching the interlayer insulating layer 11. An etching barrier layer 13 and a storage node oxide layer 14 are stacked on the interlayer insulating layer 11. Then, the storage node oxide layer 14 and the etching barrier layer 13 are sequentially etched to form grooves in which the storage node is to be formed, and then the storage node 15 having a cylindrical shape is formed in the grooves. Next, after the MPS grain 16 is formed on the inner wall surface of the storage node 15, a PH ₃ doping process is performed to secure the conductivity of the storage node 15 and the MPS grain 16.

For example, the prior art is PH ₃ doping process to adjust the concentration of phosphorus doped flow rate, by adjusting the pressure and temperature of PH ₃ to the doping process, increasing the doping efficiency, the use of the furnace doping to.

FIG. 2 is a diagram illustrating a comparison of phosphorus concentrations according to a conventional furnace doping condition, in which a 400 PH thick undoped silicon film was PH ₃ doped using a furnace doping method. 1, curve C1 is the result of furnace PH ₃ doping at 600 ° C. for 2 hours, curve C2 is the result of furnace PH ₃ doping at 700 ° C. for 2 hours, and curve C3 is the result of eliminating furnace PH ₃ doping. .

Referring to FIG. 2, the curve C1 (600 ° C., 2 hours, furnace PH ₃ doping) shows that the phosphorus concentration was maintained at a level of 5 × 10 ^{20 on the} surface of the undoped silicon film, and the phosphorus concentration was exceeded from 100 μs on the surface. It can be seen that the decrease rapidly. That is, the entire 400 Å thick undoped silicon film is not sufficiently doped.

In the case of curve C2 (700 ° C., 2 hours, furnace PH ₃ doping), the phosphorus concentration was maintained at 5 × 10 ^{19 on the} surface of the undoped silicon film, but the phosphorus concentration suddenly exceeded 100 kPa on the surface. It can be seen that the decrease. That is, it can be seen that the doping ability is lower than that of the curve C1.

Comparing curves C1 and C2, both results show that the 400 Å thick undoped silicon film is not sufficiently doped, and that the phosphorus concentration on the surface of the undoped silicon film is further decreased when the temperature rises. have.

In general, the phosphorus concentration on the surface of the undoped silicon film is determined by the extent to which PH ₃ entering the doping gas reacts with the surface of the undoped silicon film. That is, the phosphorus concentration on the surface of the undoped silicon film is purely determined by the difference between the amount of PH ₃ in the gaseous state attached to the silicon surface and the amount of phosphorus already attached to the surface desorbed from the silicon surface and escaped into the gaseous state. It is determined by the amount present in the. In the curve C2 having a doping temperature of 700 ° C., the amount of desorption from the surface is greater than that of the curve C1 having a doping temperature of 600 ° C. rather than the amount attached to the surface.

As described above, in the prior art, the method of increasing the amount of phosphorus introduced into the MPS grain surface in the gas state to increase the doping efficiency, that is, to enhance the doping efficiency by strengthening the external PH ₃ doping conditions (flow rate, pressure, temperature) However, according to the result of FIG. 1, the doping efficiency increase effect does not reach the entire area of the storage node.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and a method of manufacturing a capacitor of a semiconductor device capable of maximizing the doping capability of subsequent phosphorous (P) doping so as to extend to the entire area of the storage node when applying the MPS process. The purpose is to provide.

1 is a view briefly showing a method of manufacturing a capacitor according to the prior art,

2 is a view comparing the phosphorus concentration according to the conventional furnace doping conditions,

3A to 3G are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21: interlayer insulating film 22: contact plug

23: etching barrier layer 24: separator pattern between storage nodes

25: first amorphous silicon film 26a: MPS grain

27: storage node 28: dielectric film

29: plate

A method of manufacturing a capacitor of the present invention for achieving the above object is to form a first amorphous silicon film doped with impurities and a second amorphous silicon film doped with no impurities in situ, the first amorphous silicon film and the Patterning a second amorphous silicon film to form a storage node, growing MPS grains on a surface of the storage node, crystallizing the storage node on which the MPS grains are grown, and securing the conductivity that the storage node should have. Doping impurities into the storage node, and sequentially forming a dielectric film and a plate on the storage node doped with the impurity, and crystallizing the storage node having the MPS grain grown thereon, By nitrogen annealing at temperatures between 650 ° C and 750 ° C Characterized in, and the nitrogen annealing is characterized by using a rapid thermal annealing furnace equipment or equipment.

In addition, the method of manufacturing the capacitor of the present invention comprises the steps of forming an insulating film having a contact hole on the upper portion of the semiconductor substrate, forming a plug embedded in the contact hole and connected to the semiconductor substrate, the plug and the insulating film on the Forming a separator having grooves for exposing the plug, and forming an in-situ first amorphous silicon film doped with impurities and a second amorphous silicon film not doped with impurities at all over the groove including the grooves of the separator; Patterning a first amorphous silicon film and the second amorphous silicon film to form a cylindrical storage node in a groove of the separator, growing MPS grains on an inner wall surface of the storage node, and storing the MPS grains Crystallizing the node, in order to ensure conductivity that the storage node should have Doping an existing storage node with impurities, selectively removing the separator, further doping the storage node with impurities, and sequentially forming a dielectric layer and a plate on the storage node doped with the impurities. It is characterized by including.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3A to 3G are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.

As shown in FIG. 3A, an interlayer insulating film 21 is formed on a substrate (not shown) on which a substructure such as a transistor is formed, and a contact hole for electrically connecting an impurity region of the substrate and a storage node is formed. The conductive material is deposited thereon and planarized by chemical mechanical polishing or etch back to form the contact plug 22. Subsequently, an etch barrier film 23 is deposited on the entire surface, and plasma enhanced tetra ethyl ortho silicate (PE-TEOS), boron phosphorus silicate glass (BPSG), phosphorus silicalicate glass (PSG), or USG is formed on the etching barrier film 23 Storage node oxide such as (Undoped Silicate Glass) is deposited. At this time, the storage node oxide film is formed to a thickness of 15000 ~ 25000Å.

Next, the storage node oxide layer and the etching barrier layer 23 are sequentially etched to form an inter-storage node isolation layer pattern 24 having a groove exposing the contact plug 22 in a region where the storage node is to be formed. In this case, the etch barrier layer 23 stops the etching of the oxide layer when the isolation pattern 24 between the storage nodes is formed. The etching barrier layer 23 has a good etching selectivity with respect to the isolation pattern 24 between the storage nodes, for example, silicon nitride. To form. The etching barrier layer 23 serves to support the storage node having a high height from the side thereof, thereby obtaining a storage node having excellent mechanical strength.

In addition, the stacking order of the etching barrier film 23 may be changed. That is, after forming the interlayer insulating layer 21 and the etching barrier layer 23, forming the contact hole and the contact plug 22, a storage node oxide layer for forming the interlayer storage layer pattern 24 on the front surface is formed. Can be formed.

As shown in FIG. 3B, the first amorphous silicon film 25 doped with impurities and the second amorphous silicon film 26 doped with no impurities are disposed on the entire surface including the grooves of the isolation pattern 24 between the storage nodes. Form in succession in situ.

The reason why the first amorphous silicon film 25 doped with impurities and the second amorphous silicon film 26 without doping impurities is formed in situ is that the silicon valence is high in the amorphous silicon film having a high concentration of doping impurities. In the amorphous silicon film which is hardly moved and does not grow MPS grains and is not doped with impurities, silicon atoms are rapidly moved and MPS grains are easily grown. That is, the first amorphous silicon film 25 doped with impurities becomes an outer wall forming a skeleton of a cylinder shape of the storage node, and the second amorphous silicon film 26 not doped with impurities is formed on an inner wall of a cylinder shape. MPS grains become. Therefore, even though the silicon atoms of the second amorphous silicon film 26 which become the MPS grains are almost moved to grow to the MPS grains, the movement of the silicon atoms in the first amorphous silicon film 25 is stopped to form a skeleton of the storage node. In order to do this, the doping concentration of the first amorphous silicon film 25 is increased.

During such in-situ deposition of the first and second amorphous silicon films 25 and 26, phosphorus (P) may be used as an impurity doped in the first amorphous silicon film 25, and the first amorphous silicon film 25 may be used. Phosphorus (P) can be doped simultaneously with the deposition of. At this time, the doping concentration of phosphorus (P) can be adjusted by controlling the flow rate of the impurity source gas containing phosphorus compared to the silicon source gas, the silicon source gas as monosilane (diosilane), disilane (disilane), trisilane (trisilane) Silane gas such as dichlorosilane, and the impurity source gas containing phosphorus use PH ₃ gas. The phosphorus (P) doping concentration of the first amorphous silicon film 25 is set in consideration of the time to move the silicon atoms, the size of the silicon grain to be grown, and the like, and a high doping of about 1E20 to 3E21 / cm ³ using SIMS. Have a concentration. The phosphorus (P) doping concentration of about 1.0E20 / cm ^{3 to} 3E21cm ³ increases the contact resistance between the contact plug 22 and the storage node or depletion of the storage node due to the lack of doping. It is enough to solve the problem causing the reduction.

On the other hand, the thickness of the first amorphous silicon film 25 and the second amorphous silicon film 26 is determined according to the degree of integration of the desired device, the height, the width of the storage node, etc. In the present invention, the thickness of the amorphous silicon film The total thickness should be 300Å to 600Å. The deposition temperature of the first amorphous silicon film 25 and the second amorphous silicon film 26 is maintained at 500 ° C. to 550 ° C., which is not amorphous when the silicon film is deposited at a temperature of 550 ° C. or higher. This is because it has a crystalline form. MPS grains cannot be grown in the crystalline silicon film.

Next, the first amorphous silicon film 25 and the second amorphous silicon film 26 formed on the separation layer pattern 24 between the storage nodes are removed by chemical mechanical polishing or etch back. A storage node in the form of a cylinder serving as a double layer of the 25 and the second amorphous silicon film 26 is formed. In this case, when the first amorphous silicon film 25 and the second amorphous silicon film 26 are removed, impurities such as abrasives or etched particles may adhere to the inside of the cylinder. After filling the inside of the cylinder with the photoresist, it is preferable to perform polishing or etch back until the interlayer storage layer pattern 24 is exposed, and ashing and removing the photoresist inside the cylinder.

As shown in FIG. 3C, MPS grains 26a are grown on the inner wall of the storage node. The method of growing the MPS grains 26a is performed by forming a silicon seed on the surface of the second amorphous silicon film 26 using a silane-based gas and then moving the silicon by annealing at a temperature of 600 ° C to 650 ° C. That is, the second amorphous silicon film 26 which is not doped with impurities is grown into the MPS grains 26a. When the MPS grains 26a are grown in this way, the movement of silicon atoms in the first amorphous silicon film 25 is suppressed while the silicon atoms of the second amorphous silicon film 26 are moved to grow into the MPS grains 26a. . At this time, especially in order to increase the size of the MPS grains 26a, when the silicon atoms of the second amorphous silicon film 26 are mostly moved to grow to the MPS grains 26a, the silicon atoms of the second amorphous silicon film 26 are The first amorphous silicon film 25 may be exposed between the grown MPS grains 26a, which are mostly exhausted, and grow between the grown MPS grains 26a. In this manner, even when the second amorphous silicon film 26 is exhausted to grow to the MPS grains 26a, the first amorphous silicon film 25 having a high doping concentration of phosphorus (P) is suppressed in a small amount so that at least the The storage node skeleton as thick as one amorphous silicon film 25 is maintained.

Also be carried out, the annealing nitrogen (N ₂ annealing) at 650 ℃ ~750 ℃ temperature as shown in 3d. Here, the annealing equipment is a rapid heat treatment [RTP; Rapid Thermal Process] Equipment or Furnace equipment is used, anneal for 2 to 5 minutes in rapid heat treatment equipment, and 30 minutes to 1 hour in furnace equipment.

By this nitrogen annealing, the first amorphous silicon film 25 and the MPS grains 26a are crystallized. Hereinafter, the crystallized first amorphous silicon film 25 and the MPS grains 26a are referred to as storage nodes 27.

As described above, the present invention crystallizes the storage node before proceeding to the PH ₃ doping process. That is, the MPS grains 26a and the first amorphous silicon film 25 thereunder are crystallized before the PH ₃ doping, so that the phosphorous (P) that enters the surface from the outside during the subsequent PH ₃ doping process is a fast diffusion path of the MPS grains ( High phosphorous doping effect can be achieved by diffusing through the grain boundary of 26a).

For example, the diffusion rate of the dopant diffused through the grain boundary of the crystallized silicon film is about 10 to 100 times larger than the diffusion rate of the dopant diffused through the amorphous silicon film. After the subsequent deposition of the dielectric film, a high temperature annealing process diffuses along the phosphorus concentration gradient into the silicon grain, thereby obtaining a high doping effect.

As shown in FIG. 3E, the PH ₃ doping process is performed to secure the conductivity that the crystallized storage node 27 should have, for example, the phosphorus (P) doping concentration of the storage node 27. At this time, the PH ₃ doping process is not only for doping the phosphorus (P) to the MPS grains 26a which are not doped with impurities, but also the doping concentration of the phosphorus (P) that was doped during the deposition of the first amorphous silicon film 25. It is a process to increase. First, in order to increase the doping efficiency of the PH ₃ doping process, the surface of the storage node 27 on which the MPS grains are grown is cleaned by using HF chemicals or BOE chemicals, and then phosphorus (P) is applied to the MPS grains by performing PH ₃ doping. Doping In addition, the doping concentration of phosphorus (P) in the first amorphous silicon film 25 that has already been formed is also increased. By using the PH ₃ gas as a reaction gas and diffusing into the storage node 27 by a diffusion process, the doping concentration of phosphorus (P) is uniformly distributed over the entire area of the storage node 27.

Hereinafter, various examples of the PH ₃ doping process will be given.

First, the PH ₃ doping process uses a chamber plasma doping method. Chamber plasma doping is a method of doping phosphorus by generating a plasma of PH ₃ gas in the chamber. The process temperature is 700 ° C to 800 ° C, the process time is 2 minutes to 5 minutes, and the process pressure and plasma power are 1.5 tor to 2.5 tor and 300 to 500 W, respectively. At this time, the flow rate of the PH ₃ gas is 300 sccm to 500 sccm.

Secondly, the PH ₃ doping process uses a furnace doping method. The furnace doping method is a method of doping phosphorus using a PH ₃ gas in a furnace, the process temperature is 600 ℃ to 700 ℃, the process time is 1 hour to 2 hours, the process pressure and the flow rate of PH ₃ gas 5 to 10 torr and 100 sccm to 200 sccm, respectively.

As shown in FIG. 3F, the separator pattern 24 between storage nodes is diped out using a wet chemical of HF or BOE. After the wet deep out process, the PH ₃ doping process is further performed. This additional PH ₃ doping process is to improve the doping efficiency of the phosphorus (P) in the storage node 27 and to correct the doping profile of the phosphorus (P). That is, since the phosphorus (P) on the surface of the storage node 27 is detached during the wet deep out of the separator pattern 24 between the storage nodes, depletion may occur due to the lack of doping concentration, and thus, additionally through the PH ₃ doping process. Phosphorus doping the storage node (27).

In detail, the PH ₃ doping process is performed in addition to the storage node 27 exposed to the inner wall and the outer wall through the wet deep-out of the separator pattern 24 between the storage nodes.

Additional PH ₃ doping processes use chamber plasma doping or furnace doping.

First, the chamber plasma doping method is performed at a temperature of 700 ° C. to 800 ° C., a process time of 1 to 3 minutes, a process pressure of 1.5 tor to 2.5 tor, and a plasma power of 300 W to 500 W at a pH of ₃₀₀ sccm to 500 sccm. Proceed with flow.

In the furnace doping method, the process temperature is 600 ° C. to 700 ° C., the process time is 1 hour to 2 hours, and the process pressure and the flow rate of the PH ₃ gas are 5 tor to 10 tor and 100 sccm to 200 sccm, respectively.

Next, as shown in FIG. 3G, the dielectric film 28 and the plate 29 are formed to complete the capacitor. Herein, the dielectric film 28 uses oxidized Si ₃ N ₄ , Ta ₂ O ₅ , Al ₂ O ₃ , HfO ₂ , and the plate 29 is a doped polysilicon film or a doped polysilicon film and titanium nitride. A double film of a ride film (TiN) is used.

According to the embodiment as described above, PH ₃ written because pre-crystallization the storage node before the doping process, PH _3, without enhancement of the doping process in contact with the surface and contact plug 22 of the storage node (27) sufficiently to the floor-area Doping may be performed, thereby sufficiently securing the contact resistance between the storage node 27 and the contact plug 22 and the conductivity of the storage node 27.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention has an effect of increasing the doping efficiency of phosphorus by simply doping phosphorus after crystallizing the storage node without increasing the PH ₃ doping condition applied from the outside.

In addition, since only the nitrogen annealing process is added, cost reduction can be obtained.

Claims (18)

Forming in-situ a first amorphous silicon film doped with impurities and a second amorphous silicon film not doped with impurities at all; Patterning the first amorphous silicon film and the second amorphous silicon film to form a storage node; Growing MPS grains on the storage node surface; Crystallizing the storage node on which the MPS grain is grown; Doping impurities into the storage node to ensure conductivity that the storage node should have; And Sequentially forming a dielectric film and a plate on the impurity doped storage node Method of manufacturing a capacitor comprising a. The method of claim 1, Crystallizing the storage node in which the MPS grain is grown, A method for producing a capacitor, characterized in that it is made through nitrogen annealing. The method of claim 2, The nitrogen annealing, A process for producing a capacitor, which proceeds at a temperature of 650 ° C to 750 ° C. The method of claim 2, The nitrogen annealing method of manufacturing a capacitor, characterized in that using a rapid heat treatment equipment or furnace equipment. The method of claim 1, Doping impurities to the storage node, A method for producing a capacitor, comprising using a chamber plasma doping method or a furnace doping method. The method of claim 5, The chamber plasma doping method, A plasma power of 300W to 500W is applied at a temperature of 700 ° C to 800 ° C and a pressure of 1.5torr to 2.5torr, and is performed for 2 to 5 minutes while flowing a PH ₃ gas at a flow rate of 300sccm to 500sccm. Method of manufacturing a capacitor. The method of claim 5, The furnace doping method, A process for producing a capacitor, wherein the pH ₃ gas is flowed at 100 sccm to 200 sccm at a temperature of 600 ° C. to 700 ° C. and a pressure of ₅ tor to 10 tor. Forming an insulating film having a contact hole on the semiconductor substrate; Forming a plug embedded in the contact hole and connected to the semiconductor substrate; Forming a separator having a groove exposing the plug on the plug and the insulating layer; Forming in-situ a first amorphous silicon film doped with impurities and a second amorphous silicon film not doped with impurities at all over the groove including the groove of the separator; Patterning the first amorphous silicon film and the second amorphous silicon film to form a cylindrical storage node in a groove of the separator; Growing MPS grains on an inner wall surface of the storage node; Crystallizing the storage node on which the MPS grain is grown; Doping impurities into the storage node to ensure conductivity that the storage node should have; Selectively removing the separator; Doping impurities further into the storage node; And Sequentially forming a dielectric film and a plate on the impurity doped storage node Method of manufacturing a capacitor comprising a. The method of claim 8, Crystallizing the storage node in which the MPS grain is grown, A method for producing a capacitor, characterized in that it is made through nitrogen annealing. The method of claim 9, The nitrogen annealing, A process for producing a capacitor, which proceeds at a temperature of 650 ° C to 750 ° C. The method of claim 9, The nitrogen annealing method of manufacturing a capacitor, characterized in that using a rapid heat treatment equipment or furnace equipment. The method of claim 8, Doping impurities to the storage node, A method for producing a capacitor, comprising using a chamber plasma doping method or a furnace doping method. The method of claim 12, The chamber plasma doping method, A plasma power of 300W to 500W is applied at a temperature of 700 ° C to 800 ° C and a pressure of 1.5torr to 2.5torr, and is performed for 2 to 5 minutes while flowing a PH ₃ gas at a flow rate of 300sccm to 500sccm. Method of manufacturing a capacitor. The method of claim 12, The furnace doping method, A process for producing a capacitor, wherein the pH ₃ gas is flowed at 100 sccm to 200 sccm at a temperature of 600 ° C. to 700 ° C. and a pressure of ₅ tor to 10 tor. The method of claim 8, After growing the MPS grain, And cleaning the surface of the storage node. The method of claim 15, Cleaning the surface of the storage node, A method for producing a capacitor, characterized by using HF chemical or BOE chemical. The method of claim 8, Doping impurities in addition to the storage node, The chamber plasma doping method is used, wherein the chamber plasma doping method is applied to the plasma power of 300W to 500W at a temperature of 700 ℃ to 800 ℃ and a pressure of 1.5torr to 2.5torr, the PH ₃ gas at a flow rate of 300sccm ~ 500sccm A method for producing a capacitor, which is performed for 1 to 3 minutes while flowing. The method of claim 8, Doping impurities in addition to the storage node, The furnace doping method is used, wherein the furnace doping method is performed at a temperature of 600 ° C. to 700 ° C. and a pressure of ₅ tor to 10 torr for 1 hour to 2 hours while flowing PH ₃ gas at 100 sccm to 200 sccm. Manufacturing method.