KR100548846B1 - Method for fabricating capacitor with improved doping uniformity - Google Patents

Abstract

The present invention is to provide a method of manufacturing a capacitor suitable for preventing the decrease in efficiency of the PH ₃ doping process according to the increase of the aspect ratio, and to prevent the formation of a low dielectric layer on the storage node surface during the deposition of the dielectric film, the manufacturing of the capacitor of the present invention The method includes forming a storage node having MPS grain grown on a surface, doping phosphorus on the storage node using a plasma doping method, and then injecting additional phosphorus on the storage node using a furnace doping method. Forming a nitride film on the surface of the storage node by TU-nitriding, forming a dielectric film on the nitride film, and forming an upper electrode on the dielectric film.

Capacitor, MPS, Doping Efficiency, Plasma Doping, Furnace Doping, Nitriding

Description

METHODS FOR FABRICATING CAPACITOR WITH IMPROVED DOPING UNIFORMITY}             

1 is a view showing the structure of an MPS capacitor formed according to the prior art,

2A to 2H are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention;

3 is a result of observing the concentration profile of phosphorus in the storage node.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 interlayer insulating film

23: contact plug 24: etching barrier film

25: storage node oxide layer 26c: storage node

26d: MPS grain 27: silicon nitride film

28: dielectric film 29: plate

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a capacitor.

As the minimum line width of semiconductor devices decreases and the degree of integration increases, the area in which capacitors are formed is gradually narrowing. Even if the area where the capacitor is formed is narrowed, the capacitor in the cell must secure a capacitance of at least about 25 fF required per cell. In order to form a capacitor having a high capacitance on such a small area, a high dielectric constant such as Ta ₂ O ₅ , Al ₂ O _3, or HfO ₂ is substituted for the silicon oxide film (ε = 3.8) and the nitride film (ε = 7). Method of using a material having a dielectric film as a dielectric film, three-dimensional storage node into a cylinder type, a concave type, or growing a stable stable poly silicon (MPS) or a hemisphere grain (HSG) on the storage node surface. A method of increasing the effective surface area of a storage node by 1.7 to 2 times has been proposed.

Recently, a technique for a capacitor that has grown the effective surface area of a storage node by growing MPS or HSG on a dual storage node surface has been mainly studied. In the manufacturing method of the MPS capacitor, after forming a storage node made of an amorphous silicon film, a silane (Silane, SiH ₄ ) -based gas is injected into the seed gas and silicon atoms are migrated around the seed in a vacuum state. A method of growing MPS is known. At this time, the injection time, flow rate and temperature of the seed gas, the time, temperature and pressure of moving the silicon atoms, as well as the moving speed and amount of the silicon atoms vary according to the doping concentration of the impurities, resulting in a different size and amount of the MPS grown. You lose.

Currently, an inner capacitor structure in which MPS technology is applied only to the inner wall of the capacitor structure is applied to the extent that the cells can be separated from each other.

The structure of the MPS capacitor formed according to this conventional method is shown in FIG.

1 is a view showing the structure of an MPS capacitor formed according to the prior art.

As shown in FIG. 1, in the conventional MPS capacitor, an insulating film 12 is formed on the semiconductor substrate 11, and a contact plug 13 penetrating the insulating film 12 is connected to the semiconductor substrate 11. The storage node 14 having the MPS grains 15 formed in all regions of the contact portion is in contact with the contact plug 13. The dielectric film 16 and the plate 17 are formed on the storage node 14.

The storage node 14 is supported by a laminated film of the etch barrier film 18 and the storage node oxide film 19.

In FIG. 1, after forming the storage node 14 having the MPS grains 15 formed thereon, a PH ₃ doping process is performed to secure conductivity to dope the storage node 14 with a phosphorous.

Recently, with the development of highly integrated DRAM devices having a circuit line width of 0.13 μm or less, the cell size has to be reduced and the height of the storage node has to be increased in order to secure the capacitance of the capacitor, which leads to an increase in the aspect ratio of the storage node. do.

However, if the aspect ratio of the storage node is increased, the efficiency of PH ₃ doping process on the storage node having the MPS grain is reduced, and phosphorous doping is not performed properly. Thus, a depletion layer is formed at the lower electrode during device operation, thereby reducing capacitance. Results in. For example, when the height of the storage node is increased, it is difficult to sufficiently dope the bottom of the storage node in contact with the contact plug during the PH ₃ doping process.

In addition, in the prior art, a portion of the storage node is oxidized during the deposition of a dielectric film to form a low dielectric layer such as SiO ₂ , resulting in a decrease in capacitance.

The present invention has been proposed to solve the above problems of the prior art, a capacitor suitable for preventing the degradation of the efficiency of the PH ₃ doping process due to the increase in the aspect ratio, and to prevent the formation of a low dielectric layer on the storage node surface during the deposition of the dielectric film It is an object to provide a manufacturing method.

According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of the present invention, the method comprising: forming a storage node having MPS grain grown on a surface thereof, doping phosphorus by using a plasma doping method on the storage node, and furnace doping the storage node. Further doping phosphorus using a method, followed by nitriding in situ to form a nitride film on the storage node surface, forming a dielectric film on the nitride film, and forming an upper electrode on the dielectric film. In the doping of phosphorus using the plasma doping method, the plasma power of 300 W to 450 W is applied under a pressure of 1 tor to 2 torr, and the PH ₃ gas is flowed at a flow rate of 300 sccm to 450 sccm. It is characterized in that for proceeding from seconds to 140 seconds, and further doping the phosphorus using the furnace doping method The process is carried out for 1 hour to 2 hours while flowing a pH ₃ gas at a flow rate of 100 sccm to 200 sccm under a process temperature of 600 ° C. to 700 ° C. and a pressure of ₅ tor to 20 tor, and the nitriding treatment proceeds with the furnace doping method. It is characterized in that the furnace is run for 30 minutes to 120 minutes while flowing NH ₃ gas at a flow rate of 1000 sccm to 5000 sccm at a temperature of 650 ° C. to 800 ° C. and a pressure of ₅ tor to 30 tor in one furnace.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A to 2H are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.

As shown in FIG. 2A, an interlayer insulating film 22 is formed on a semiconductor substrate 21 on which a substructure such as a transistor is formed, and a contact hole for electrically connecting an impurity region of the semiconductor substrate 21 to a storage node. After forming, the conductive material is laminated thereon and planarized by chemical mechanical polishing or etch back to form the contact plug 23. Subsequently, an etch barrier layer 24 is deposited on the entire surface, and the plasma enhanced tetra ethyl ortho silicate (PE-TEOS), boron phosphorus silicate glass (BPSG), phoshporus silicate glass (PSG), or USG is formed on the etch barrier layer 24. Storage node oxide such as (Undoped Silicate Glass) is deposited. At this time, the storage node oxide film is formed to a thickness of 15000 kPa to 30000 kPa.

Subsequently, the storage node oxide layer and the etching barrier layer 24 are sequentially etched to form an isolation layer pattern 25 between the storage nodes exposing the contact plugs 23 in the region where the storage node is to be formed. In this case, the etch barrier layer 24 stops the etching of the oxide layer when the isolation pattern 25 between the storage nodes is formed. The etching barrier layer 24 has a good etching selectivity with respect to the isolation pattern 25 between the storage nodes, for example, silicon nitride. To form. The etching barrier layer 24 serves to support the storage node having a high height from the side, thereby obtaining a storage node having excellent mechanical strength.

In addition, the stacking order of the etching barrier film 24 may be changed. That is, after forming the interlayer insulating layer 22 and the etching barrier layer 24, forming the contact hole and the contact plug 23, the storage node oxide layer for forming the isolation layer pattern 25 between the storage nodes is formed on the entire surface. Can be formed.

As shown in FIG. 2B, the first amorphous silicon layer 26a doped with impurities and the second amorphous silicon layer 26b without doping any impurities are identified on the entire surface including the isolation layer pattern 25 between storage nodes. Formed continuously in a tu

The reason for forming the first amorphous silicon film 26a doped with impurities and the second amorphous silicon film 26b not doped with impurities at all is that the silicon atoms are high in the amorphous silicon film having a high concentration of doping impurities. In the amorphous silicon film which is hardly moved and does not grow silicon grain and is not doped with impurities, silicon atoms are quickly moved to easily grow silicon grain. That is, the first amorphous silicon film 26a doped with impurities becomes an outer wall forming a skeleton of a cylinder shape of the storage node, and the second amorphous silicon film 26b without doping impurities is formed on an inner wall of a cylinder shape. MPS grains become. Therefore, even though the silicon atoms of the second amorphous silicon film 26b which become the MPS grains are almost moved to grow into the MPS grains, the movement of the silicon atoms in the first amorphous silicon film 26a is stopped to form a skeleton of the storage node. In order to do this, the doping concentration of the first amorphous silicon film 26a is increased.

During such in-situ deposition of the first and second amorphous silicon films 26a and 26b, phosphorus (P) may be used as an impurity doped into the first amorphous silicon film 26a, and the first amorphous silicon film 26a may be used. Phosphorus (P) can be doped simultaneously with the deposition of. At this time, the doping concentration of phosphorus (P) can be adjusted by adjusting the flow rate of the impurity source gas containing phosphorus (P) relative to the silicon source gas, the silicon source gas as silane (silane), disilane (trisilane), trisilane Silane-based gases such as trisilane and dichlorosilane are used, and an impurity source gas containing phosphorus uses a PH ₃ gas. For example, the first amorphous silicon film 26a is deposited using silane (SiH ₄ ) gas and PH ₃ gas, and the second amorphous silicon film 26b is deposited using only SiH ₄ gas.

The phosphorus (P) doping concentration of the first amorphous silicon film 26a is set in consideration of the time to move the silicon atoms, the size of the MPS grains to be grown, and the like. ^Have a doping concentration of about ³ . The phosphorus (P) doping concentration of about 1.0E20 / cm ^{3 to} 3E21cm ³ is a doping concentration that can suppress depletion of the storage node due to lack of doping.

On the other hand, the thickness of the first amorphous silicon film 26a and the second amorphous silicon film 26b is determined depending on the degree of integration of the desired device, the height, the width of the storage node, and the like. In addition, during in-situ deposition of the first amorphous silicon film 26a and the second amorphous silicon film 26b, the deposition temperature is maintained at 500 ° C. to 530 ° C., which is not amorphous when the silicon film is deposited at a temperature of 530 ° C. or higher. This is because it has a crystalline form. MPS grains cannot be grown in the crystalline silicon film.

As illustrated in FIG. 2C, the first amorphous silicon layer 26a and the second amorphous silicon layer 26b formed on the separation layer pattern 25 between storage nodes are removed by chemical mechanical polishing or etch back. A cylinder 26 serving as a double layer of the first amorphous silicon film 26a and the second amorphous silicon film 26b is formed. Here, when removing the first amorphous silicon film 26a and the second amorphous silicon film 26b, impurities such as abrasives or etched particles may adhere to the inside of the cylinder 26. For example, after filling the inside of the cylinder 26 with photoresist, polishing or etching back is performed until the inter-storage separator pattern 25 is exposed, and ashing the photoresist inside the cylinder 26. It is good to remove it.

As shown in FIG. 2D, MPS grains 26d are grown on the inner wall of the storage node 26c. Here, the storage node 26c is crystalline of the first amorphous silicon film 26a, and the MPS grain 26d is crystalline of the second amorphous silicon film 26b.

The method of growing the MPS grains 26d is performed by forming a silicon seed on the surface of the second amorphous silicon film 26b using a silane-based gas and then moving the silicon by annealing at a temperature of 600 ° C to 650 ° C. . That is, the second amorphous silicon film 26b without doping impurities grows into the MPS grain 26d.

When the MPS grains 26d are grown in this way, the silicon atoms in the first amorphous silicon film 26a are suppressed while the silicon atoms of the second amorphous silicon film 26b are moved to grow into the MPS grains 26d. In addition, the first amorphous silicon film 26a and the MPS grain 26b are crystallized by annealing at 600 ° C to 650 ° C. At this time, especially in order to increase the size of the MPS grain 26b, when the silicon atoms of the second amorphous silicon film 26b are mostly moved to grow into the MPS grain 26b, the silicon atoms of the second amorphous silicon film 26b are The first amorphous silicon film 26a may be exposed between the grown MPS grains 26d, which are mostly exhausted to grow into the MPS grains 26d. In this manner, even when the second amorphous silicon film 26b is exhausted and grown to MPS grains 26d, the first amorphous silicon film 26a having a high doping concentration of phosphorus (P) is suppressed in a small amount, so that at least The storage node skeleton as thick as the first amorphous silicon film 26a is maintained.

As described above, the crystalline first amorphous silicon film 26a becomes a storage node 26c, and a structure in which the MPS grain 26d is grown on the surface of the storage node 26c is formed.

As shown in FIG. 2E, PH ₃ is required to ensure the doping concentration of phosphorus (P) of the storage node 26c and the MPS grain 26d, such as the storage node 26c and the MPS grain 26d. Proceed with the doping process.

Using the HF chemical to BOE chemical to increase the doping efficiency of PH ₃ doping step prior to proceeding with the PH ₃ doping process to be cleaned the growth storage node (26c) grain surfaces MPS (26d).

The above-described PH ₃ doping process is to increase the doping concentration of phosphorus (P) in the storage node 26c which has already been doped with phosphorus (P) in the MPS grain (26d).

The plasma doping method is used as a method of the PH ₃ doping process. Here, the plasma doping method is a method of doping the phosphorus by generating a plasma of the PH ₃ gas in the chamber, the plasma power is 300W ~ 450W, the flow rate of PH ₃ gas is 300sccm ~ 450sccm The pressure is 1 to 2 tor, and the doping time is 70 to 140 seconds.

The plasma doping method as described above physically doped phosphorus (P) on the surface of the storage node 26c, that is, MPS grains 26d that are not doped with any impurities, and thus the doping concentration of the surface of the storage node 26c. Can be satisfied, but is insufficient to meet the doping concentration of the bottom portion in contact with the contact plug (23).

Accordingly, the present invention further provides a doping concentration to the bottom portion in contact with the contact plug 23 by further proceeding the furnace doping method to have a uniform doping concentration over the entire area of the storage node 26c. do.

As shown in FIG. 2F, the furnace doping method is carried out as an additional PH ₃ doping process. Here, the furnace doping method is to proceed the doping process through the heat treatment using the furnace (Furnace), the process temperature is 600 ℃ ~ 700 ℃, the flow rate of PH ₃ gas is 100sccm ~ 200sccm, the pressure is 5torr ~ It is 20 torr and doping time is 1 hour-2 hours.

On the other hand, in the case where the furnace doping method is performed immediately without performing the plasma doping method, the doping concentration may be satisfied up to the bottom portion in contact with the contact plug 23, but due to the long-term heat treatment, If P) is excessively diffused, there is a disadvantage in that required surface concentration cannot be obtained.

Therefore, the present invention combines the advantages of the plasma doping method and the furnace doping method to provide a uniform doping concentration over the entire area of the storage node 26c by performing the PH ₃ doping process.

As described above, the PH ₃ doping process combining the plasma doping method and the furnace doping method can sufficiently meet the doping concentration of the bottom portion in contact with the contact plug 23 while ensuring the surface doping concentration. The contact plug 23 may be the most preferable method for securing contact resistance and securing the conductivity of the storage node 26c.

After the furnace doping, the supply of the PH ₃ gas is stopped and the nitriding process is performed in situ. In this case, the nitriding process is performed to form an oxidation barrier for preventing the surface of the storage node 26c from being oxidized during subsequent dielectric film deposition.

In the nitriding process described above, NH ₃ gas is flowed at a flow rate of 1000 sccm to 5000 sccm, the process temperature is 650 ° C. to 800 ° C., the pressure is 5 tor to 30 tor, and the nitriding time is 30 to 120 minutes. After such a nitriding process, silicon nitride films (Si ₃ N ₄ , 27) are formed on the surface of the storage node 26c on which the MPS grains 26c have been grown to have a thickness of 5 Å to 15 Å.

Figure 2g shows the structure completed until the in-situ nitriding process.

As shown in FIG. 2G, when the silicon nitride layer 27 is formed on the surface of the storage node 26c, the capacitance acts as an anti-oxidation layer to suppress an oxide layer that is excessively generated on the storage node 26c during subsequent deposition of the dielectric layer. Improve.

In addition, the silicon nitride film 27 serves to prevent out-diffusion of phosphorus (P) doped into the storage node 26c, and the nitriding process is performed at a temperature of 650 ° C to 800 ° C in the furnace. As the process proceeds, the activation of the doped phosphorus is optimized to minimize generation of a depletion layer at the storage node 26c during device operation. On the other hand, if the silicon nitride film 27 is not formed, even though phosphorus is sufficiently doped by plasma doping and furnace doping, external diffusion of doped phosphorus (P) occurs during the subsequent high temperature thermal process. This results in a reduced doping concentration.

Therefore, the plasma PH ₃ doping, furnace PH ₃ doping and in situ nitriding processes must be carried out continuously to obtain the effects listed above.

Next, as shown in FIG. 2H, the dielectric film 28 and the plate 29 are sequentially formed on the entire surface including the silicon nitride film 27.

The dielectric film 28 is selected from Al ₂ O ₃ , HfO _2, or Ta ₂ O ₅ , and is deposited to have a thickness of 30 kPa to 100 kPa using atomic layer deposition (ALD), which is capable of having a high step coverage and low temperature process. For example, in the atomic layer deposition method of Al ₂ O ₃ , TMA [Tri Methyl Aluminum, Al (CH ₃ ) ₃ ], which is an aluminum source, is flowed for 0.1 seconds to 5 seconds and adsorbed onto the surface of the silicon nitride film 27. The N ₂ gas is flowed for 0.1 seconds to 5 seconds to remove unreacted TMAs other than the TMAs forming. Next, O ₃ gas, which is a reaction gas, is flowed for 0.1 seconds to 5 seconds to induce a reaction with the adsorbed TMA so that an Al ₂ O ₃ atomic layer is formed on the silicon nitride film surface. Next, N ₂ gas is flowed for 0.1 second to 5 seconds to remove unreacted O ₃ gas and reaction byproducts. As described above, the TMA source supply, purge, O ₃ gas supply, and purge may be repeatedly performed to deposit Al ₂ O ₃ having a desired thickness.

After deposition of the dielectric film 28, heat treatment is performed using a rapid thermal process (RTP) or a furnace in an N ₂ atmosphere to improve film quality by removing impurities in the film. At this time, the RTP heat treatment is performed for 10 minutes to 60 minutes at a temperature of 500 ° C to 750 ° C and a pressure of 50torr to 760torr, and the furnace heat treatment is 10 to 30 seconds at a temperature of 500 ° C to 800 ° C and a pressure of 50torr to 760torr. To be carried out.

Next, the plate 29 forms a doped polysilicon having a thickness of 1500 GPa to 3000 GPa to form a silicon insulator silicon (SIS) capacitor, or a laminated film of TiN (200 GPa to 500 GPa) and doped polysilicon (1500 GPa to 3000 GPa). It may be formed to form a metal insulator silicon (MIS) capacitor.

In the above-described embodiment, the capacitor of the concave type has been described, but the present invention is also applicable to the manufacture of the capacitor of the cylinder type.

For example, after the completion of the PH ₃ doping process using plasma doping, the storage node oxide layer 25 is wet-removed using HF or BOE solution, followed by the PH ₃ doping process and in situ nitriding process using furnace doping. Proceed. In a subsequent process, dielectric film 28 and plate 29 are formed.

3 is a result of observing the concentration profile of phosphorus in the storage node. For example, 100 Å of the doped amorphous silicon film forming the backbone of the storage node, 300 Å of the undoped amorphous silicon film forming the MPS grain, and 40 Å of Al ₂ O ₃ as the dielectric film contacting the MPS grain are formed. . Curve C1 is the result of annealing the furnace at 725 ° C./20 torr / NH ₃ 500 sccm / 1 hour in an NH ₃ atmosphere after furnace doping at 700 ° C./5 torr / PH ₃ 300 sccm / N ₂ 400 sccm / 2 hours. Is the result of furnace doping at 700 ℃ / 5torr / PH ₃ 100sccm / N ₂ 400sccm / 2 hours, curve C3 is the result of plasma doping at 300W / PH ₃ 300sccm / 1torr / 70 seconds and curve C4 is 450W / the results of PH ₃ 450sccm / 2torr / 70 sec conditions with the plasma doping.

As shown in FIG. 3, the curves C1 and C2 using the furnace doping method maintain the highest phosphorus concentration at the storage node and the dielectric layer interface, and show that the phosphorus doping concentration is remarkably decreased as they enter the storage node.

On the other hand, the plasma doping curves C3 and C4 showed higher total doping concentration levels in the storage node by 5E20 / cm ^{3 to} 6E20 / cm ³ than the furnace doping method.

However, the peak concentration of the doped phosphorus was 4.2E21 / cm ^{3 to} 4.3E21 / cm ³ , the same level as that of the furnace doping method, and the peak concentration was present at 80 Å to 120 Å within the storage node.

If the peak concentration is present inside the storage node and the phosphorus concentration at the interface with the dielectric film is lowered, it causes a problem of increasing the depletion of the capacitor.

Therefore, in the present invention, by mixing the plasma doping method and the furnace doping method, the MPS grains on the surface of the storage node 26c in contact with the dielectric film are increased while increasing the total phosphorus concentration of the storage node 26c in which the MPS grains are grown. A uniform phosphorus concentration of 26d) can be maintained at 1E21 / cm ³ or higher. As a result, the contact resistance between the storage node 26c and the contact plug 23 in which the MPS grains 26d are grown may be secured while sufficiently securing the conductivity of the entire area of the storage node 26c.

In addition, as a result of evaluating the electrical characteristics of the 95nm device by applying the present invention, the capacitance was increased by more than 3fF / cell, the capacitance is increased to 3fF / cell in terms of effective oxide film thickness (Tox) is 4Å It is the same effect as reducing it.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can obtain the effect of improving the capacitance through the reduction of the capacitance change and the effect of improving the overall capacitance due to reduction of oxidation of the storage node and maximization of doping of phosphorus.

Claims (5)

Forming a storage node having MPS grain grown on a surface thereof; Doping phosphorus to the storage node using a plasma doping method; Further doping phosphorus by using a furnace doping method and then nitriding in situ to form a nitride film on the surface of the storage node; Forming a dielectric film on the nitride film; And Forming an upper electrode on the dielectric layer Method of manufacturing a capacitor comprising a. The method of claim 1, Doping the phosphorus using the plasma doping method, A method for producing a capacitor, characterized by applying plasma power of 300W to 450W under a pressure of 1torr to 2torr and proceeding for 70 seconds to 140 seconds while flowing PH ₃ gas at a flow rate of 300sccm to 450sccm. The method of claim 1, Further doping the phosphorus using the furnace doping method, A process for producing a capacitor, characterized in that it proceeds for 1 hour to 2 hours while flowing PH ₃ gas at a flow rate of 100 sccm to 200 sccm under a process temperature of 600 ° C. to 700 ° C. and a pressure of ₅ tor to 20 tor. The method of claim 1, The nitriding treatment, Manufacture of a capacitor, characterized in that for 30 minutes to 120 minutes while flowing the NH ₃ gas at a flow rate of 1000sccm to 5000sccm at a temperature of 650 ℃ to 800 ℃ and a pressure of 5torr to 30torr in the furnace where the furnace doping method Way. The method of claim 4, wherein A method for producing a capacitor, wherein a silicon nitride film is formed to have a thickness of 5 to 15 Å by the nitriding treatment.

Images