KR20050002056A - Method for fabricating capacitor of semiconductor device improved mps doping efficiency - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to improve doping efficiency of a bottom electrode in growing of MPS(Meta-stable Poly Silicon) grains by using a plasma doping and a furnace doing. CONSTITUTION: A lower electrode(29) is formed on a semiconductor substrate(21). MPS grains are grown on the bottom electrode. Phosphorous is doped into the resultant structure in order to obtain uniform doping concentration by using a plasma doping and a furnace doping. A dielectric film is then formed on the phosphorous-doped bottom electrode. An upper electrode is formed on the dielectric film.

Description

METHODS FOR FABRICATING CAPACITOR OF SEMICONDUCTOR DEVICE IMPROVED MPS DOPING EFFICIENCY}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a capacitor.

As the minimum line width of semiconductor devices decreases and the degree of integration increases, the area in which capacitors are formed is gradually narrowing. Even if the area where the capacitor is formed is narrowed, the capacitor in the cell must secure a capacitance of at least about 25 fF required per cell. In order to form a capacitor having a high capacitance on such a small area, a high dielectric constant such as Ta ₂ O ₅ , Al ₂ O _3, or HfO ₂ is substituted for the silicon oxide film (ε = 3.8) and the nitride film (ε = 7). It is possible to increase the effective surface area of a storage node by using a material having a dielectric film as a dielectric film, or dimensionalizing the storage node into a cylinder type or a concave type, or by growing a meta stable-poly silicon (MPS) on the storage node surface. The method of increasing by about 2 times etc. was proposed.

Recently, a technique for a capacitor which has grown the MPS on the surface of a dual storage node to increase the effective surface area of the storage node has been mainly studied. In the manufacturing method of the MPS capacitor, after forming a storage node made of an amorphous silicon film, a silane (Silane, SiH ₄ ) -based gas is injected into the seed gas and silicon atoms are migrated around the seed in a vacuum state. A method of growing MPS is known. At this time, the injection time, flow rate and temperature of the seed gas, the time, temperature and pressure of moving the silicon atoms, as well as the moving speed and amount of the silicon atoms vary according to the doping concentration of the impurities, resulting in a different size and amount of the MPS grown. You lose.

Currently, an inner capacitor structure in which MPS technology is applied only to the inner wall of the capacitor structure is applied to the extent that the cells can be separated from each other.

The structure of the MPS capacitor formed according to this conventional method is shown in FIG.

1 is a view showing the structure of an MPS capacitor formed according to the prior art.

As shown in FIG. 1, in the conventional MPS capacitor, an interlayer insulating film 12 is formed on the semiconductor substrate 11, and the semiconductor substrate 11 is provided in a contact hole (not shown) provided by etching the interlayer insulating film 12. The contact plug 13 connected with) is buried.

In addition, a stacked layer of an etch barrier layer 14 and a storage node oxide layer 15 is formed on the interlayer insulating layer 12 and has a groove for opening the contact plug 13, and the lower electrode 16 having a cylindrical shape is formed in the groove. ) Is formed. Here, MPS grain 17 is grown on the surface of the lower electrode 16.

The dielectric layer 18 is formed on the lower electrode 16 and the storage node oxide layer 15, and the upper electrode 19 is formed on the dielectric layer 18 to fill the inside of the cylinder in which the lower electrode 16 is formed. .

In FIG. 1, doped silicon and undoped silicon doped with phosphorus (P) are heavily doped to form a lower electrode 16 on which MPS grain 17 is grown. After depositing a double layer of undoped silicon in-situ, a cylindrical shape is formed by chemical mechanical polishing or etch back, and the undoped silicon film is grown to MPS grains (17) by the MPS process. It is formed to maintain the cylinder skeleton of the lower electrode 16.

Recently, as the design rule becomes smaller, it is necessary to optimize the size of the MPS grain 17 and to optimize the guidance of the grown MPS grain 17 to secure the capacitance in the same capacitor structure.

Moreover, in order for the MPS grain 17 to function as a lower electrode, depletion inevitably generated during operation of the device should be minimized. To this end, the MPS grain 17 directly contacting the capacitor dielectric material at a sufficient concentration is introduced. You must ping it.

As such, the plasma PH ₃ doping method and the furnace PH ₃ doping method have been proposed as conventional techniques for phosphorus doping the MPS grains 17 to a sufficient concentration.

FIG. 2 is a diagram illustrating a comparison of phosphorus concentrations according to a conventional furnace doping condition, in which a 400 PH thick undoped silicon film was PH ₃ doped using a furnace doping method. 1, curve C1 is the result of furnace PH ₃ doping at 600 ° C. for 2 hours, curve C2 is the result of furnace PH ₃ doping at 700 ° C. for 2 hours, and curve C3 is the result of eliminating furnace PH ₃ doping. .

Referring to FIG. 2, the curve C1 (600 ° C., 2 hours, furnace PH ₃ doping) shows that the phosphorus concentration was maintained at a level of 5 × 10 ^{20 on the} surface of the undoped silicon film, and the phosphorus concentration was exceeded from 100 μs on the surface. It can be seen that the decrease rapidly. That is, the entire 400 Å thick undoped silicon film is not sufficiently doped.

In the case of curve C2 (700 ° C., 2 hours, furnace PH ₃ doping), the phosphorus concentration was maintained at 5 × 10 ^{19 on the} surface of the undoped silicon film, but the phosphorus concentration suddenly exceeded 100 kPa on the surface. It can be seen that the decrease. That is, it can be seen that the doping ability is lower than that of the curve C1.

Comparing curves C1 and C2, both results show that the 400 Å thick undoped silicon film is not sufficiently doped, and that the phosphorus concentration on the surface of the undoped silicon film is further decreased when the temperature rises. have.

In general, the phosphorus concentration on the surface of the undoped silicon film is determined by the extent to which PH ₃ entering the doping gas reacts with the surface of the undoped silicon film. That is, the phosphorus concentration on the surface of the undoped silicon film is purely determined by the difference between the amount of PH ₃ in the gaseous state attached to the silicon surface and the amount of phosphorus already attached to the surface desorbed from the silicon surface and escaped into the gaseous state. It is determined by the amount present in the. In the curve C2 having a doping temperature of 700 ° C., the amount of desorption from the surface is greater than that of the curve C1 having a doping temperature of 600 ° C. rather than the amount attached to the surface.

As described above, in the prior art, the method of increasing the amount of phosphorus introduced into the MPS grain surface in the gas state to increase the doping efficiency, that is, to enhance the doping efficiency by strengthening the external PH ₃ doping conditions (flow, pressure, temperature) However, according to the result of FIG. 1, the effect of increasing the doping efficiency does not reach the entire region of the lower electrode.

The present invention has been made to solve the above problems of the prior art, it is an object of the present invention to provide a method for manufacturing a capacitor that can maximize the doping efficiency of subsequent phosphorous (P) doping to extend to the entire region of the lower electrode when applying the MPS process There is this.

1 is a view showing the structure of an MPS capacitor formed according to the prior art,

2 is a view comparing the phosphorus concentration according to the conventional furnace doping conditions,

3A to 3F are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention;

4 is a view showing the structure of a capacitor according to another embodiment of the present invention;

5 is a result of observing the phosphorus concentration profile according to the lower electrode depth.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 interlayer insulating film

23: contact plug 24: etching barrier film

25: storage node oxide film 27a: cylinder

28a: MPS grain 29: lower electrode

30 dielectric layer 31 upper electrode

The method of manufacturing the capacitor of the present invention for achieving the above object is a step of forming a lower electrode on which MPS grain is grown on the surface, the plasma doping method and the furnace to have a uniform doping concentration over the entire surface of the lower electrode and the inside Doping the phosphorus by mixing a doping method, forming a dielectric film on the lower electrode doped with the phosphorus, and forming an upper electrode on the dielectric film. The plasma doping method may be performed after the plasma doping method is performed, or after the plasma doping method is performed, the plasma doping method may be performed. The plasma power of 300W-450W is applied under process temperature and the pressure of 1torr-2.5torr, and PH ₃ gas is flowed at a flow rate of 300sccm-450sccm. The furnace doping method is characterized in that it proceeds for 70 seconds to 140 seconds, and the furnace doping method is performed for 1 hour to a flow of PH ₃ gas at a flow rate of 100 sccm to 200 sccm under a process temperature of 600 ° C to 700 ° C and a pressure of 5torr to 20torr. Characterized in proceeding for 2 hours.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3A to 3F are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.

As shown in FIG. 3A, an interlayer insulating film 22 is formed on a semiconductor substrate 21 on which a lower structure such as a transistor is formed, and a contact hole for electrically connecting an impurity region of the semiconductor substrate 21 to a lower electrode. After forming, the conductive material is laminated thereon and planarized by chemical mechanical polishing or etch back to form the contact plug 23. Subsequently, an etch barrier film 24 is deposited on the entire surface, and the plasma enhanced tetra ethyl ortho silicate (PE-TEOS), boron phosphorus silicate glass (BPSG), phoshporus silicate glass (PSG), or USG is formed on the etching barrier film 24. A storage node oxide (25) such as (Undoped Silicate Glass) is deposited. At this time, the storage node oxide film 25 is formed to a thickness of 15000 kPa to 25000 kPa.

Next, the storage node oxide layer 25 and the etching barrier layer 24 are sequentially etched to form grooves 26 exposing the contact plugs 23 in the region where the lower electrode is to be formed. In this case, the etch barrier layer 24 is a film that stops etching when the groove 26 is formed, and is formed of the silicon nitride layer having a good etching selectivity with the storage node oxide layer 25. The etching barrier layer 24 serves to support the storage node having a high height from the side, thereby obtaining a lower electrode having better mechanical strength.

As shown in FIG. 3B, a doped silicon film 27 doped with impurities (phosphorus) and an undoped doped with no impurities are formed on the entire surface including the grooves 26 formed by etching the storage node oxide film 25. The de silicon film 28 is continuously formed in situ.

The reason why the doped silicon film 27 and the undoped silicon film 28 are formed in situ is that in the silicon film having a high doping concentration of impurities, almost no silicon atoms are moved, so that MPS grains do not grow and impurities are formed. In the undoped silicon film, the silicon atoms are rapidly moved to facilitate the growth of MPS grains. That is, the doped silicon film 27 doped with impurities becomes an outer wall forming the cylinder skeleton of the lower electrode, and the undoped silicon film 28 without dopants is formed of MPS grain formed on the inner wall of the cylinder shape. To grow.

During such in-situ deposition of the doped silicon film 27 and the undoped silicon 27, phosphorus (P) may be used as an impurity doped in the doped silicon film 27, and the doped silicon film 27 Phosphorus (P) can be doped at the same time as the deposition. At this time, the doping concentration of phosphorus (P) can be adjusted by controlling the flow rate of the impurity source gas containing phosphorus compared to the silicon source gas, the silicon source gas as monosilane (diosilane), disilane (disilane), trisilane (trisilane) Silane gas such as dichlorosilane, and the impurity source gas containing phosphorus use PH ₃ gas. The phosphorus (P) doping concentration of the doped silicon film 27 is set in consideration of the time to move the silicon atoms, the size of the MPS grain to be grown, and the like. The high doping concentration of about 1E20 to 3E21 / cm ³ using SIMS is used. To have.

On the other hand, the thickness of the doped silicon film 27 and the undoped silicon film 28 is determined according to the degree of integration of the desired device, the height and width of the lower electrode, etc. In the present invention, the total thickness is about 300 kPa to 300 kPa, respectively. It should be ~ 600Å. The doped silicon film 27 and the undoped silicon film 28 are deposited in an amorphous state, and the deposition temperature is maintained at 500 ° C. to 550 ° C. during in-situ deposition. This is because when the silicon film is deposited at a temperature of 550 ° C. or higher, it has a crystalline form, not amorphous. MPS grains cannot be grown in the crystalline silicon film.

Next, the doped silicon film 27 and the undoped silicon film 28 formed on the storage node oxide film 25 are removed by chemical mechanical polishing, etch back, or the like to help only the inner wall of the groove 26. The dope silicon film 27 and the undoped silicon film 28 remain in the form of a cylinder. Here, when removing the doped silicon film 27 and the undoped silicon film 28, impurities such as abrasives or etched particles may adhere to the inside of the cylinder. After filling the inside of the cylinder with the resist, it is preferable to perform polishing or etch back until the surface of the storage node oxide film 25 is exposed, and ashing and removing the photoresist inside the cylinder.

As shown in FIG. 3C, MPS grain 28a is grown on the inner wall of the cylinder 27a. The method of growing the MPS grain 28a is performed by forming a silicon seed on the surface of the undoped silicon film 28 using a silane-based gas, and then moving the silicon by annealing at a temperature of 600 ° C to 650 ° C. For example, an undoped silicon film 28 that is not doped with impurities grows into the MPS grain 28a, and a doped silicon film 27 in which movement of silicon atoms is suppressed forms a skeleton of the cylinder 27a. As a result, in the doped silicon film 27 having a high doping concentration of phosphorus (P), the movement of silicon atoms is suppressed, so that at least the skeleton of the cylinder 27a at least as thick as the doped silicon film 27 is maintained.

Hereinafter, the cylinder 27a and the MPS grain 28a will be collectively referred to as the lower electrode 29 for convenience.

As shown in FIG. 3D, the PH ₃ doping process is performed to secure the overall conductivity of the lower electrode 29, for example, the phosphorus (P) doping concentration. At this time, the PH ₃ doping process is not only for doping the phosphorus (P) to the MPS grain on the surface of the lower electrode 29, but also the phosphorus (doped during the deposition of the doped silicon film 27 forming the lower electrode 29) It is a process for increasing the doping concentration of P). First, in order to increase the doping efficiency of the PH ₃ doping process, the surface of the lower electrode 29 is cleaned by using HF chemicals or BOE chemicals, and then doped with phosphorus (P) on the MPS grains by performing PH ₃ doping. The doping concentration of phosphorus (P) in the lower electrode 29 which has already been formed is also increased. By using the PH ₃ gas as a reaction gas and diffusing into the lower electrode 29 by the diffusion process, the doping concentration of phosphorus (P) is uniformly distributed over the entire surface of the lower electrode 29 and the inside.

The present invention proceeds continuously by mixing the plasma doping method and the furnace doping method so that phosphorous doping can be uniformly spread over the entire area of the lower electrode 29.

In a first method, plasma doping is first performed, followed by furnace doping. For example, the plasma doping method, which proceeds first, is a method of generating a plasma of PH ₃ gas in the chamber to dope phosphorus. The process temperature is 700 ° C. to 800 ° C., and the process time is 70 seconds to 140 seconds. The pressure and the plasma power are in the range of 1 tor to 2.5 tor and 300 to 450 W, respectively. At this time, the flow rate of the PH ₃ gas is set to 300 sccm to 450 sccm. Next, the furnace doping method is carried out. The furnace doping method is a method of doping phosphorus using a PH ₃ gas in a furnace. The process temperature is 600 ° C to 700 ° C, and the process time is 1 hour to 2 hours. The process pressure and the flow rate of the PH ₃ gas are 5 tortorr and 20 torrr and 100 sccm to 200 sccm, respectively.

In a second method, the furnace doping method is first performed, followed by the plasma doping method. For example, in a furnace doping method furnace, the phosphorus is doped using a PH ₃ gas. The process temperature is 600 ° C to 700 ° C, the process time is 1 hour to 2 hours, and the process pressure and The flow rate of the PH ₃ gas is set at 5 tor to 20 tor and 100 to cm to 200 sccm, respectively. Next, a plasma doping method is performed, in which a plasma of PH ₃ gas is generated in the chamber to dope phosphorus, the process temperature is 700 ° C. to 800 ° C., the process time is 70 seconds to 140 seconds, and the process pressure. And plasma power are in the range of 1 tor to 2.5 tor and 300 to 450 W, respectively. At this time, the flow rate of the PH ₃ gas is set to 300 sccm to 450 sccm.

As illustrated in FIG. 3E, the storage node oxide layer 25 is dip-outed using the wet chemical of HF or BOE using the etch barrier layer 24 as an etch stop layer.

Next, the PH ₃ doping process is further performed after the wet deep out process. This additional PH ₃ doping process is to improve the doping efficiency of phosphorus (P) in the lower electrode 29 and to correct the doping profile of phosphorus (P). That is, since the phosphorus (P) on the surface of the lower electrode 29 is released during the wet deep out of the storage node oxide layer 25, depletion may occur due to insufficient doping concentration, and thus, the lower electrode may be further subjected to a PH ₃ doping process. Phosphorus is added to (29).

In detail, the storage node oxide layer 25 is further subjected to a PH ₃ doping process in addition to the lower electrode 29 exposed to the inner wall and the outer wall through a wet deep out.

Further PH ₃ doping processes use plasma doping or furnace doping.

First, the plasma doping method flows PH ₃ gas at a flow rate of 300 sccm to 500 sccm under a process temperature of 700 ° C. to 800 ° C., a process time of 1 minute to 3 minutes, a process pressure of 1 tor to 2 tor, and a plasma power of 100 W to 300 W. Proceed by giving.

In the furnace doping method, the process temperature is 600 ° C. to 700 ° C., the process time is 1 hour to 2 hours, and the process pressure and the flow rate of the PH ₃ gas are 5 tor to 10 tor and 100 sccm to 200 sccm, respectively.

Next, as shown in FIG. 3F, the dielectric film 30 and the upper electrode 31 are formed to complete the capacitor of the cylinder structure. Herein, the dielectric film 30 uses oxidized Si ₃ N ₄ , Ta ₂ O ₅ , Al ₂ O ₃ , HfO ₂ , and the upper electrode 31 is a doped polysilicon film or a doped polysilicon film and titanium. A double film of nitride film TiN is used.

As described above, the present invention mixes the plasma doping method and the furnace doping method in order to sufficiently secure the doping concentration of the lower electrode and the MPS grain.

Plasma doping is a physical doping of phosphorus (P) on the surface of the lower electrode 29. If only the plasma doping is performed, the doping concentration of the surface where the MPS grain is grown can be satisfied, but the contact plug 23 and It is not enough to meet the doping concentration of the contacting part. Therefore, the furnace doping method is further proceeded after the plasma doping of the present invention.

In addition, the furnace doping method chemically dope phosphorus on the surface of the lower electrode 29. When only the furnace doping method is performed, the doping concentration of the portion contacting the contact plug 23 may be satisfied, but the lower electrode 29 When the phosphorus (P) of the surface is excessively diffused, there was a disadvantage that the required surface concentration could not be obtained. Therefore, in the present invention, the plasma doping method is further performed before or after the furnace doping method.

4 is a view showing the structure of a capacitor according to another embodiment of the present invention, a capacitor having a concave structure.

As shown in FIG. 4, the dielectric layer 30 and the upper electrode 31 are formed directly on the resultant in which the PH ₃ doping of FIG. 3D is completed without wet-drying the storage node oxide layer 25 to form a capacitor having a concave structure. Will be completed.

In the case of FIG. 4, an additional PH ₃ doping process such as FIG. 3E is omitted.

5 is a result of observing the phosphorus concentration profile according to the depth of the lower electrode. For example, 100 결과 of the doped silicon film forming the skeleton of the lower electrode, 300 Å of the undoped silicon film forming the MPS grain, and Al ₂ O ₃ as the dielectric film contacting the MPS grain have a thickness of 40 Å. Curve C4 is the result of annealing the furnace at 725 ° C./20 torr / NH ₃ 500 sccm / 1 hour in an NH ₃ atmosphere after furnace doping under 700 ° C./5 torr / PH ₃ 300 sccm / N ₂ 400 sccm / 2 hours. Is the result of furnace doping at 700 ℃ / 5torr / PH ₃ 100sccm / N ₂ 400sccm / 2 hours, curve C6 is the result of plasma doping at 300W / PH ₃ 300sccm / 1torr / 70 seconds and curve C7 is 450W / the results of PH ₃ 450sccm / 2torr / 70 sec conditions with the plasma doping.

As shown in FIG. 5, curves 4 and 5 using the furnace doping method maintain the highest phosphorus concentration at the interface between the lower electrode and the dielectric layer, and show a characteristic that the indoping concentration is significantly lowered as it enters the lower electrode.

On the other hand, curve 6 and curve 7 using plasma doping method showed that the total indoping concentration level in the lower electrode was about 5E20 / cm ^{3 to} 6E20 / cm ³ higher than that of furnace doping method.

However, the peak concentration of the doped phosphorus was 4.2E21 / cm ^{3 to} 4.3E21 / cm ³ , the same level as the furnace doping method, and the peak concentration was present at a point of 80 kV to 120 kV inside the lower electrode.

If the peak concentration is present inside the lower electrode and the phosphorus concentration at the interface with the dielectric film is lowered, a problem of increasing the depletion of the capacitor occurs.

Accordingly, in the present invention, the plasma doping method and the furnace doping method are mixed and continuously performed, thereby increasing the total phosphorus concentration of the lower electrode 29 on which the MPS grain is grown, and simultaneously controlling the MPS grain on the surface of the lower electrode 29 in contact with the dielectric film. The uniform phosphorus concentration can be kept high above 1E21 / cm ³ . As a result, the conductive resistance of the entire region of the lower electrode 29 may be sufficiently secured while securing the contact resistance between the lower electrode 29 and the contact plug 23 on which the MPS grain is grown.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, when the MPS grain is grown on the inner wall of the lower electrode of the capacitor structure, there is an effect of improving the guided efficiency of the lower electrode.

In addition, since the lower electrode can be sufficiently guided, the depletion of the capacitor can be reduced to realize an additional increase effect of the capacitance.

In addition, there is an effect that can improve the uniformity of the phosphorus concentration into the lower electrode at the interface between the lower electrode and the dielectric film.

Claims (6)

Forming a bottom electrode having MPS grain grown on a surface thereof; And Doping the phosphorus by mixing the plasma doping method and the furnace doping method so as to have a uniform doping concentration over the entire surface of the lower electrode and the inside of the lower electrode; Forming a dielectric layer on the phosphorus-doped lower electrode; And Forming an upper electrode on the dielectric layer Method of manufacturing a capacitor comprising a. The method of claim 1, Doping the phosphorus, And the furnace doping method after the plasma doping process. The method of claim 1, Doping the phosphorus, The process of manufacturing the capacitor, characterized in that the plasma doping method proceeds first after the furnace doping method. The method according to claim 2 or 3, The plasma doping method, A plasma power of 300 W to 450 W is applied at a process temperature of 700 ° C. to 800 ° C. and a pressure of 1 tor to 2.5 tor, and flows for 70 seconds to 140 seconds while flowing PH ₃ gas at a flow rate of 300 sccm to 450 sccm. Method of manufacturing a capacitor. The method according to claim 2 or 3, The furnace doping method, A process for producing a capacitor, characterized in that it proceeds for 1 hour to 2 hours while flowing PH ₃ gas at a flow rate of 100 sccm to 200 sccm under a process temperature of 600 ° C. to 700 ° C. and a pressure of ₅ tor to 20 tor. The method of claim 1, Forming the lower electrode, Forming an insulating film having a groove on which a lower electrode is to be formed; Depositing an in-doped undoped silicon film and an undoped undoped silicon film on the insulating film including the groove in situ; Patterning the doped silicon film and the undoped silicon film in the form of a cylinder and remaining in the groove; And Performing an MPS process to allow the doped silicon film to form a skeleton of the lower electrode and to grow the undoped silicon film to the MPS grain