KR101046757B1 - Capacitor of semiconductor device and manufacturing method thereof - Google Patents

Capacitor of semiconductor device and manufacturing method thereof Download PDF

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KR101046757B1
KR101046757B1 KR1020040060548A KR20040060548A KR101046757B1 KR 101046757 B1 KR101046757 B1 KR 101046757B1 KR 1020040060548 A KR1020040060548 A KR 1020040060548A KR 20040060548 A KR20040060548 A KR 20040060548A KR 101046757 B1 KR101046757 B1 KR 101046757B1
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film
buffer layer
capacitor
lower electrode
growth buffer
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KR20060011622A (en
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홍권
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2

Abstract

본 발명은 HfO2 공정시 하부전극 표면이 산화되는 것을 방지하면서 고품질의 HfO2를 얻을 수 있는 반도체소자의 캐패시터 및 그 제조 방법을 제공하기 위한 것으로, 본 발명의 캐패시터의 제조 방법은 하부전극을 형성하는 단계, 상기 하부전극 상에 산화저항막(RTN을 이용한 실리콘질화막)을 형성하는 단계, 상기 산화저항막 상에 하프늄옥사이드의 균일한 성장을 위한 성장 버퍼층(ALD를 이용한 SiO2)을 형성하는 단계, 상기 성장 버퍼층 상에 하프늄옥사이드를 형성하는 단계, 및 상기 하프늄옥사이드 상에 상부전극을 형성하는 단계를 포함한다.
The present invention is to provide a capacitor and a method for manufacturing the semiconductor device capable of obtaining high quality HfO 2 while preventing the surface of the lower electrode is oxidized during the HfO 2 process, the method of manufacturing the capacitor of the present invention to form a lower electrode Forming an oxide resistance film (a silicon nitride film using RTN) on the lower electrode, and forming a growth buffer layer (SiO 2 using ALD) for uniform growth of hafnium oxide on the oxide film. Forming a hafnium oxide on the growth buffer layer, and forming an upper electrode on the hafnium oxide.

캐패시터, 산화저항막, 급속열질화, RTN, 성장버퍼층, 하프늄옥사이드Capacitor, Oxidation Resistance Film, Rapid Thermal Nitridation, RTN, Growth Buffer Layer, Hafnium Oxide

Description

반도체소자의 캐패시터 및 그 제조 방법{CAPACITOR IN SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME} Capacitor of semiconductor device and manufacturing method therefor {CAPACITOR IN SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME}             

도 1은 종래기술에 따른 SIS 캐패시터의 구조를 도시한 도면,1 is a view showing the structure of a SIS capacitor according to the prior art,

도 2는 본 발명의 실시예에 따른 SIS 캐패시터의 구조를 도시한 도면,2 illustrates a structure of a SIS capacitor according to an embodiment of the present invention;

도 3a 내지 도 3d는 도 2에 도시된 캐패시터의 제조 방법을 도시한 공정 단면도.
3A to 3D are cross-sectional views illustrating a method of manufacturing the capacitor shown in FIG. 2.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 하부전극 22 : 산화저항막21: lower electrode 22: oxidation resistance film

23 : 성장버퍼층 24 : HfO2 23: growth buffer layer 24: HfO 2

25 : 상부전극
25: upper electrode

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체소자의 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a method of manufacturing capacitors in semiconductor devices.

최근 미세화된 반도체 공정 기술의 발달로 메모리 제품의 고집적화가 가속화됨에 따라 단위 셀면적이 크게 감소하고 있으며, 동작전압의 저전압화가 이루어지고 있다. 그러나, 기억소자의 동작에 필요한 충전용량은 셀면적 감소에도 불구하고, 소프트 에러(soft error)의 발생과 리프레쉬 시간(refresh time)의 단축을 방지하기 위해서 25fF/cell 이상의 충분한 용량이 지속적으로 요구되고 있다. 따라서, 현재 DCS(Di-Chloro-Silane) 가스를 사용하여 증착한 실리콘질화막(Si3N4)을 유전체로 사용하고 있는 DRAM용 NO(Nitride/Oxide) 캐패시터 소자의 경우 표면적이 큰 반구형 구조의 전극 표면을 갖는 3차원 형태의 전하저장전극을 사용하고 있음에도 불구하고, 그 높이가 계속적으로 증가하고 있다.Recently, as the integration of memory products is accelerated due to the development of miniaturized semiconductor processing technology, the unit cell area is greatly reduced, and the operating voltage is being lowered. However, the charging capacity required for the operation of the memory device, despite the reduction in cell area, sufficient capacity of 25 fF / cell or more is continuously required to prevent the occurrence of soft errors and shortening of the refresh time. have. Therefore, in the case of a DRAM (Nitride / Oxide) capacitor device for DRAM that uses a silicon nitride film (Si 3 N 4 ) deposited using a Di-Chloro-Silane (DCS) gas as a dielectric, the electrode has a hemispherical structure with a large surface area. Despite the use of a three-dimensional surface charge storage electrode, its height continues to increase.

한편, NO 캐패시터가 256M 이상의 차세대 DRAM 제품에 필요한 충전용량을 확보하는데 그 한계를 보이고 있기 때문에 Ta2O5, Al2O3, HfO 2 등의 고유전상수를 갖는 유전막을 채용한 캐패시터 소자의 개발이 본격적으로 진행되고 있다.On the other hand, since NO capacitors have shown a limit in securing the necessary charging capacity for next-generation DRAM products of 256M or more, the development of a capacitor device employing a dielectric film having a high dielectric constant such as Ta 2 O 5 , Al 2 O 3 , HfO 2, etc. It is progressing in earnest.

그러나, 등가산화막두께(Tox.eq) 관점에서 보면, 유전상수가 낮은 실리콘질화막을 채용한 캐패시터는 더이상 등가산화막두께를 40Å 이하로 낮출 수가 없으며, Ta2O5를 채용한 캐패시터는 제조 특성상 하부전극의 산화가 심하게 발생하여 저유전산화막이 비교적 두껍게 형성되기 때문에 사실상 등가산화막두께를 30Å 이하로 낮출 수가 없고, 또한 상부전극 형성후 고온 열공정에 의한 유전막의 열화로 누 설전류가 발생하는 문제점을 갖고 있다. However, from the point of equivalent oxide film thickness (Tox.eq), a capacitor employing a silicon nitride film having a low dielectric constant can no longer lower the equivalent oxide film thickness to 40 kW or less, and a capacitor employing Ta 2 O 5 has a lower electrode in view of manufacturing characteristics. Since the low dielectric oxide film is formed relatively thick due to severe oxidation, the equivalent oxide film thickness cannot be lowered to 30 kV or less, and leakage current is generated due to deterioration of the dielectric film by high temperature thermal process after forming the upper electrode. have.

이러한 유전성의 한계를 극복하기 위해 HfO2, Al2O3를 채용한 캐패시터가 제안되었다. 그러나, Al2O3(ε=8)는 유전상수가 아주 크지 않기 때문에 충전용량 확보에 제약이 있다. 한편, HfO2는 유전상수가 20∼25 정도로 매우 커서 충전용량 확보가 유리하다.In order to overcome these limitations, a capacitor employing HfO 2 and Al 2 O 3 has been proposed. However, Al 2 O 3 (ε = 8) has a limitation in securing the charging capacity because the dielectric constant is not very large. On the other hand, HfO 2 has a dielectric constant of about 20 to 25, so it is advantageous to secure a charging capacity.

도 1은 종래기술에 따른 SIS(Silicon Insulator Silicon) 캐패시터의 구조를 도시한 도면이다.1 is a view showing the structure of a silicon insulator silicon (SIS) capacitor according to the prior art.

도 1을 참조하면, 종래 SIS 캐패시터는, 폴리실리콘막으로 형성된 하부전극(11), 하부전극(11) 상에 형성된 HfO2(12), HfO2(12) 상에 형성된 폴리실리콘막으로 형성된 상부전극(13)을 포함한다.Referring to FIG. 1, a conventional SIS capacitor includes a lower electrode 11 formed of a polysilicon film, an HfO 2 12 formed on the lower electrode 11, and an upper part formed of a polysilicon film formed on the HfO 2 12. Electrode 13.

위와 같은 종래기술은 HfO2(12)의 증착 및 후속 열처리 공정에 의해 하부전극(11) 표면이 산화되는 것을 방지하고자 HfO2(12) 형성전에 급속열질화(Rapid Thermal Nitridation; RTN) 공정을 진행하여 하부전극(11)과 HfO2(12)의 계면에 산화저항막 역할을 하는 실리콘질화막(Silicon nitride, 14)을 형성하고 있다.The prior art as described above proceeds with a Rapid Thermal Nitridation (RTN) process before the formation of HfO 2 12 to prevent the surface of the lower electrode 11 from being oxidized by the deposition of HfO 2 12 and subsequent heat treatment. As a result, a silicon nitride film 14 is formed at the interface between the lower electrode 11 and the HfO 2 12.

그러나, 종래기술은 급속열질화를 통해 형성한 실리콘질화막(14) 위에 HfO2(12)를 형성하므로, HfO2(12)의 막 품질(Layer quality)이 매우 불량하다. 즉,실리콘질화막(14) 위에서 HfO2(12)을 균일하게 성장시키기가 매우 어렵고, 또한 후 속 열처리 공정을 거치는동안 보이드(void)가 발생하는 등 열적으로도 매우 불안정해진다.However, in the prior art, since HfO 2 12 is formed on the silicon nitride film 14 formed through rapid thermal nitriding, the layer quality of HfO 2 12 is very poor. That is, it is very difficult to uniformly grow HfO 2 12 on the silicon nitride film 14, and also becomes thermally unstable, such as voids, during the subsequent heat treatment process.

통상적으로, HfO2는 실리콘산화막(SiO2)과 같은 산화막 또는 폴리실리콘막 위에서는 성장이 잘 이루어져 균일한 막 품질을 보이나, 실리콘질화막과 같은 질화막 위에서는 성장이 잘 이루어지지 않아 막 품질이 매우 불량한 것으로 알려져 있다.
In general, HfO 2 grows well on an oxide film or a polysilicon film such as silicon oxide film (SiO 2 ) and shows uniform film quality, but does not grow well on a nitride film such as silicon nitride film and thus has very poor film quality. It is known.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로, HfO2 공정시 하부전극 표면이 산화되는 것을 방지하면서 고품질의 HfO2를 얻을 수 있는 반도체소자의 캐패시터 및 그 제조 방법을 제공하는데 그 목적이 있다.
The present invention has been proposed to solve the above problems of the prior art, and provides a capacitor and a method of manufacturing the semiconductor device capable of obtaining high quality HfO 2 while preventing the lower electrode surface from being oxidized during the HfO 2 process. There is a purpose.

상기 목적을 달성하기 위한 본 발명의 캐패시터는 하부전극, 상기 하부전극 상의 산화저항막, 상기 산화저항막 상의 성장버퍼층, 상기 성장버퍼층 상의 하프늄옥사이드, 및 상기 하프늄옥사이드 상의 상부전극을 포함하는 것을 특징으로 하고, 상기 산화저항막은 상기 하프늄옥사이드 형성시 상기 하부전극의 산화를 방지하는 물질을 포함하고, 상기 성장버퍼층은 상기 하프늄옥사이드의 성장을 균일하게 하는 물질을 포함하며, 상기 산화저항막은 실리콘질화막이고, 상기 성장버퍼층은 실리콘산화막인 것을 특징으로 한다.The capacitor of the present invention for achieving the above object is characterized in that it comprises a lower electrode, an oxide resistive film on the lower electrode, a growth buffer layer on the oxidation resistive film, hafnium oxide on the growth buffer layer, and an upper electrode on the hafnium oxide The oxidation resistance film includes a material for preventing oxidation of the lower electrode when the hafnium oxide is formed, the growth buffer layer includes a material for uniformly growing the hafnium oxide, and the oxidation resistance film is a silicon nitride film. The growth buffer layer is characterized in that the silicon oxide film.

그리고, 본 발명의 캐패시터의 제조 방법은 하부전극을 형성하는 단계, 상기 하부전극 상에 산화저항막을 형성하는 단계, 상기 산화저항막 상에 성장 버퍼층을 형성하는 단계, 상기 성장 버퍼층 상에 하프늄옥사이드를 형성하는 단계, 및 상기 하프늄옥사이드 상에 상부전극을 형성하는 단계를 포함하고, 상기 산화저항막은 상기 하프늄옥사이드 형성시 상기 하부전극의 산화를 방지하는 물질을 포함하고, 상기 성장버퍼층은 상기 하프늄옥사이드의 성장을 균일하게 하는 물질을 포함하며, 상기 성장 버퍼층은 실리콘산화막으로 형성하는 것을 특징으로 하며, 상기 산화저항막은 급속열질화를 이용한 실리콘질화막으로 형성하는 것을 특징으로 한다.In addition, the method of manufacturing the capacitor of the present invention includes the steps of forming a lower electrode, forming an oxide resistance film on the lower electrode, forming a growth buffer layer on the oxidation resistance film, and forming hafnium oxide on the growth buffer layer. And forming an upper electrode on the hafnium oxide, wherein the oxidation resistance film includes a material for preventing oxidation of the lower electrode when the hafnium oxide is formed, and the growth buffer layer is formed of the hafnium oxide. The growth buffer layer may be formed of a silicon oxide film, and the oxidation resistance layer may be formed of a silicon nitride film using rapid thermal nitriding.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2는 본 발명의 실시예에 따른 SIS 캐패시터의 구조를 도시한 도면이다.2 is a diagram illustrating a structure of a SIS capacitor according to an embodiment of the present invention.

도 2에 도시된 바와 같이, 하부전극(21), 하부전극(21) 상에 형성된 산화저항막(22), 산화저항막(22) 상에 형성된 성장 버퍼층(Buffer for growing HfO2, 23), 성장버퍼층(23) 상의 하프늄옥사이드(HfO2, 24), 하프늄옥사이드(24) 상의 상부전극(25)을 포함한다. 이하, 하프늄옥사이드(24)를 HfO2(24)라 약칭한다.As shown in FIG. 2, the lower electrode 21, the oxidation resistive film 22 formed on the lower electrode 21, the growth buffer layer Buffer for growing HfO 2 , 23, Hafnium oxide (HfO 2 , 24) on the growth buffer layer 23, and an upper electrode 25 on the hafnium oxide 24 are included. Hereinafter, hafnium oxide 24 is abbreviated as HfO 2 (24).

도 2에서, 하부전극(21)과 상부전극(25)은 불순물이 도핑된 폴리실리콘막이다. 이때, 폴리실리콘막은 인(Phosphorous)이 도핑되어 있다.In FIG. 2, the lower electrode 21 and the upper electrode 25 are polysilicon films doped with impurities. At this time, the polysilicon film is doped with phosphorous (Phosphorous).

그리고, 산화저항막(22)은 HfO2(24) 공정시 하부전극(21) 표면이 산화되는 것을 방지하기 위한 것으로 급속열질화(RTN) 공정을 통해 형성한 실리콘질화막(SiN)이다. The oxidation resistance film 22 is a silicon nitride film (SiN) formed through a rapid thermal nitriding (RTN) process to prevent the surface of the lower electrode 21 from being oxidized during the HfO 2 24 process.

그리고, 성장버퍼층(23)은 HfO2(24)의 막품질을 균일하게 하기 위해 도입된 버퍼층으로 실리콘산화막(SiO2)이다. 여기서, 성장버퍼층(23)으로 사용된 실리콘산화막은 원자층증착(Atomic Layer Deposition; ALD) 방식으로 형성하고, 그 두께는 3Å∼10Å 정도로 매우 얇다.The growth buffer layer 23 is a silicon oxide film (SiO 2 ) as a buffer layer introduced to make the film quality of HfO 2 24 uniform. Here, the silicon oxide film used as the growth buffer layer 23 is formed by Atomic Layer Deposition (ALD), and the thickness thereof is very thin, about 3 GPa to 10 GPa.

도 3a 내지 도 3d는 도 2에 도시된 캐패시터의 제조 방법을 도시한 공정 단면도이다.3A to 3D are cross-sectional views illustrating a method of manufacturing the capacitor shown in FIG. 2.

도 3a에 도시된 바와 같이, 폴리실리콘막을 이용하여 하부전극(21)을 형성한다. 이때, 하부전극(21)으로 폴리실리콘막 증착시 인(P) 또는 비소(As)와 같은 불순물을 도핑시켜 하부전극(21)이 전기전도성을 갖도록 한다. 한편, 하부전극(21)인 폴리실리콘막 증착 공정은 스퍼터링법(sputtering), 화학기상증착법(Chemical Vapor Deposition; CVD) 또는 원자층증착법(Atomic Layer Deosition; ALD)을 이용한다. As shown in FIG. 3A, the lower electrode 21 is formed using a polysilicon film. At this time, the lower electrode 21 is doped with impurities such as phosphorus (P) or arsenic (As) when the polysilicon film is deposited, so that the lower electrode 21 has electrical conductivity. On the other hand, the polysilicon film deposition process of the lower electrode 21 uses sputtering, chemical vapor deposition (CVD) or atomic layer deposition (ALD).

다음으로, 하부전극(21) 표면의 자연산화막(native oxide)을 제거하기 위해 전세정 공정을 진행한다. 이때, 전세정(pre-cleaning) 공정은 HF 혼합액(H2O/HF=10∼100배 희석된 HF 또는 NH4F/HF=5∼500배로 혼합)을 이용한다.Next, a pre-cleaning process is performed to remove the native oxide on the surface of the lower electrode 21. At this time, the pre-cleaning process uses a HF mixed liquid (H 2 O / HF = 10 to 100 times diluted HF or NH 4 F / HF = 5 to 500 times mixed).

여기서, HF 혼합액을 이용한 전세정 과정 전/후에 하부전극(21) 표면상의 무기물 또는 유기물 등의 이물질을 제거하기 위해 NH4OH 혼합액(NH4OH:H2O 2:H2O) 또는 H2SO4 혼합액(H2SO4:H2O2)을 사용하여 하부전극(21) 표면을 한번 더 세정할 수도 있 다.Here, in order to remove foreign substances such as inorganic or organic matter on the surface of the lower electrode 21 before and after the pre-cleaning process using the HF mixture solution, NH 4 OH mixture (NH 4 OH: H 2 O 2 : H 2 O) or H 2 The surface of the lower electrode 21 may be cleaned once more using the SO 4 mixed solution (H 2 SO 4 : H 2 O 2 ).

도 3b에 도시된 바와 같이, 하부전극(21) 상에 산화저항막(22)을 형성한다. 이때, 산화저항막(22)은 하부전극(21) 표면을 급속열질화(RTN)시켜 형성한 실리콘질화막으로, 후속 HfO2 공정시 하부전극(21) 표면의 산화를 방지하여 누설전류를 감소시키는 역할을 한다.As shown in FIG. 3B, an oxide resistance film 22 is formed on the lower electrode 21. At this time, the oxidation resistance film 22 is a silicon nitride film formed by rapid thermal nitriding (RTN) on the surface of the lower electrode 21, and prevents oxidation of the surface of the lower electrode 21 during the subsequent HfO 2 process to reduce leakage current. Play a role.

예컨대, 하부전극(21) 표면을 질화시키기 위한 급속열질화(RTN) 방법은, 급속열처리 챔버내에서 800℃∼1000℃의 NH3(25sccm∼250sccm) 분위기에서 30초∼120초동안 어닐링한다.For example, the rapid thermal nitriding (RTN) method for nitriding the surface of the lower electrode 21 is annealed for 30 seconds to 120 seconds in an NH 3 (25sccm to 250sccm) atmosphere at 800 ° C to 1000 ° C in a rapid heat treatment chamber.

도 3c에 도시된 바와 같이, 산화저항막(22) 상에 성장버퍼층(23)을 형성한다. 이때, 성장버퍼층(23)은 후속 HfO2 성장이 균일하게 이루어지도록 하기 위해 도입된 버퍼층으로, 원자층증착(ALD) 방법을 이용하여 증착한 실리콘산화막이다.As shown in FIG. 3C, the growth buffer layer 23 is formed on the oxidation resistant film 22. In this case, the growth buffer layer 23 is a buffer layer introduced to allow subsequent HfO 2 growth to be uniform, and is a silicon oxide film deposited using an atomic layer deposition (ALD) method.

성장버퍼층(23)이 되는 실리콘산화막의 원자층 증착 공정시, 프리커서(Precursor)로는 TCS(Trichlorosilane, SiHCl3) 또는 HCD(Hexachlorodisilane, Si2Cl6)를 사용하고, 기판온도는 상온∼200℃ 범위이며, 산화제는 H2O를 사용한다.In the atomic layer deposition process of the silicon oxide film to be the growth buffer layer 23, TCS (Trichlorosilane, SiHCl 3 ) or HCD (Hexachlorodisilane, Si 2 Cl 6 ) is used as a precursor, and the substrate temperature is from room temperature to 200 ° C. Range, the oxidant uses H 2 O.

예컨대, 기판온도를 상온∼200℃로 유지하면서 TCS 또는 HCD와 같은 실리콘소스를 챔버내에 0.1초∼10초 동안 흘려주는 실리콘소스 공급 스텝을 진행한다. 이처럼, 실리콘소스를 챔버내에 공급하면, 기판 표면에 실리콘소스가 흡착된다. 다음으로, 미반응 실리콘소스를 퍼지하기 위해서 질소 또는 아르곤 가스를 0.1초∼10초 동안 흘려주는 퍼지스텝을 진행한다. 이어서, 산화제인 H2O를 챔버내에 0.1∼10초 동안 흘려주는 산화제 공급 스텝을 진행한다. 이때, 기판에 흡착된 실리콘소스와 H2O의 반응하여 원자층 단위의 SiO2이 형성된다. 이어서, 미반응 H2O 및 반응부산물을 제거하기 위하여 질소 또는 아르곤가스를 챔버내에 흘려주는 퍼지스텝을 진행한다.For example, a silicon source supply step of flowing a silicon source such as TCS or HCD into the chamber for 0.1 to 10 seconds while maintaining the substrate temperature at room temperature to 200 ° C is performed. As such, when the silicon source is supplied into the chamber, the silicon source is adsorbed onto the substrate surface. Next, to purge the unreacted silicon source, a purge step of flowing nitrogen or argon gas for 0.1 to 10 seconds is performed. Subsequently, an oxidant supply step of flowing H 2 O as an oxidant into the chamber for 0.1 to 10 seconds is performed. At this time, SiO 2 in atomic layer units is formed by reacting the silicon source adsorbed on the substrate with H 2 O. Then, unreacted H 2 O And a purge step of flowing nitrogen or argon gas into the chamber to remove the reaction byproduct.

상술한 바와 같이, 실리콘소스 공급 스텝, 퍼지스텝, 산화제 공급 스텝 및 퍼지 스텝의 단계를 수회 반복하므로써 3Å∼10Å 두께의 스텝커버리지특성이 우수한 SiO2 박막을 형성한다.As described above, by repeating the steps of the silicon source supply step, the purge step, the oxidant supply step and the purge step several times, an SiO 2 thin film having excellent step coverage characteristics of 3 to 10 Å thickness is formed.

한편, 산화저항막(22)으로 사용된 실리콘질화막 위에서 산화공정을 통해 SiO2 박막을 형성하는 것은 매우 어려우나, 원자층증착방식을 이용하면 쉽게 SiO2 박막을 형성할 수 있고, 또한 스텝커버리지특성이 우수한 것으로 알려진 원자층증착방식을 이용하여 SiO2 박막을 형성하므로 후속 HfO2의 성장이 매우 균일해진다. On the other hand, it is very difficult to form a SiO 2 thin film on the silicon nitride film used as the oxidation resistance film 22 through an oxidation process, but by using the atomic layer deposition method, the SiO 2 thin film can be easily formed, and the step coverage characteristics are improved. The SiO 2 thin film is formed using atomic layer deposition, which is known to be excellent, so that the subsequent growth of HfO 2 is very uniform.

위와 같은 일련의 공정에 의해 형성한 성장버퍼층(23)인 SiO2 위에서는 HfO2가 고품질을 갖고 용이하게 성장할 수 있다.On SiO 2 , which is a growth buffer layer 23 formed by a series of processes as described above, HfO 2 may be easily grown with high quality.

도 3d에 도시된 바와 같이, 성장버퍼층(23) 상에 HfO2(24)를 증착한다. 이때, HfO2(24)는 원자층증착방식을 이용하여 50Å∼100Å 두께로 증착한다.As shown in FIG. 3D, HfO 2 24 is deposited on the growth buffer layer 23. At this time, HfO 2 (24) is deposited in a thickness of 50 kPa to 100 kPa using atomic layer deposition.

HfO2(24)의 원자층증착 공정시, 하프늄성분의 소스가스는 TEMAHf[Tetrakis- Ethyl-Methyl-Amino-Hafnium, Hf(N(CH3)C2H5)4] 등의 유기금속화합물을 전구체로 사용하고, 반응가스는 O3 또는 O2를 사용한다. 이때, 소스가스는 50sccm∼500sccm으로 흘려주고, 반응가스는 0.1slm∼1slm으로 흘려주며, 반응가스인 O3의 농도는 200±20g/m3이다. 그리고, HfO2(24)의 증착온도는 200℃∼300℃의 온도 범위이다.In the atomic layer deposition process of HfO 2 (24), the hafnium source gas may contain an organometallic compound such as TEMAHf [Tetrakis-Ethyl-Methyl-Amino-Hafnium, Hf (N (CH 3 ) C 2 H 5 ) 4 ], etc. It is used as a precursor and the reaction gas uses O 3 or O 2 . At this time, the source gas flows in 50sccm ~ 500sccm, the reaction gas flows in 0.1slm ~ 1slm, and the concentration of O 3 which is the reaction gas is 200 ± 20g / m 3 . The deposition temperature of HfO 2 (24) is in the temperature range of 200 ° C to 300 ° C.

그리고, HfO2(24)를 증착한 후에는 유전특성 확보를 위해 질소(N2) 분위기(유량:0.5slm∼ 1slm)의 상압 또는 감압 분위기에서 급속열처리한다. 이때, 급속열처리는 600℃∼800℃에서 1분∼3분동안 실시한다.After the deposition of HfO 2 (24), rapid heat treatment is performed at atmospheric pressure or reduced pressure in a nitrogen (N 2 ) atmosphere (flow rate: 0.5 slm to 1 slm) to ensure dielectric properties. At this time, rapid heat treatment is performed at 600 to 800 ° C for 1 to 3 minutes.

다음으로, HfO2(24) 상에 상부전극(25)을 형성한다. 이때, 상부전극(25)은 하부전극(21)과 동일하게 인(P) 또는 비소(As)와 같은 불순물이 도핑된 폴리실리콘막으로 형서한다.Next, the upper electrode 25 is formed on the HfO 2 24. In this case, the upper electrode 25 is shaped like a lower electrode 21 as a polysilicon film doped with impurities such as phosphorus (P) or arsenic (As).

상술한 본 발명의 캐패시터는 콘케이브(Concave) 구조 또는 실린더(Cylinder) 구조의 캐패시터에도 적용 가능하다.The above-described capacitor of the present invention can be applied to a capacitor having a concave structure or a cylinder structure.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 급속열질화를 통해 형성한 산화저항막을 구비하고, HfO2을 성장버퍼층(SiO2) 상에서 성장시키므로써, 하부전극 표면의 산화를 방지함과 동시에 막 품질이 우수한 HfO2를 얻을 수 있어 캐패시터의 신뢰성을 향상시킬 수 있는 효과가 있다.The present invention described above has an oxidation resistant film formed through rapid thermal nitriding and grows HfO 2 on a growth buffer layer (SiO 2 ), thereby preventing oxidation of the lower electrode surface and at the same time obtaining HfO 2 having excellent film quality. It can be effective to improve the reliability of the capacitor.

Claims (12)

하부전극;Lower electrode; 상기 하부전극 상의 산화저항막;An oxidation resistant film on the lower electrode; 상기 산화저항막 상의 성장버퍼층;A growth buffer layer on the oxidation resistant film; 상기 성장버퍼층 상의 하프늄옥사이드; 및Hafnium oxide on the growth buffer layer; And 상기 하프늄옥사이드 상의 상부전극을 포함하고,An upper electrode on the hafnium oxide, 상기 산화저항막은 상기 하프늄옥사이드 형성시 상기 하부전극의 산화를 방지하는 물질을 포함하고, 상기 성장버퍼층은 상기 하프늄옥사이드의 성장을 균일하게 하는 물질을 포함하는 The oxidation resistant film includes a material for preventing oxidation of the lower electrode when the hafnium oxide is formed, and the growth buffer layer includes a material for uniformly growing the hafnium oxide. 캐패시터.Capacitor. 청구항 2은(는) 설정등록료 납부시 포기되었습니다.Claim 2 has been abandoned due to the setting registration fee. 제1항에 있어서,The method of claim 1, 상기 산화저항막은 실리콘질화막이고, 상기 성장버퍼층은 실리콘산화막인 것을 특징으로 하는 캐패시터.The oxidation resistance film is a silicon nitride film, the growth buffer layer is a capacitor, characterized in that the silicon oxide film. 청구항 3은(는) 설정등록료 납부시 포기되었습니다.Claim 3 was abandoned when the setup registration fee was paid. 제2항에 있어서,The method of claim 2, 상기 성장버퍼층은, 3Å∼10Å 두께인 것을 특징으로 하는 캐패시터.The growth buffer layer is a capacitor, characterized in that the thickness of 3 ~ 10Å. 청구항 4은(는) 설정등록료 납부시 포기되었습니다.Claim 4 was abandoned when the registration fee was paid. 제1항 내지 제3항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 3, 상기 하부전극과 상기 상부전극은 불순물이 도핑된 폴리실리콘막인 것을 특징으로 하는 캐패시터.And the lower electrode and the upper electrode are polysilicon films doped with impurities. 하부전극을 형성하는 단계;Forming a lower electrode; 상기 하부전극 상에 산화저항막을 형성하는 단계;Forming an oxidation resistant film on the lower electrode; 상기 산화저항막 상에 성장 버퍼층을 형성하는 단계;Forming a growth buffer layer on the oxidation resistant film; 상기 성장 버퍼층 상에 하프늄옥사이드를 형성하는 단계; 및Forming hafnium oxide on the growth buffer layer; And 상기 하프늄옥사이드 상에 상부전극을 형성하는 단계를 포함하고,Forming an upper electrode on the hafnium oxide; 상기 산화저항막은 상기 하프늄옥사이드 형성시 상기 하부전극의 산화를 방지하는 물질을 포함하고, 상기 성장버퍼층은 상기 하프늄옥사이드의 성장을 균일하게 하는 물질을 포함하는The oxidation resistant film includes a material for preventing oxidation of the lower electrode when the hafnium oxide is formed, and the growth buffer layer includes a material for uniformly growing the hafnium oxide. 캐패시터의 제조 방법.Method of manufacturing a capacitor. 청구항 6은(는) 설정등록료 납부시 포기되었습니다.Claim 6 was abandoned when the registration fee was paid. 제5항에 있어서,The method of claim 5, 상기 성장 버퍼층은,The growth buffer layer, 실리콘산화막으로 형성하는 것을 특징으로 하는 캐패시터의 제조 방법.A method for producing a capacitor, characterized in that formed of a silicon oxide film. 청구항 7은(는) 설정등록료 납부시 포기되었습니다.Claim 7 was abandoned upon payment of a set-up fee. 제6항에 있어서,The method of claim 6, 상기 실리콘산화막은,The silicon oxide film, 원자층증착 방법을 이용하여 증착하는 것을 특징으로 하는 캐패시터의 제조 방법.A method for producing a capacitor, characterized in that the deposition using the atomic layer deposition method. 청구항 8은(는) 설정등록료 납부시 포기되었습니다.Claim 8 was abandoned when the registration fee was paid. 제7항에 있어서,The method of claim 7, wherein 상기 실리콘산화막은,The silicon oxide film, 실리콘소스로 TCS 또는 HCD를 이용하고, 산화제로 H2O를 이용하여 증착하는 것을 특징으로 하는 캐패시터의 제조 방법.A method of manufacturing a capacitor, characterized in that the deposition using TCS or HCD as a silicon source, H 2 O as an oxidizing agent. 청구항 9은(는) 설정등록료 납부시 포기되었습니다.Claim 9 was abandoned upon payment of a set-up fee. 제5항에 있어서,The method of claim 5, 상기 성장 버퍼층은,The growth buffer layer, 3Å∼10Å 두께로 형성하는 것을 특징으로 하는 캐패시터의 제조 방법.It is formed in the thickness of 3 microseconds-10 microseconds, The manufacturing method of a capacitor characterized by the above-mentioned. 청구항 10은(는) 설정등록료 납부시 포기되었습니다.Claim 10 was abandoned upon payment of a setup registration fee. 제5항 내지 제9항 중 어느 한 항에 있어서,The method according to any one of claims 5 to 9, 상기 산화저항막은, 실리콘질화막으로 형성하는 것을 특징으로 하는 캐패시터의 제조 방법.The oxidation resistance film is formed of a silicon nitride film. 청구항 11은(는) 설정등록료 납부시 포기되었습니다.Claim 11 was abandoned upon payment of a setup registration fee. 제10항에 있어서,The method of claim 10, 상기 실리콘질화막은, 급속열질화 방법으로 형성하는 것을 특징으로 하는 캐패시터의 제조 방법.The silicon nitride film is formed by a rapid thermal nitriding method. 청구항 12은(는) 설정등록료 납부시 포기되었습니다.Claim 12 was abandoned upon payment of a registration fee. 제11항에 있어서,The method of claim 11, 상기 급속열질화는, 800℃∼1000℃의 NH3 분위기에서 30초∼120초동안 진행하는 것을 특징으로 하는 캐패시터의 제조 방법.The rapid thermal nitriding is performed for 30 seconds to 120 seconds in an NH 3 atmosphere of 800 ° C to 1000 ° C.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010017820A (en) * 1999-08-14 2001-03-05 윤종용 Semiconductor device and manufacturing method thereof
KR20030059388A (en) * 2001-12-29 2003-07-10 주식회사 하이닉스반도체 Method of manufacturing capacitor for semiconductor device
KR20040057781A (en) * 2002-12-26 2004-07-02 주식회사 하이닉스반도체 Method of fabricating Hafnium dioxide Capacitor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010017820A (en) * 1999-08-14 2001-03-05 윤종용 Semiconductor device and manufacturing method thereof
KR20030059388A (en) * 2001-12-29 2003-07-10 주식회사 하이닉스반도체 Method of manufacturing capacitor for semiconductor device
KR20040057781A (en) * 2002-12-26 2004-07-02 주식회사 하이닉스반도체 Method of fabricating Hafnium dioxide Capacitor

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